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August 20, 2021 09:57
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two input glitch-free clock multiplexer for CPLD, in CUPL language, extracted from larger design
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| Name CLOCKSEL; | |
| PartNo U11; | |
| Revision 01; | |
| Date 11/27/2015; | |
| Designer Eric Smith; | |
| Company none; | |
| Assembly FDC; | |
| Location U11; | |
| Device v750c; /* ATF750CL */ | |
| Pin 1 = clk1; | |
| Pin 2 = clk2; | |
| Pin 11 = clksel; | |
| Pin 22 = clk_out; | |
| Node clk2_ff1; | |
| Node clk2_ff2; | |
| Node clk1_ff1; | |
| Node clk1_ff2; | |
| clk2_ff1.d = !clksel & !clk1_ff2; | |
| clk2_ff1.ck = clk2; | |
| clk2_ff1.sp = 'b'0; | |
| clk2_ff2.d = clk2_ff1; | |
| clk2_ff2.ck = clk2; | |
| clk2_ff2.sp = 'b'0; | |
| clk1_ff1.d = clksel & !clk2_ff2; | |
| clk1_ff1.ck = clk1; | |
| clk1_ff1.sp = 'b'0; | |
| clk1_ff2.d = clk1_ff1; | |
| clk1_ff2.ck = clk1; | |
| clk1_ff2.sp = 'b'0; | |
| clk_out = (clk2 & clk2_ff2) # (clk1 & clk1_ff2); |
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