Testbench for https://github.com/promach/UART/blob/master/rtl/baud_generator.v

baud_generator_tb.v

`timescale 1ps/100fs

module baud_generator_tb;
  reg clk;
  wire baud_out;

	baud_generator BG1
	(
      .clk(clk),
      .baud_out(baud_out)
	);

	initial
	begin
	    $dumpfile("baud_generator.vcd");
	    $dumpvars(0, baud_generator_tb);

            clk = 1;	

	    #1000000000 $finish;
	end

  always #10416.7 clk = !clk;  // 48Mhz has a clock period of (20833/2)ps
endmodule