HLS generated verilog RTL code for taylor series of 1/(1-x)

HLS_kernel_taylor.v

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7vx485tffg1761-2,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=4.108000,HLS_SYN_LAT=13,HLS_SYN_TPT=9,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=937,HLS_SYN_LUT=380}" *)

module kernel (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        stream_i0_V_V_dout,
        stream_i0_V_V_empty_n,
        stream_i0_V_V_read,
        stream_o0_V_V_din,
        stream_o0_V_V_full_n,
        stream_o0_V_V_write
);

parameter    ap_ST_fsm_pp0_stage0 = 9'd1;
parameter    ap_ST_fsm_pp0_stage1 = 9'd2;
parameter    ap_ST_fsm_pp0_stage2 = 9'd4;
parameter    ap_ST_fsm_pp0_stage3 = 9'd8;
parameter    ap_ST_fsm_pp0_stage4 = 9'd16;
parameter    ap_ST_fsm_pp0_stage5 = 9'd32;
parameter    ap_ST_fsm_pp0_stage6 = 9'd64;
parameter    ap_ST_fsm_pp0_stage7 = 9'd128;
parameter    ap_ST_fsm_pp0_stage8 = 9'd256;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [31:0] stream_i0_V_V_dout;
input   stream_i0_V_V_empty_n;
output   stream_i0_V_V_read;
output  [31:0] stream_o0_V_V_din;
input   stream_o0_V_V_full_n;
output   stream_o0_V_V_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg stream_i0_V_V_read;
reg stream_o0_V_V_write;

(* fsm_encoding = "none" *) reg   [8:0] ap_CS_fsm;
wire    ap_CS_fsm_pp0_stage0;
reg    ap_enable_reg_pp0_iter0;
reg    ap_enable_reg_pp0_iter1;
reg    ap_idle_pp0;
wire    ap_CS_fsm_pp0_stage8;
wire    ap_block_state9_pp0_stage8_iter0;
wire    ap_block_pp0_stage8_flag00011001;
reg    stream_i0_V_V_blk_n;
wire    ap_CS_fsm_pp0_stage1;
wire    ap_block_pp0_stage1_flag00000000;
reg   [0:0] tmp_reg_116;
reg    stream_o0_V_V_blk_n;
wire    ap_CS_fsm_pp0_stage4;
wire    ap_block_pp0_stage4_flag00000000;
reg   [0:0] ap_reg_pp0_iter1_tmp_reg_116;
reg    ap_block_state1_pp0_stage0_iter0;
wire    ap_block_state10_pp0_stage0_iter1;
reg    ap_block_pp0_stage0_flag00011001;
reg  signed [31:0] tmp_V_1_reg_120;
reg    ap_block_state2_pp0_stage1_iter0;
wire    ap_block_state11_pp0_stage1_iter1;
reg    ap_block_pp0_stage1_flag00011001;
reg  signed [31:0] ap_reg_pp0_iter1_tmp_V_1_reg_120;
wire   [31:0] grp_fu_85_p2;
reg   [31:0] p_s_reg_131;
wire    ap_block_state5_pp0_stage4_iter0;
reg    ap_block_state14_pp0_stage4_iter1;
reg    ap_block_pp0_stage4_flag00011001;
wire  signed [31:0] tmp2_fu_89_p2;
reg  signed [31:0] tmp2_reg_136;
wire    ap_CS_fsm_pp0_stage5;
wire    ap_block_state6_pp0_stage5_iter0;
wire    ap_block_pp0_stage5_flag00011001;
wire   [31:0] grp_fu_93_p2;
reg   [31:0] tmp3_reg_141;
wire  signed [31:0] tmp4_fu_97_p2;
reg  signed [31:0] tmp4_reg_146;
wire   [31:0] grp_fu_101_p2;
reg   [31:0] tmp5_reg_151;
wire    ap_CS_fsm_pp0_stage3;
wire    ap_block_state4_pp0_stage3_iter0;
wire    ap_block_state13_pp0_stage3_iter1;
wire    ap_block_pp0_stage3_flag00011001;
reg    ap_enable_reg_pp0_iter0_reg;
reg    ap_block_pp0_stage4_flag00011011;
wire    ap_block_pp0_stage8_flag00011011;
reg    ap_block_pp0_stage4_flag00001001;
wire    ap_CS_fsm_pp0_stage2;
wire    ap_block_pp0_stage2_flag00000000;
wire    ap_block_pp0_stage5_flag00000000;
wire    ap_CS_fsm_pp0_stage6;
wire    ap_block_pp0_stage6_flag00000000;
wire    ap_block_pp0_stage0_flag00000000;
wire   [31:0] tmp1_fu_105_p2;
reg    grp_fu_85_ce;
wire    ap_block_state3_pp0_stage2_iter0;
wire    ap_block_state12_pp0_stage2_iter1;
wire    ap_block_pp0_stage2_flag00011001;
reg    grp_fu_93_ce;
wire    ap_block_state7_pp0_stage6_iter0;
wire    ap_block_pp0_stage6_flag00011001;
wire    ap_block_state8_pp0_stage7_iter0;
wire    ap_block_pp0_stage7_flag00011001;
wire    ap_CS_fsm_pp0_stage7;
reg    grp_fu_101_ce;
reg   [8:0] ap_NS_fsm;
reg    ap_block_pp0_stage0_flag00011011;
reg    ap_idle_pp0_1to1;
reg    ap_block_pp0_stage1_flag00011011;
wire    ap_block_pp0_stage2_flag00011011;
wire    ap_block_pp0_stage3_flag00011011;
reg    ap_idle_pp0_0to0;
reg    ap_reset_idle_pp0;
wire    ap_block_pp0_stage5_flag00011011;
wire    ap_block_pp0_stage6_flag00011011;
wire    ap_block_pp0_stage7_flag00011011;
wire    ap_enable_pp0;

// power-on initialization
initial begin
#0 ap_CS_fsm = 9'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter0_reg = 1'b0;
end

kernel_mul_32s_32bkb #(
    .ID( 1 ),
    .NUM_STAGE( 3 ),
    .din0_WIDTH( 32 ),
    .din1_WIDTH( 32 ),
    .dout_WIDTH( 32 ))
kernel_mul_32s_32bkb_U1(
    .clk(ap_clk),
    .reset(ap_rst),
    .din0(tmp_V_1_reg_120),
    .din1(tmp_V_1_reg_120),
    .ce(grp_fu_85_ce),
    .dout(grp_fu_85_p2)
);

kernel_mul_32s_32bkb #(
    .ID( 1 ),
    .NUM_STAGE( 3 ),
    .din0_WIDTH( 32 ),
    .din1_WIDTH( 32 ),
    .dout_WIDTH( 32 ))
kernel_mul_32s_32bkb_U2(
    .clk(ap_clk),
    .reset(ap_rst),
    .din0(tmp_V_1_reg_120),
    .din1(tmp2_reg_136),
    .ce(grp_fu_93_ce),
    .dout(grp_fu_93_p2)
);

kernel_mul_32s_32bkb #(
    .ID( 1 ),
    .NUM_STAGE( 3 ),
    .din0_WIDTH( 32 ),
    .din1_WIDTH( 32 ),
    .dout_WIDTH( 32 ))
kernel_mul_32s_32bkb_U3(
    .clk(ap_clk),
    .reset(ap_rst),
    .din0(tmp_V_1_reg_120),
    .din1(tmp4_reg_146),
    .ce(grp_fu_101_ce),
    .dout(grp_fu_101_p2)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter0_reg <= 1'b0;
    end else begin
        if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin
            ap_enable_reg_pp0_iter0_reg <= ap_start;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011011 == 1'b0))) begin
            ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
        end else if (((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011011 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
            ap_enable_reg_pp0_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
        ap_reg_pp0_iter1_tmp_V_1_reg_120 <= tmp_V_1_reg_120;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        ap_reg_pp0_iter1_tmp_reg_116 <= tmp_reg_116;
        tmp_reg_116 <= stream_i0_V_V_empty_n;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_reg_116 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
        p_s_reg_131 <= grp_fu_85_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((tmp_reg_116 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage5) & (ap_block_pp0_stage5_flag00011001 == 1'b0))) begin
        tmp2_reg_136 <= tmp2_fu_89_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0) & (tmp_reg_116 == 1'd1))) begin
        tmp3_reg_141 <= grp_fu_93_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (tmp_reg_116 == 1'd1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        tmp4_reg_146 <= tmp4_fu_97_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0))) begin
        tmp5_reg_151 <= grp_fu_101_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_reg_116 == 1'd1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
        tmp_V_1_reg_120 <= stream_i0_V_V_dout;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin
        ap_enable_reg_pp0_iter0 = ap_start;
    end else begin
        ap_enable_reg_pp0_iter0 = ap_enable_reg_pp0_iter0_reg;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_idle_pp0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
        ap_idle_pp0 = 1'b1;
    end else begin
        ap_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if ((1'b0 == ap_enable_reg_pp0_iter0)) begin
        ap_idle_pp0_0to0 = 1'b1;
    end else begin
        ap_idle_pp0_0to0 = 1'b0;
    end
end

always @ (*) begin
    if ((1'b0 == ap_enable_reg_pp0_iter1)) begin
        ap_idle_pp0_1to1 = 1'b1;
    end else begin
        ap_idle_pp0_1to1 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage8) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage8_flag00011001 == 1'b0))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to0))) begin
        ap_reset_idle_pp0 = 1'b1;
    end else begin
        ap_reset_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)))) begin
        grp_fu_101_ce = 1'b1;
    end else begin
        grp_fu_101_ce = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage4) & (ap_block_pp0_stage4_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage3) & (ap_block_pp0_stage3_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage2) & (ap_block_pp0_stage2_flag00011001 == 1'b0)))) begin
        grp_fu_85_ce = 1'b1;
    end else begin
        grp_fu_85_ce = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_CS_fsm_pp0_stage8) & (ap_block_pp0_stage8_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage6) & (ap_block_pp0_stage6_flag00011001 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage7) & (ap_block_pp0_stage7_flag00011001 == 1'b0)))) begin
        grp_fu_93_ce = 1'b1;
    end else begin
        grp_fu_93_ce = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (ap_block_pp0_stage1_flag00000000 == 1'b0) & (tmp_reg_116 == 1'd1))) begin
        stream_i0_V_V_blk_n = stream_i0_V_V_empty_n;
    end else begin
        stream_i0_V_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (tmp_reg_116 == 1'd1) & (ap_block_pp0_stage1_flag00011001 == 1'b0))) begin
        stream_i0_V_V_read = 1'b1;
    end else begin
        stream_i0_V_V_read = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage4_flag00000000 == 1'b0) & (1'd1 == ap_reg_pp0_iter1_tmp_reg_116))) begin
        stream_o0_V_V_blk_n = stream_o0_V_V_full_n;
    end else begin
        stream_o0_V_V_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (ap_block_pp0_stage4_flag00011001 == 1'b0))) begin
        stream_o0_V_V_write = 1'b1;
    end else begin
        stream_o0_V_V_write = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_pp0_stage0 : begin
            if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & ~((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_1to1)))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        ap_ST_fsm_pp0_stage1 : begin
            if ((ap_block_pp0_stage1_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage1;
            end
        end
        ap_ST_fsm_pp0_stage2 : begin
            if ((ap_block_pp0_stage2_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage2;
            end
        end
        ap_ST_fsm_pp0_stage3 : begin
            if ((ap_block_pp0_stage3_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage3;
            end
        end
        ap_ST_fsm_pp0_stage4 : begin
            if (((ap_block_pp0_stage4_flag00011011 == 1'b0) & (ap_reset_idle_pp0 == 1'b0))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
            end else if (((ap_block_pp0_stage4_flag00011011 == 1'b0) & (1'b1 == ap_reset_idle_pp0))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage4;
            end
        end
        ap_ST_fsm_pp0_stage5 : begin
            if ((ap_block_pp0_stage5_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage5;
            end
        end
        ap_ST_fsm_pp0_stage6 : begin
            if ((ap_block_pp0_stage6_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage6;
            end
        end
        ap_ST_fsm_pp0_stage7 : begin
            if ((ap_block_pp0_stage7_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage8;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage7;
            end
        end
        ap_ST_fsm_pp0_stage8 : begin
            if ((ap_block_pp0_stage8_flag00011011 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage8;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd2];

assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd3];

assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd4];

assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd5];

assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd6];

assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd7];

assign ap_CS_fsm_pp0_stage8 = ap_CS_fsm[32'd8];

assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage0_flag00011001 = ((1'b0 == ap_start) & (1'b1 == ap_enable_reg_pp0_iter0));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011011 = ((1'b0 == ap_start) & (1'b1 == ap_enable_reg_pp0_iter0));
end

assign ap_block_pp0_stage1_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage1_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_116 == 1'd1) & (1'b0 == stream_i0_V_V_empty_n));
end

always @ (*) begin
    ap_block_pp0_stage1_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter0) & (tmp_reg_116 == 1'd1) & (1'b0 == stream_i0_V_V_empty_n));
end

assign ap_block_pp0_stage2_flag00000000 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage2_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage2_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage3_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage3_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage4_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage4_flag00001001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (1'b0 == stream_o0_V_V_full_n));
end

always @ (*) begin
    ap_block_pp0_stage4_flag00011001 = ((1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (1'b0 == stream_o0_V_V_full_n));
end

always @ (*) begin
    ap_block_pp0_stage4_flag00011011 = ((1'b1 == ap_enable_reg_pp0_iter1) & (1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (1'b0 == stream_o0_V_V_full_n));
end

assign ap_block_pp0_stage5_flag00000000 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage5_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage5_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage6_flag00000000 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage6_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage6_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage7_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage7_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage8_flag00011001 = ~(1'b1 == 1'b1);

assign ap_block_pp0_stage8_flag00011011 = ~(1'b1 == 1'b1);

assign ap_block_state10_pp0_stage0_iter1 = ~(1'b1 == 1'b1);

assign ap_block_state11_pp0_stage1_iter1 = ~(1'b1 == 1'b1);

assign ap_block_state12_pp0_stage2_iter1 = ~(1'b1 == 1'b1);

assign ap_block_state13_pp0_stage3_iter1 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state14_pp0_stage4_iter1 = ((1'd1 == ap_reg_pp0_iter1_tmp_reg_116) & (1'b0 == stream_o0_V_V_full_n));
end

always @ (*) begin
    ap_block_state1_pp0_stage0_iter0 = (1'b0 == ap_start);
end

always @ (*) begin
    ap_block_state2_pp0_stage1_iter0 = ((tmp_reg_116 == 1'd1) & (1'b0 == stream_i0_V_V_empty_n));
end

assign ap_block_state3_pp0_stage2_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state4_pp0_stage3_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state5_pp0_stage4_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state6_pp0_stage5_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state7_pp0_stage6_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state8_pp0_stage7_iter0 = ~(1'b1 == 1'b1);

assign ap_block_state9_pp0_stage8_iter0 = ~(1'b1 == 1'b1);

assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);

assign stream_o0_V_V_din = ($signed(tmp1_fu_105_p2) + $signed(ap_reg_pp0_iter1_tmp_V_1_reg_120));

assign tmp1_fu_105_p2 = (tmp5_reg_151 + 32'd1);

assign tmp2_fu_89_p2 = ($signed(tmp_V_1_reg_120) + $signed(p_s_reg_131));

assign tmp4_fu_97_p2 = ($signed(tmp_V_1_reg_120) + $signed(tmp3_reg_141));

endmodule //kernel