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Spidergon Networks On Chip
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| [tasks] | |
| proof | |
| cover | |
| [options] | |
| proof: mode prove | |
| proof: depth 10 | |
| cover: mode cover | |
| cover: depth 20 | |
| cover: append 12 | |
| [engines] | |
| smtbmc yices | |
| # smtbmc boolector | |
| # abc pdr | |
| # aiger avy | |
| # aiger suprove | |
| [script] | |
| read_verilog -formal -sv arbiter.v | |
| prep -top arbiter | |
| [files] | |
| arbiter.v |
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| // Credit: https://github.com/thomasrussellmurphy/stx_cookbook/blob/master/arbitration/arbiter.v | |
| // Copyright 2007 Altera Corporation. All rights reserved. | |
| // Altera products are protected under numerous U.S. and foreign patents, | |
| // maskwork rights, copyrights and other intellectual property laws. | |
| // | |
| // This reference design file, and your use thereof, is subject to and governed | |
| // by the terms and conditions of the applicable Altera Reference Design | |
| // License Agreement (either as signed by you or found at www.altera.com). By | |
| // using this reference design file, you indicate your acceptance of such terms | |
| // and conditions between you and Altera Corporation. In the event that you do | |
| // not agree with such terms and conditions, you may not use the reference | |
| // design file and please promptly destroy any copies you have made. | |
| // | |
| // This reference design file is being provided on an "as-is" basis and as an | |
| // accommodation and therefore all warranties, representations or guarantees of | |
| // any kind (whether express, implied or statutory) including, without | |
| // limitation, warranties of merchantability, non-infringement, or fitness for | |
| // a particular purpose, are specifically disclaimed. By making this reference | |
| // design file available, Altera expressly does not recommend, suggest or | |
| // require that this reference design file be used in combination with any | |
| // other product not provided by Altera. | |
| ///////////////////////////////////////////////////////////////////////////// | |
| // baeckler - 02-13-2007 | |
| // | |
| // 'base' is a one hot signal indicating the first request | |
| // that should be considered for a grant. Followed by higher | |
| // indexed requests, then wrapping around. | |
| // | |
| // https://www.reddit.com/r/FPGA/comments/axutbt/understanding_a_simple_roundrobin_arbiter_verilog/ | |
| module arbiter #(parameter WIDTH = 4) (clk, reset, req, grant); | |
| input clk, reset; | |
| input [WIDTH-1:0] req; | |
| output [WIDTH-1:0] grant; | |
| // 'grant' is one-hot vector, which means only one client request is granted/given green light to proceed | |
| // note that 'base' is one-hot vector, | |
| // 'base' signal helps round-robin arbiter to decide which 'req' to start servicing | |
| reg [WIDTH-1:0] base; | |
| wire [2*WIDTH-1:0] double_req = {req,req}; | |
| reg [2*WIDTH-1:0] double_grant; | |
| assign grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH]; | |
| // for reducing power consumption during the time when there is no client requests | |
| // by preventing signals from toggling when the arbiter is not in use. | |
| wire idle = (req == 0); | |
| always @(posedge clk) | |
| begin | |
| if(reset || idle) double_grant <= 0; | |
| else double_grant <= double_req & ~(double_req - {{(WIDTH){1'b0}}, base}); | |
| end | |
| reg [WIDTH-1:0] req_previous; | |
| always @(posedge clk) req_previous <= req; | |
| always @(*) | |
| begin | |
| // starts round-robin arbiter with req #0 getting prioritized first | |
| if(reset) base = 1; | |
| // 'grant' is a one-hot signal, but 'req' is not a one-hot signal | |
| // 'base' is a one-hot signal which rotates | |
| // after the corresponding 'req' had been granted/given permission to proceed) | |
| // Rotation wraps around upon reaching MSB | |
| else base = (grant[WIDTH-1]) ? 1 : (grant == 0) ? 1 : (grant << 1); | |
| end | |
| `ifdef FORMAL | |
| initial assume(reset); | |
| initial assume(req == 0); // only enable this assume() to test the cover() at line 100 properly | |
| genvar grant_num; | |
| generate | |
| for(grant_num = 0; grant_num < WIDTH; grant_num = grant_num + 1) | |
| always @(*) cover(first_clock_had_passed && grant[grant_num]); // covers grants to each of the clients' request | |
| endgenerate | |
| always @(posedge clk) cover(!$past(reset) && (grant == 0)); // covers the ability to go to an idle state | |
| // covers the ability to handle requests properly even with ALL requests ON | |
| always @(posedge clk) cover((&$past(req_previous)) && (&$past(req)) && (&req) && first_clock_had_passed && $past(first_clock_had_passed) && ((grant & $past(req)) == grant)); | |
| reg [WIDTH-1:0] grant_previous; | |
| always @(posedge clk) grant_previous <= grant; | |
| always @(posedge clk) cover(grant != grant_previous); // covers the ability to switch grants to any other requests | |
| always @(posedge clk) cover(first_clock_had_passed && $past(first_clock_had_passed) && (&req) && (req_previous == 4'b1100) && ($past(req_previous) == 4'b1011)); // covers round-robin ability | |
| `endif | |
| `ifdef FORMAL | |
| reg first_clock_had_passed; | |
| initial first_clock_had_passed = 0; | |
| always @(posedge clk) first_clock_had_passed <= 1; | |
| always @(posedge clk) | |
| begin | |
| if(first_clock_had_passed) | |
| begin | |
| if($past(reset) || $past(idle)) assert(grant == 0); | |
| else begin | |
| assert((grant & $past(req)) == grant); // $onehot(grant) equivalent in the case of rr arbiter | |
| if (|$past(req)) assert(grant != 0); | |
| end | |
| end | |
| end | |
| always @(*) | |
| begin | |
| // starts round-robin arbiter with req #0 getting prioritized first | |
| if(reset) assert(base == 1); | |
| // 'grant' is a one-hot signal, but 'req' is not a one-hot signal | |
| // 'base' is a one-hot signal which rotates | |
| // after the corresponding 'req' had been granted/given permission to proceed) | |
| // Rotation wraps around upon reaching MSB | |
| else begin | |
| assert(base == (grant[WIDTH-1]) ? 1 : (grant == 0) ? 1 : (grant << 1)); | |
| assert(base != 0); | |
| end | |
| end | |
| // assertions for round-robin capability | |
| `endif | |
| endmodule |
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| // Credit : https://www.eevblog.com/forum/fpga/understanding-linear-implementation-of-a-round-robin-arbiter/ | |
| module arbiter2 #(parameter WIDTH = 4) (clk, reset, req, grant); | |
| input clk, reset; | |
| input [WIDTH-1:0] req; | |
| output [WIDTH-1:0] grant; | |
| // 'grant' is one-hot vector, which means only one client request is granted/given green light to proceed | |
| // note that 'base' is one-hot vector, | |
| // 'base' signal helps round-robin arbiter to decide which 'req' to start servicing | |
| reg [WIDTH-1:0] base; | |
| always @(posedge clk) | |
| begin | |
| if(reset) base <= 1; | |
| else base <= (grant[WIDTH-1]) ? 1 : (grant == 0) ? base : ( grant << 1 ); | |
| end | |
| wire [WIDTH-1:0] priority_in; | |
| wire [(WIDTH << 1)-1:0] priority_out; // the two leftmost significant bit are left unused | |
| wire [WIDTH-1:0] granting = req & priority_in; | |
| wire [WIDTH-2:0] approval; // we only have (WIDTH-1) block F | |
| genvar index; | |
| generate | |
| for(index = 0; index < WIDTH; index = index + 1) | |
| begin | |
| if(index == WIDTH-1) assign grant[index] = (reset) ? 0 : granting[index]; | |
| else assign grant[index] = (reset) ? 0 : ( granting[index] | approval[index] ); | |
| if(index < (WIDTH-1)) assign approval[index] = ( priority_out[index+WIDTH-1] & req[index] ); | |
| if(index > 0) assign priority_in[index] = ( base[index] | priority_out[index-1] ); | |
| else assign priority_in[index] = base[index]; | |
| end | |
| endgenerate | |
| genvar priority_index; | |
| generate | |
| for(priority_index = 0; priority_index < (WIDTH << 1); priority_index = priority_index + 1) | |
| begin : out_priority | |
| if(priority_index < (WIDTH)) | |
| assign priority_out[priority_index] = (~req[priority_index]) & priority_in[priority_index]; | |
| else assign priority_out[priority_index] = (~req[priority_index-WIDTH]) & priority_out[priority_index-1]; | |
| end | |
| endgenerate | |
| `ifdef FORMAL | |
| initial assume(reset); | |
| initial assume(req == 0); // only enable this assume() to test the cover() at line 100 properly | |
| genvar grant_num; | |
| generate | |
| for(grant_num = 0; grant_num < WIDTH; grant_num = grant_num + 1) | |
| always @(*) cover(first_clock_had_passed && grant[grant_num]); // covers grants to each of the clients' request | |
| endgenerate | |
| reg [WIDTH-1:0] req_previous; | |
| always @(posedge clk) | |
| begin | |
| if(reset) req_previous <= 0; | |
| else req_previous <= req; | |
| end | |
| reg [WIDTH-1:0] grant_previous; | |
| always @(posedge clk) | |
| begin | |
| if(reset) grant_previous <= 0; | |
| else grant_previous <= grant; | |
| end | |
| always @(posedge clk) | |
| begin | |
| if(first_clock_had_passed) | |
| begin | |
| cover(!$past(reset) && (grant == 0)); // covers the ability to go to an idle state | |
| // covers the ability to handle requests properly even with ALL requests ON | |
| cover((&$past(req_previous)) && (&$past(req)) && (&req) && $past(first_clock_had_passed) && ((grant & $past(req)) == grant)); | |
| cover(grant != grant_previous); // covers the ability to switch grants to any other requests | |
| cover(first_clock_had_passed && $past(first_clock_had_passed) && (&req) && (req_previous == 4'b1100) && ($past(req_previous) == 4'b1011)); // covers round-robin ability | |
| end | |
| end | |
| `endif | |
| `ifdef FORMAL | |
| reg first_clock_had_passed; | |
| initial first_clock_had_passed = 0; | |
| always @(posedge clk) first_clock_had_passed <= 1; | |
| // https://graphics.stanford.edu/~seander/bithacks.html#DetermineIfPowerOf2 | |
| wire grant_is_one_hot = (grant != 0) && ((grant & (grant - 1)) == 0); | |
| wire base_is_one_hot = (base != 0) && ((base & (base - 1)) == 0); | |
| // assertions for round-robin capability | |
| always @(*) | |
| begin | |
| if(reset) assert(grant == 0); | |
| else begin | |
| if (|req) assert(grant_is_one_hot); | |
| else assert(grant == 0); | |
| end | |
| end | |
| always @(posedge clk) | |
| begin | |
| if(first_clock_had_passed) | |
| begin | |
| // starts round-robin arbiter with req #0 getting prioritized first | |
| if($past(reset)) assert(base == 1); | |
| // 'grant' is a one-hot signal, but 'req' is not a one-hot signal | |
| // 'base' is a one-hot signal which rotates | |
| // after the corresponding 'req' had been granted/given permission to proceed) | |
| // Rotation wraps around upon reaching MSB | |
| else begin | |
| assert(base == $past(grant[WIDTH-1]) ? 1 : ($past(grant) == 0) ? $past(base) : ($past(grant) << 1) ); | |
| assert(base_is_one_hot); | |
| end | |
| end | |
| end | |
| genvar f_index; | |
| generate | |
| for(f_index = 0; f_index < WIDTH; f_index = f_index + 1) | |
| begin | |
| always @(*) | |
| begin | |
| if(reset) assert( grant[f_index] == 0 ); | |
| else begin | |
| if(f_index == WIDTH-1) assert( grant[f_index] == granting[f_index] ); | |
| else assert( grant[f_index] == ( granting[f_index] | approval[f_index] ) ); | |
| end | |
| if(f_index < (WIDTH-1)) assert( approval[f_index] == ( priority_out[f_index+WIDTH-1] & req[f_index] )); | |
| if(f_index > 0) assert( priority_in[f_index] == (base[f_index] | priority_out[f_index-1] )); | |
| else assert( priority_in[f_index] == base[f_index] ); | |
| end | |
| end | |
| endgenerate | |
| genvar f_priority_index; | |
| generate | |
| for(f_priority_index = 0; f_priority_index < (WIDTH << 1); f_priority_index = f_priority_index + 1) | |
| begin : out_priority | |
| always @(*) | |
| begin | |
| if(f_priority_index < (WIDTH)) | |
| assert( priority_out[f_priority_index] == | |
| ((~req[f_priority_index]) & priority_in[f_priority_index]) ); | |
| else assert( priority_out[f_priority_index] == | |
| ((~req[f_priority_index-WIDTH]) & priority_out[f_priority_index-1]) ); | |
| end | |
| end | |
| endgenerate | |
| `endif | |
| endmodule |
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| [*] | |
| [*] GTKWave Analyzer v3.3.94 (w)1999-2018 BSI | |
| [*] Sat Aug 17 15:03:51 2019 | |
| [*] | |
| [dumpfile] "/home/phung/Downloads/spidergon/arbiter_cover/engine_0/trace5.vcd" | |
| [dumpfile_mtime] "Sat Aug 17 15:01:44 2019" | |
| [dumpfile_size] 1749 | |
| [savefile] "/home/phung/Downloads/spidergon/arbiter_cover.gtkw" | |
| [timestart] 0 | |
| [size] 960 995 | |
| [pos] -51 -1 | |
| *-4.955800 20 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | |
| [sst_width] 51 | |
| [signals_width] 332 | |
| [sst_expanded] 0 | |
| [sst_vpaned_height] 141 | |
| @28 | |
| smt_clock | |
| @420 | |
| smt_step | |
| @28 | |
| arbiter.base[3:0] | |
| arbiter.clk | |
| arbiter.double_grant[7:0] | |
| arbiter.double_req[7:0] | |
| arbiter.first_clock_had_passed | |
| @29 | |
| arbiter.grant[3:0] | |
| @28 | |
| arbiter.grant_previous[3:0] | |
| arbiter.idle | |
| @29 | |
| arbiter.req[3:0] | |
| @28 | |
| arbiter.req_previous[3:0] | |
| arbiter.reset | |
| [pattern_trace] 1 | |
| [pattern_trace] 0 |
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| [*] | |
| [*] GTKWave Analyzer v3.3.94 (w)1999-2018 BSI | |
| [*] Sat Aug 17 14:50:15 2019 | |
| [*] | |
| [dumpfile] "/home/phung/Downloads/spidergon/arbiter_proof/engine_0/trace_induct.vcd" | |
| [dumpfile_mtime] "Sat Aug 17 14:49:41 2019" | |
| [dumpfile_size] 2199 | |
| [savefile] "/home/phung/Downloads/spidergon/arbiter_induction.gtkw" | |
| [timestart] 0 | |
| [size] 960 995 | |
| [pos] -1 -1 | |
| *-5.510494 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | |
| [sst_width] 51 | |
| [signals_width] 364 | |
| [sst_expanded] 0 | |
| [sst_vpaned_height] 141 | |
| @28 | |
| smt_clock | |
| @24 | |
| smt_step | |
| @28 | |
| arbiter.base[3:0] | |
| arbiter.clk | |
| arbiter.double_grant[7:0] | |
| arbiter.double_req[7:0] | |
| arbiter.first_clock_had_passed | |
| @29 | |
| arbiter.grant[3:0] | |
| @28 | |
| arbiter.grant_previous[3:0] | |
| arbiter.idle | |
| @29 | |
| arbiter.req[3:0] | |
| @28 | |
| arbiter.req_previous[3:0] | |
| arbiter.reset | |
| [pattern_trace] 1 | |
| [pattern_trace] 0 |
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| // Credits : https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v | |
| module clock_gate ( | |
| // OUTPUTs | |
| gclk, // Gated clock | |
| // INPUTs | |
| clk, // Clock | |
| enable_in // Clock enable | |
| ); | |
| // OUTPUTs | |
| //========= | |
| output gclk; // Gated clock | |
| // INPUTs | |
| //========= | |
| input clk; // Clock | |
| input enable_in; // Clock enable | |
| //============================================================================= | |
| // CLOCK GATE: LATCH + AND | |
| //============================================================================= | |
| // LATCH the enable signal | |
| reg enable_latch; | |
| always @(clk or enable_in) | |
| begin | |
| enable_latch <= 1; | |
| if (~clk) | |
| enable_latch <= enable_in; | |
| end | |
| // AND gate | |
| assign gclk = (clk & enable_latch); | |
| endmodule |
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| module NoC | |
| #( | |
| `ifdef FORMAL | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=8, | |
| parameter NODE_BUFFER_WIDTH=16, | |
| `else | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=16, | |
| parameter NODE_BUFFER_WIDTH=32, // a single vc buffer can hold 2 flits at one time | |
| `endif | |
| parameter NUM_OF_VIRTUAL_CHANNELS=2 // 2 vc for each input ports of each node | |
| ) | |
| (clk, reset); | |
| input clk, reset; | |
| reg [NUM_OF_NODES*FLIT_TOTAL_WIDTH-1:0] data_input; | |
| wire [FLIT_DATA_WIDTH-1:0] data_output; | |
| localparam HEAD_TAIL = 2; | |
| localparam FLIT_TOTAL_WIDTH = HEAD_TAIL+FLIT_DATA_WIDTH; | |
| // the most significant two bits are to indicate head and/or tail flits, | |
| // followed by dest_node and flit_data_payload | |
| // See http://www.lisnoc.org/packets.html | |
| // 01 = head_flit , 10 = data_flit (body_flit), 00 = tail_flit, 11 = flit_without_data_payload | |
| localparam HEAD_FLIT = 2'b01; | |
| localparam HEADER = 2'b11; // flit_without_data_payload | |
| localparam BODY_FLIT = 2'b10; | |
| localparam TAIL_FLIT = 2'b00; | |
| spidergon_top | |
| #( | |
| .NUM_OF_NODES(NUM_OF_NODES), | |
| .FLIT_DATA_WIDTH(FLIT_DATA_WIDTH), | |
| .NODE_BUFFER_WIDTH(NODE_BUFFER_WIDTH), | |
| .NUM_OF_VIRTUAL_CHANNELS(NUM_OF_VIRTUAL_CHANNELS) | |
| ) | |
| sp(.clk(clk), .reset(reset), .data_input(data_input), .data_output(data_output)); | |
| //`define ONE_NODE_SENDING 1 | |
| //`define TWO_NODES_SENDING 1 | |
| //`define FOUR_NODES_SENDING 1 | |
| `define ALL_NODES_SENDING 1 | |
| generate | |
| genvar node_num; | |
| for(node_num = 0; node_num < NUM_OF_NODES; node_num = node_num + 1) | |
| begin : DATA_INPUT | |
| `ifdef ONE_NODE_SENDING | |
| always@(posedge clk) | |
| begin | |
| if(node_num == 1) // send data from node 1 to node 0 | |
| begin | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {HEADER, node_num[FLIT_DATA_WIDTH-1:0]}; | |
| end | |
| else data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {TAIL_FLIT, {FLIT_DATA_WIDTH{1'b0}}}; | |
| end | |
| `endif | |
| `ifdef TWO_NODES_SENDING | |
| // send data from nodes 1,2 to node 0, | |
| // to verify virtual channel reservation logic | |
| // given that both nodes 1 and 2 need to compete for virtual channels | |
| // at the same port (clockwise) | |
| always@(posedge clk) | |
| begin | |
| if((node_num == 1) || (node_num == 2)) | |
| begin | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {HEADER, node_num[FLIT_DATA_WIDTH-1:0]}; | |
| end | |
| else data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {TAIL_FLIT, {FLIT_DATA_WIDTH{1'b0}}}; | |
| end | |
| `endif | |
| `ifdef FOUR_NODES_SENDING | |
| // send data from nodes 1,2 (clockwise) and 6,7 (anti-clockwise) to node 0, | |
| // to verify virtual channel reservation logic | |
| // given that both nodes 1 and 2 need to compete for virtual channels | |
| // at the same port (clockwise) | |
| // Same competition for both nodes 6 and 7 | |
| always@(posedge clk) | |
| begin | |
| if((node_num == 1) || (node_num == 2) || (node_num == 6) || (node_num == 7)) | |
| begin | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {HEADER, node_num[FLIT_DATA_WIDTH-1:0]}; | |
| end | |
| else data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {TAIL_FLIT, {FLIT_DATA_WIDTH{1'b0}}}; | |
| end | |
| `endif | |
| `ifdef ALL_NODES_SENDING | |
| always@(posedge clk) | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH] <= | |
| {HEADER, node_num[FLIT_DATA_WIDTH-1:0]}; | |
| `endif | |
| end | |
| endgenerate | |
| endmodule |
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| // Credit : https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/oh_to_idx.sv | |
| // | |
| // Copyright 2011-2015 Jeff Bush | |
| // | |
| // Licensed under the Apache License, Version 2.0 (the "License"); | |
| // you may not use this file except in compliance with the License. | |
| // You may obtain a copy of the License at | |
| // | |
| // http://www.apache.org/licenses/LICENSE-2.0 | |
| // | |
| // Unless required by applicable law or agreed to in writing, software | |
| // distributed under the License is distributed on an "AS IS" BASIS, | |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |
| // See the License for the specific language governing permissions and | |
| // limitations under the License. | |
| // | |
| // | |
| // Convert a one-hot signal to a binary index corresponding to the active bit. | |
| // (Binary encoder) | |
| // If DIRECTION is "LSB0", index 0 corresponds to the least significant bit | |
| // If "MSB0", index 0 corresponds to the most significant bit | |
| // | |
| module oh_to_idx | |
| #(parameter NUM_SIGNALS = 4, | |
| parameter DIRECTION = "LSB0", | |
| parameter INDEX_WIDTH = $clog2(NUM_SIGNALS)) | |
| (input[NUM_SIGNALS - 1:0] one_hot, | |
| output reg[INDEX_WIDTH - 1:0] index); | |
| integer oh_index; | |
| always @(*) | |
| begin : convert | |
| index = 0; | |
| for (oh_index = 0; oh_index < NUM_SIGNALS; oh_index=oh_index+1) | |
| begin | |
| if (one_hot[oh_index]) | |
| begin | |
| if (DIRECTION == "LSB0") | |
| index = index | oh_index[INDEX_WIDTH - 1:0]; // Use 'or' to avoid synthesizing priority encoder | |
| else | |
| index = index | (NUM_SIGNALS[INDEX_WIDTH - 1:0] - oh_index[INDEX_WIDTH - 1:0] - 1); | |
| end | |
| end | |
| end | |
| endmodule |
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| // shortest path routing algorithm of Spidergon | |
| module router | |
| #(parameter | |
| `ifdef FORMAL | |
| NUM_OF_NODES=8 | |
| `else | |
| NUM_OF_NODES=32 | |
| `endif | |
| ) | |
| (dest_node, current_node, direction); | |
| localparam DIRECTION_WIDTH = 2; | |
| localparam STOP = 3; | |
| localparam ACROSS = 2; | |
| localparam CLOCKWISE = 1; | |
| localparam ANTI_CLOCKWISE = 0; | |
| //input clk; | |
| input [$clog2(NUM_OF_NODES)-1:0] dest_node, current_node; | |
| output reg [DIRECTION_WIDTH-1:0] direction; // stop, clockwise, anti-clockwise, across | |
| // RelAd = ((dest-current) mod (NUM_OF_NODES)) * 4 | |
| // https://en.wikipedia.org/wiki/Modulo_operation#Performance_issues | |
| // x % 2^n == x < 0 ? x | ~(2^n - 1) : x & (2^n - 1) | |
| wire signed [$clog2(NUM_OF_NODES)-1:0] diff; | |
| wire [$clog2(NUM_OF_NODES)-1:0] RelAd; | |
| assign diff = dest_node - current_node; | |
| /* verilator lint_off WIDTH */ | |
| assign RelAd = (diff < 0) ? (diff | ~(NUM_OF_NODES-1)) : (diff & (NUM_OF_NODES-1)); | |
| /* verilator lint_on WIDTH */ | |
| localparam SHIFT_BY_TWO = 2; // multiply by four | |
| localparam NUM_OF_NODES_TIMES_THREE = 3*NUM_OF_NODES; | |
| localparam NUM_OF_NODES_TIMES_FOUR = 4*NUM_OF_NODES; | |
| /* verilator lint_off WIDTH */ | |
| wire [$clog2(NUM_OF_NODES)+1:0] RelAd_2 = (RelAd << SHIFT_BY_TWO); | |
| /* verilator lint_on WIDTH */ | |
| always @(*) | |
| begin | |
| // https://www.xilinx.com/support/answers/64777.html | |
| /*case(RelAd << SHIFT_BY_TWO) inside | |
| [0:0] : direction <= STOP; | |
| [NUM_OF_NODES:1] : direction <= CLOCKWISE; | |
| [NUM_OF_NODES_TIMES_FOUR:NUM_OF_NODES_TIMES_THREE] : direction <= ANTI_CLOCKWISE; | |
| default : direction <= ACROSS; | |
| endcase*/ | |
| // https://www.reddit.com/r/yosys/comments/b0vaml/system_verilog_case_inside_range_expression/ | |
| if(RelAd_2 == 0) direction = STOP; | |
| else if((RelAd_2 > 0) && (RelAd_2 <= NUM_OF_NODES)) direction = CLOCKWISE; | |
| else if((RelAd_2 >= NUM_OF_NODES_TIMES_THREE) && (RelAd_2 <= NUM_OF_NODES_TIMES_FOUR)) | |
| direction = ANTI_CLOCKWISE; | |
| else direction = ACROSS; | |
| end | |
| endmodule |
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| [*] | |
| [*] GTKWave Analyzer v3.3.94 (w)1999-2018 BSI | |
| [*] Mon Sep 30 13:30:01 2019 | |
| [*] | |
| [dumpfile] "/home/phung/Downloads/spidergon/spidergon.vcd" | |
| [dumpfile_mtime] "Mon Sep 30 11:18:27 2019" | |
| [dumpfile_size] 106965 | |
| [savefile] "/home/phung/Downloads/spidergon/spidergon.gtkw" | |
| [timestart] 21 | |
| [size] 960 995 | |
| [pos] 909 -1 | |
| *-5.446210 35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | |
| [treeopen] test_spidergon. | |
| [treeopen] test_spidergon.noc. | |
| [treeopen] test_spidergon.noc.sp. | |
| [treeopen] test_spidergon.noc.sp.NODES[0]. | |
| [sst_width] 51 | |
| [signals_width] 563 | |
| [sst_expanded] 0 | |
| [sst_vpaned_height] 381 | |
| @28 | |
| test_spidergon.clk | |
| test_spidergon.noc.clk | |
| @22 | |
| test_spidergon.noc.data_input[143:0] | |
| test_spidergon.noc.data_output[15:0] | |
| @28 | |
| test_spidergon.noc.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.clk | |
| test_spidergon.noc.sp.NODES[0].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.data_input[17:0] | |
| @23 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_input_anticlockwise[17:0] | |
| @29 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_input_are_valid[2:0] | |
| @23 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_input_clockwise[17:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[0].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[0].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[0].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[0].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[0].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.clk | |
| test_spidergon.noc.sp.NODES[1].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[1].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[1].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[1].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[1].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[1].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.clk | |
| test_spidergon.noc.sp.NODES[2].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[2].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[2].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[2].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[2].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[2].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.clk | |
| test_spidergon.noc.sp.NODES[3].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[3].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[3].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[3].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[3].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[3].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.clk | |
| test_spidergon.noc.sp.NODES[4].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[4].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[4].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[4].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[4].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[4].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.clk | |
| test_spidergon.noc.sp.NODES[5].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[5].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[5].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[5].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[5].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[5].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.clk | |
| test_spidergon.noc.sp.NODES[6].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[6].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[6].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[6].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[6].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[6].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].prev_vc | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[0].stop_flow | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].prev_vc | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[1].stop_flow | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[0].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].dequeue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].enqueue_en | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.count[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.dequeue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.empty | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_en | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.enqueue_value[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.full | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.rd_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].VIRTUAL_CHANNELS[1].fifo.wr_addr[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].adjacent_nodes_vc_are_reserved_and_not_full[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].granted_vc_enqueue[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].output_flit_type[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].prev_vc | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].previous_vc[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.base[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.grant[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.idle | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.req[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rr_arb_data_to_vc.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.RelAd[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.RelAd_2[4:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.current_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.dest_node[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.diff[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].rt.direction[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.PORTS[2].stop_flow | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.adjacent_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.adjacent_nodes_are_ready[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.clk | |
| test_spidergon.noc.sp.NODES[7].SPnode.current_node[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.current_node_is_ready[5:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.current_node_vc_are_full[5:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.data_input[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_input_across[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_input_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_input_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_input_clockwise[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_output_across[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_output_anticlockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_output_are_valid[2:0] | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.flit_data_output_clockwise[17:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.granted_port[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.granted_port_index[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.granted_vc[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.granted_vc_index | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.input_flit_type[5:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.node_data_from_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.node_data_to_cpu[17:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.out_port_num[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.outstanding_requests_in_multiple_ports[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.past_req_port[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.port_index.index[1:0] | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.port_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.port_index.one_hot[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.req_port[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.requests_from_multiple_ports | |
| test_spidergon.noc.sp.NODES[7].SPnode.requests_in_ports_have_been_served[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.reset_previously | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.base[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.double_grant[5:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.double_req[5:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.grant[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.req[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.req_previous[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_port_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.base[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.clk | |
| @22 | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.double_grant[3:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.double_req[3:0] | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.grant[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.idle | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.req[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.req_previous[1:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.rr_arb_vc_to_cpu.reset | |
| test_spidergon.noc.sp.NODES[7].SPnode.valid_output[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.valid_output_previously[2:0] | |
| test_spidergon.noc.sp.NODES[7].SPnode.vc_index.index | |
| @420 | |
| test_spidergon.noc.sp.NODES[7].SPnode.vc_index.oh_index | |
| @28 | |
| test_spidergon.noc.sp.NODES[7].SPnode.vc_index.one_hot[1:0] | |
| test_spidergon.noc.sp.clk | |
| @22 | |
| test_spidergon.noc.sp.data_input[143:0] | |
| test_spidergon.noc.sp.data_output[15:0] | |
| @28 | |
| test_spidergon.noc.sp.reset | |
| test_spidergon.reset | |
| [pattern_trace] 1 | |
| [pattern_trace] 0 |
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Learn more about bidirectional Unicode characters
| [tasks] | |
| proof | |
| cover | |
| [options] | |
| proof: mode prove | |
| proof: depth 10 | |
| cover: mode cover | |
| cover: depth 7 | |
| cover: append 3 | |
| [engines] | |
| smtbmc yices | |
| # smtbmc boolector | |
| # abc pdr | |
| # aiger avy | |
| # aiger suprove | |
| [script] | |
| read_verilog -formal spidergon_top.v | |
| read_verilog -formal spidergon_node.v | |
| read_verilog -formal router.v | |
| read_verilog -formal arbiter.v | |
| read_verilog -formal sync_fifo.v | |
| read_verilog -formal oh_to_idx.v | |
| prep -top spidergon_top | |
| [files] | |
| spidergon_top.v | |
| spidergon_node.v | |
| router.v | |
| arbiter.v | |
| sync_fifo.v | |
| oh_to_idx.v |
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Learn more about bidirectional Unicode characters
| read_verilog NoC.v | |
| read_verilog spidergon_top.v | |
| read_verilog spidergon_node.v | |
| read_verilog router.v | |
| read_verilog arbiter.v | |
| read_verilog sync_fifo.v | |
| read_verilog oh_to_idx.v | |
| synth_ice40 -flatten -top NoC -json spidergon.json | |
| abc -g NAND | |
| ltp t:SB_DFF* %n | |
| stat |
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Learn more about bidirectional Unicode characters
| [*] | |
| [*] GTKWave Analyzer v3.3.94 (w)1999-2018 BSI | |
| [*] Sat Aug 3 15:51:03 2019 | |
| [*] | |
| [dumpfile] "/home/phung/Downloads/spidergon/spidergon_proof/engine_0/trace.vcd" | |
| [dumpfile_mtime] "Sat Aug 3 15:49:07 2019" | |
| [dumpfile_size] 26557 | |
| [savefile] "/home/phung/Downloads/spidergon/spidergon_bmc.gtkw" | |
| [timestart] 0 | |
| [size] 960 995 | |
| [pos] -51 -1 | |
| *-4.278380 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | |
| [sst_width] 50 | |
| [signals_width] 326 | |
| [sst_expanded] 0 | |
| [sst_vpaned_height] 278 | |
| @28 | |
| smt_clock | |
| @420 | |
| smt_step | |
| @22 | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6278<0>.$genblock$spidergon_router.v:259$6281<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6278<0>.$genblock$spidergon_router.v:259$6281<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6278<0>.$genblock$spidergon_router.v:259$6295<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6278<0>.$genblock$spidergon_router.v:259$6295<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6310<1>.$genblock$spidergon_router.v:259$6313<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6310<1>.$genblock$spidergon_router.v:259$6313<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6310<1>.$genblock$spidergon_router.v:259$6327<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6310<1>.$genblock$spidergon_router.v:259$6327<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6342<2>.$genblock$spidergon_router.v:259$6345<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6342<2>.$genblock$spidergon_router.v:259$6345<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6342<2>.$genblock$spidergon_router.v:259$6359<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$1<0>./SProuter.\$genblock$spidergon_router.v:225$6342<2>.$genblock$spidergon_router.v:259$6359<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5694<0>.$genblock$spidergon_router.v:259$5697<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5694<0>.$genblock$spidergon_router.v:259$5697<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5694<0>.$genblock$spidergon_router.v:259$5711<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5694<0>.$genblock$spidergon_router.v:259$5711<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5726<1>.$genblock$spidergon_router.v:259$5729<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5726<1>.$genblock$spidergon_router.v:259$5729<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5726<1>.$genblock$spidergon_router.v:259$5743<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5726<1>.$genblock$spidergon_router.v:259$5743<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5758<2>.$genblock$spidergon_router.v:259$5761<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5758<2>.$genblock$spidergon_router.v:259$5761<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5758<2>.$genblock$spidergon_router.v:259$5775<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$35<1>./SProuter.\$genblock$spidergon_router.v:225$5758<2>.$genblock$spidergon_router.v:259$5775<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5110<0>.$genblock$spidergon_router.v:259$5113<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5110<0>.$genblock$spidergon_router.v:259$5113<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5110<0>.$genblock$spidergon_router.v:259$5127<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5110<0>.$genblock$spidergon_router.v:259$5127<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5142<1>.$genblock$spidergon_router.v:259$5145<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5142<1>.$genblock$spidergon_router.v:259$5145<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5142<1>.$genblock$spidergon_router.v:259$5159<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5142<1>.$genblock$spidergon_router.v:259$5159<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5174<2>.$genblock$spidergon_router.v:259$5177<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5174<2>.$genblock$spidergon_router.v:259$5177<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5174<2>.$genblock$spidergon_router.v:259$5191<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$69<2>./SProuter.\$genblock$spidergon_router.v:225$5174<2>.$genblock$spidergon_router.v:259$5191<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4526<0>.$genblock$spidergon_router.v:259$4529<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4526<0>.$genblock$spidergon_router.v:259$4529<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4526<0>.$genblock$spidergon_router.v:259$4543<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4526<0>.$genblock$spidergon_router.v:259$4543<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4558<1>.$genblock$spidergon_router.v:259$4561<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4558<1>.$genblock$spidergon_router.v:259$4561<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4558<1>.$genblock$spidergon_router.v:259$4575<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4558<1>.$genblock$spidergon_router.v:259$4575<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4590<2>.$genblock$spidergon_router.v:259$4593<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4590<2>.$genblock$spidergon_router.v:259$4593<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4590<2>.$genblock$spidergon_router.v:259$4607<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$103<3>./SProuter.\$genblock$spidergon_router.v:225$4590<2>.$genblock$spidergon_router.v:259$4607<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3942<0>.$genblock$spidergon_router.v:259$3945<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3942<0>.$genblock$spidergon_router.v:259$3945<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3942<0>.$genblock$spidergon_router.v:259$3959<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3942<0>.$genblock$spidergon_router.v:259$3959<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3974<1>.$genblock$spidergon_router.v:259$3977<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3974<1>.$genblock$spidergon_router.v:259$3977<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3974<1>.$genblock$spidergon_router.v:259$3991<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$3974<1>.$genblock$spidergon_router.v:259$3991<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$4006<2>.$genblock$spidergon_router.v:259$4009<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$4006<2>.$genblock$spidergon_router.v:259$4009<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$4006<2>.$genblock$spidergon_router.v:259$4023<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$137<4>./SProuter.\$genblock$spidergon_router.v:225$4006<2>.$genblock$spidergon_router.v:259$4023<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3358<0>.$genblock$spidergon_router.v:259$3361<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3358<0>.$genblock$spidergon_router.v:259$3361<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3358<0>.$genblock$spidergon_router.v:259$3375<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3358<0>.$genblock$spidergon_router.v:259$3375<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3390<1>.$genblock$spidergon_router.v:259$3393<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3390<1>.$genblock$spidergon_router.v:259$3393<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3390<1>.$genblock$spidergon_router.v:259$3407<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3390<1>.$genblock$spidergon_router.v:259$3407<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3422<2>.$genblock$spidergon_router.v:259$3425<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3422<2>.$genblock$spidergon_router.v:259$3425<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3422<2>.$genblock$spidergon_router.v:259$3439<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$171<5>./SProuter.\$genblock$spidergon_router.v:225$3422<2>.$genblock$spidergon_router.v:259$3439<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2774<0>.$genblock$spidergon_router.v:259$2777<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2774<0>.$genblock$spidergon_router.v:259$2777<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2774<0>.$genblock$spidergon_router.v:259$2791<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2774<0>.$genblock$spidergon_router.v:259$2791<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2806<1>.$genblock$spidergon_router.v:259$2809<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2806<1>.$genblock$spidergon_router.v:259$2809<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2806<1>.$genblock$spidergon_router.v:259$2823<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2806<1>.$genblock$spidergon_router.v:259$2823<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2838<2>.$genblock$spidergon_router.v:259$2841<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2838<2>.$genblock$spidergon_router.v:259$2841<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2838<2>.$genblock$spidergon_router.v:259$2855<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$205<6>./SProuter.\$genblock$spidergon_router.v:225$2838<2>.$genblock$spidergon_router.v:259$2855<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2190<0>.$genblock$spidergon_router.v:259$2193<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2190<0>.$genblock$spidergon_router.v:259$2193<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2190<0>.$genblock$spidergon_router.v:259$2207<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2190<0>.$genblock$spidergon_router.v:259$2207<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2222<1>.$genblock$spidergon_router.v:259$2225<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2222<1>.$genblock$spidergon_router.v:259$2225<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2222<1>.$genblock$spidergon_router.v:259$2239<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2222<1>.$genblock$spidergon_router.v:259$2239<1>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2254<2>.$genblock$spidergon_router.v:259$2257<0>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2254<2>.$genblock$spidergon_router.v:259$2257<0>./fifo.data<1>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2254<2>.$genblock$spidergon_router.v:259$2271<1>./fifo.data<0>[9:0] | |
| spidergon_top.\$genblock$spidergon_top.v:103$239<7>./SProuter.\$genblock$spidergon_router.v:225$2254<2>.$genblock$spidergon_router.v:259$2271<1>./fifo.data<1>[9:0] | |
| spidergon_top.adjacent_node_vc_are_full<0>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<1>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<2>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<3>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<4>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<5>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<6>[5:0] | |
| spidergon_top.adjacent_node_vc_are_full<7>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<0>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<1>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<2>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<3>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<4>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<5>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<6>[5:0] | |
| spidergon_top.adjacent_nodes_are_ready<7>[5:0] | |
| @28 | |
| spidergon_top.clk | |
| @22 | |
| spidergon_top.current_node_is_ready<0>[5:0] | |
| spidergon_top.current_node_is_ready<1>[5:0] | |
| spidergon_top.current_node_is_ready<2>[5:0] | |
| spidergon_top.current_node_is_ready<3>[5:0] | |
| spidergon_top.current_node_is_ready<4>[5:0] | |
| spidergon_top.current_node_is_ready<5>[5:0] | |
| spidergon_top.current_node_is_ready<6>[5:0] | |
| spidergon_top.current_node_is_ready<7>[5:0] | |
| spidergon_top.current_node_vc_are_full<0>[5:0] | |
| spidergon_top.current_node_vc_are_full<1>[5:0] | |
| spidergon_top.current_node_vc_are_full<2>[5:0] | |
| spidergon_top.current_node_vc_are_full<3>[5:0] | |
| spidergon_top.current_node_vc_are_full<4>[5:0] | |
| spidergon_top.current_node_vc_are_full<5>[5:0] | |
| spidergon_top.current_node_vc_are_full<6>[5:0] | |
| spidergon_top.current_node_vc_are_full<7>[5:0] | |
| spidergon_top.data_input[79:0] | |
| spidergon_top.data_output[7:0] | |
| spidergon_top.data_packet_contains_header[7:0] | |
| spidergon_top.destination_address_matches[7:0] | |
| @28 | |
| spidergon_top.first_clock_had_passed | |
| @22 | |
| spidergon_top.flit_data_input<0>[9:0] | |
| spidergon_top.flit_data_input<1>[9:0] | |
| spidergon_top.flit_data_input<2>[9:0] | |
| spidergon_top.flit_data_input<3>[9:0] | |
| spidergon_top.flit_data_input<4>[9:0] | |
| spidergon_top.flit_data_input<5>[9:0] | |
| spidergon_top.flit_data_input<6>[9:0] | |
| spidergon_top.flit_data_input<7>[9:0] | |
| spidergon_top.flit_data_input<8>[9:0] | |
| spidergon_top.flit_data_input<9>[9:0] | |
| spidergon_top.flit_data_input<10>[9:0] | |
| spidergon_top.flit_data_input<11>[9:0] | |
| spidergon_top.flit_data_input<12>[9:0] | |
| spidergon_top.flit_data_input<13>[9:0] | |
| spidergon_top.flit_data_input<14>[9:0] | |
| spidergon_top.flit_data_input<15>[9:0] | |
| spidergon_top.flit_data_input<16>[9:0] | |
| spidergon_top.flit_data_input<17>[9:0] | |
| spidergon_top.flit_data_input<18>[9:0] | |
| spidergon_top.flit_data_input<19>[9:0] | |
| spidergon_top.flit_data_input<20>[9:0] | |
| spidergon_top.flit_data_input<21>[9:0] | |
| spidergon_top.flit_data_input<22>[9:0] | |
| spidergon_top.flit_data_input<23>[9:0] | |
| @28 | |
| spidergon_top.flit_data_input_are_valid<0>[2:0] | |
| spidergon_top.flit_data_input_are_valid<1>[2:0] | |
| spidergon_top.flit_data_input_are_valid<2>[2:0] | |
| spidergon_top.flit_data_input_are_valid<3>[2:0] | |
| spidergon_top.flit_data_input_are_valid<4>[2:0] | |
| spidergon_top.flit_data_input_are_valid<5>[2:0] | |
| spidergon_top.flit_data_input_are_valid<6>[2:0] | |
| spidergon_top.flit_data_input_are_valid<7>[2:0] | |
| @22 | |
| spidergon_top.flit_data_output<0>[9:0] | |
| spidergon_top.flit_data_output<1>[9:0] | |
| spidergon_top.flit_data_output<2>[9:0] | |
| spidergon_top.flit_data_output<3>[9:0] | |
| spidergon_top.flit_data_output<4>[9:0] | |
| spidergon_top.flit_data_output<5>[9:0] | |
| spidergon_top.flit_data_output<6>[9:0] | |
| spidergon_top.flit_data_output<7>[9:0] | |
| spidergon_top.flit_data_output<8>[9:0] | |
| spidergon_top.flit_data_output<9>[9:0] | |
| spidergon_top.flit_data_output<10>[9:0] | |
| spidergon_top.flit_data_output<11>[9:0] | |
| spidergon_top.flit_data_output<12>[9:0] | |
| spidergon_top.flit_data_output<13>[9:0] | |
| spidergon_top.flit_data_output<14>[9:0] | |
| spidergon_top.flit_data_output<15>[9:0] | |
| spidergon_top.flit_data_output<16>[9:0] | |
| spidergon_top.flit_data_output<17>[9:0] | |
| spidergon_top.flit_data_output<18>[9:0] | |
| spidergon_top.flit_data_output<19>[9:0] | |
| spidergon_top.flit_data_output<20>[9:0] | |
| spidergon_top.flit_data_output<21>[9:0] | |
| spidergon_top.flit_data_output<22>[9:0] | |
| spidergon_top.flit_data_output<23>[9:0] | |
| @28 | |
| spidergon_top.flit_data_output_are_valid<0>[2:0] | |
| spidergon_top.flit_data_output_are_valid<1>[2:0] | |
| spidergon_top.flit_data_output_are_valid<2>[2:0] | |
| spidergon_top.flit_data_output_are_valid<3>[2:0] | |
| spidergon_top.flit_data_output_are_valid<4>[2:0] | |
| spidergon_top.flit_data_output_are_valid<5>[2:0] | |
| spidergon_top.flit_data_output_are_valid<6>[2:0] | |
| spidergon_top.flit_data_output_are_valid<7>[2:0] | |
| @22 | |
| spidergon_top.input_flit_type<0>[5:0] | |
| spidergon_top.input_flit_type<1>[5:0] | |
| spidergon_top.input_flit_type<2>[5:0] | |
| spidergon_top.input_flit_type<3>[5:0] | |
| spidergon_top.input_flit_type<4>[5:0] | |
| spidergon_top.input_flit_type<5>[5:0] | |
| spidergon_top.input_flit_type<6>[5:0] | |
| spidergon_top.input_flit_type<7>[5:0] | |
| spidergon_top.node_data_from_cpu<0>[9:0] | |
| spidergon_top.node_data_from_cpu<1>[9:0] | |
| spidergon_top.node_data_from_cpu<2>[9:0] | |
| spidergon_top.node_data_from_cpu<3>[9:0] | |
| spidergon_top.node_data_from_cpu<4>[9:0] | |
| spidergon_top.node_data_from_cpu<5>[9:0] | |
| spidergon_top.node_data_from_cpu<6>[9:0] | |
| spidergon_top.node_data_from_cpu<7>[9:0] | |
| spidergon_top.node_data_to_cpu<0>[9:0] | |
| spidergon_top.node_data_to_cpu<1>[9:0] | |
| spidergon_top.node_data_to_cpu<2>[9:0] | |
| spidergon_top.node_data_to_cpu<3>[9:0] | |
| spidergon_top.node_data_to_cpu<4>[9:0] | |
| spidergon_top.node_data_to_cpu<5>[9:0] | |
| spidergon_top.node_data_to_cpu<6>[9:0] | |
| spidergon_top.node_data_to_cpu<7>[9:0] | |
| spidergon_top.out_port_num<0>[5:0] | |
| spidergon_top.out_port_num<1>[5:0] | |
| spidergon_top.out_port_num<2>[5:0] | |
| spidergon_top.out_port_num<3>[5:0] | |
| spidergon_top.out_port_num<4>[5:0] | |
| spidergon_top.out_port_num<5>[5:0] | |
| spidergon_top.out_port_num<6>[5:0] | |
| spidergon_top.out_port_num<7>[5:0] | |
| spidergon_top.packet_arrived_at_dest[7:0] | |
| @28 | |
| spidergon_top.reset | |
| [pattern_trace] 1 | |
| [pattern_trace] 0 |
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| // a single node within the Spidergon | |
| module spidergon_node | |
| #( | |
| `ifdef FORMAL | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=8, | |
| parameter NODE_BUFFER_WIDTH=16, | |
| `else | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=16, | |
| parameter NODE_BUFFER_WIDTH=32, // a single vc buffer can hold 2 flits at one time | |
| `endif | |
| parameter NODE_IDENTIFIER=0, | |
| parameter NUM_OF_VIRTUAL_CHANNELS=2 // 2 vc for each input ports of each node | |
| ) | |
| ( | |
| clk, reset, | |
| `ifdef FORMAL | |
| input_flit_type, | |
| out_port_num, | |
| `endif | |
| flit_data_input_across, flit_data_input_clockwise, flit_data_input_anticlockwise, | |
| flit_data_output_across, flit_data_output_clockwise, flit_data_output_anticlockwise, | |
| node_data_from_cpu, node_data_to_cpu, data_input, | |
| flit_data_input_are_valid, flit_data_output_are_valid, | |
| current_node_is_ready, adjacent_nodes_are_ready, | |
| current_node_vc_are_full, adjacent_node_vc_are_full | |
| ); | |
| parameter DEST_NODE_WIDTH = $clog2(NUM_OF_NODES); | |
| parameter VIRTUAL_CHANNELS_BITWIDTH = $clog2(NUM_OF_VIRTUAL_CHANNELS); | |
| localparam STOP = 3; | |
| localparam ACROSS = 2; | |
| localparam CLOCKWISE = 1; | |
| localparam ANTI_CLOCKWISE = 0; | |
| // the most significant two bits are to indicate head and/or tail flits, | |
| // followed by dest_node and flit_data_payload | |
| // See http://www.lisnoc.org/packets.html | |
| // 01 = head_flit , 10 = data_flit (body_flit), 00 = tail_flit, 11 = flit_without_data_payload | |
| localparam HEAD_FLIT = 'b01; | |
| localparam HEADER = 'b11; // flit_without_data_payload | |
| localparam BODY_FLIT = 'b10; | |
| localparam TAIL_FLIT = 'b00; | |
| localparam HEAD_TAIL = 2; | |
| localparam FLIT_TOTAL_WIDTH = HEAD_TAIL+FLIT_DATA_WIDTH; | |
| localparam NUM_OF_PORTS = 3; // clockwise, anti-clockwise, across | |
| localparam BIDIRECTIONAL_PER_PORT = 2; // two-way data traffic | |
| input clk, reset; | |
| input [FLIT_TOTAL_WIDTH-1:0] data_input; | |
| input [FLIT_TOTAL_WIDTH-1:0] flit_data_input_across; | |
| input [FLIT_TOTAL_WIDTH-1:0] flit_data_input_clockwise; | |
| input [FLIT_TOTAL_WIDTH-1:0] flit_data_input_anticlockwise; | |
| input [FLIT_TOTAL_WIDTH-1:0] node_data_from_cpu; | |
| output reg [FLIT_TOTAL_WIDTH-1:0] node_data_to_cpu; | |
| output [FLIT_TOTAL_WIDTH-1:0] flit_data_output_across; | |
| output [FLIT_TOTAL_WIDTH-1:0] flit_data_output_clockwise; | |
| output [FLIT_TOTAL_WIDTH-1:0] flit_data_output_anticlockwise; | |
| input [NUM_OF_PORTS-1:0] flit_data_input_are_valid; | |
| output [NUM_OF_PORTS-1:0] flit_data_output_are_valid; | |
| // adjacent nodes can accept new head flit to reserve one virtual channel | |
| input [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] adjacent_nodes_are_ready; | |
| // current node can accept new head flit to reserve one virtual channel | |
| output [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] current_node_is_ready; | |
| // to indicate to the node about the virtual channel buffers fill status | |
| input [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] adjacent_node_vc_are_full; | |
| output [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] current_node_vc_are_full; | |
| `ifdef FORMAL | |
| output [NUM_OF_PORTS*HEAD_TAIL-1:0] input_flit_type; | |
| output [NUM_OF_PORTS*DIRECTION_WIDTH-1:0] out_port_num; | |
| `else | |
| wire [NUM_OF_PORTS*HEAD_TAIL-1:0] input_flit_type; | |
| //wire [NUM_OF_PORTS*DIRECTION_WIDTH-1:0] out_port_num; | |
| `endif | |
| wire [NUM_OF_PORTS-1:0] valid_output; | |
| reg [NUM_OF_PORTS-1:0] valid_output_previously; | |
| wire [FLIT_TOTAL_WIDTH-1:0] flit_data_input [NUM_OF_PORTS-1:0]; | |
| reg [FLIT_TOTAL_WIDTH-1:0] flit_data_output [NUM_OF_PORTS-1:0]; | |
| assign flit_data_input[ACROSS] = flit_data_input_across; | |
| assign flit_data_input[CLOCKWISE] = flit_data_input_clockwise; | |
| assign flit_data_input[ANTI_CLOCKWISE] = flit_data_input_anticlockwise; | |
| assign flit_data_output_across = flit_data_output[ACROSS]; | |
| assign flit_data_output_clockwise = flit_data_output[CLOCKWISE]; | |
| assign flit_data_output_anticlockwise = flit_data_output[ANTI_CLOCKWISE]; | |
| // these virtual channel buffers are at input port side | |
| wire [FLIT_TOTAL_WIDTH-1:0] data_output_from_vc [NUM_OF_PORTS-1:0][NUM_OF_VIRTUAL_CHANNELS-1:0]; | |
| wire [FLIT_TOTAL_WIDTH-1:0] data_input_to_vc [NUM_OF_PORTS-1:0][NUM_OF_VIRTUAL_CHANNELS-1:0]; | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] vc_is_available [NUM_OF_PORTS-1:0]; // vc is not BUSY | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] vc_buffer_is_empty [NUM_OF_PORTS-1:0]; // no flits inside vc | |
| // requests for the input data (from one of the 3 input ports) | |
| // to be routed to destination node (via one of the 3 output ports) | |
| // this 'req' is not a one-hot vector: reg [vc_num] req [out_port]; | |
| // multiple input data streams from different virtual channels could compete for the same output port | |
| reg [NUM_OF_VIRTUAL_CHANNELS-1:0] req [NUM_OF_PORTS-1:0]; | |
| reg [NUM_OF_VIRTUAL_CHANNELS-1:0] req_previous [NUM_OF_PORTS-1:0]; | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] vc_is_to_be_allocated [NUM_OF_PORTS-1:0]; | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] vc_is_to_be_deallocated [NUM_OF_PORTS-1:0]; | |
| localparam DIRECTION_WIDTH = 2; | |
| wire [DIRECTION_WIDTH-1:0] direction [NUM_OF_PORTS-1:0]; // stop, clockwise, anti-clockwise, across | |
| wire [DEST_NODE_WIDTH-1:0] dest_node [NUM_OF_PORTS-1:0]; | |
| localparam NON_EXISTENCE_VC_NUM = {(NUM_OF_VIRTUAL_CHANNELS+1){1'b1}}; | |
| wire [NUM_OF_PORTS-1:0] req_port; | |
| // note that 'grant' is one-hot vector, | |
| // when asserted, it means the corresponding 'req' is approved/granted | |
| // and only a single priority line is serviced (granted) at any given clock cycle | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] granted_vc; | |
| wire [NUM_OF_PORTS-1:0] granted_port; | |
| // binary encoding of 'granted_vc' and 'granted_port'. Refer to module 'oh_to_idx' | |
| wire [$clog2(NUM_OF_VIRTUAL_CHANNELS)-1:0] granted_vc_index; | |
| wire [$clog2(NUM_OF_PORTS)-1:0] granted_port_index; | |
| // for detecting if all outstanding requests are already served | |
| wire [NUM_OF_PORTS-1:0] requests_in_ports_have_been_served = req_port & granted_port; | |
| //wire [NUM_OF_PORTS-1:0] outstanding_requests_in_multiple_ports = req_port - granted_port; | |
| // https://graphics.stanford.edu/~seander/bithacks.html#DetermineIfPowerOf2 | |
| wire requests_from_multiple_ports = (req_port != 0) && !((req_port & (req_port - 1)) == 0); | |
| // Ports round-robin arbitration (maps port to cpu) | |
| arbiter #(NUM_OF_PORTS) rr_arb_port_to_cpu | |
| (.clk(clk), .reset(reset), .req(req_port), .grant(granted_port)); | |
| // remember that each ports have multiple vc | |
| // virtual channel (VC) outgoing buffers round-robin arbitration (maps vc in port to cpu) | |
| arbiter #(NUM_OF_VIRTUAL_CHANNELS) rr_arb_vc_to_cpu | |
| (.clk(clk), .reset(reset), .req(req[granted_port_index]), .grant(granted_vc)); | |
| // for one-hot encoding to binary encoding conversion | |
| oh_to_idx #(NUM_OF_PORTS) port_index (.one_hot(granted_port), .index(granted_port_index)); | |
| oh_to_idx #(NUM_OF_VIRTUAL_CHANNELS) vc_index (.one_hot(granted_vc), .index(granted_vc_index)); | |
| //reg [NUM_OF_PORTS-1:0] past_req_port; | |
| //always @(posedge clk) past_req_port <= req_port; | |
| always @(*) | |
| begin | |
| if(reset & reset_previously) | |
| node_data_to_cpu = data_input; | |
| //else if(past_req_port == 0) node_data_to_cpu = 0; | |
| else node_data_to_cpu = data_output_from_vc[granted_port_index][granted_vc_index]; | |
| end | |
| wire [$clog2(NUM_OF_NODES)-1:0] current_node = NODE_IDENTIFIER; | |
| // 'reset' signal spans across 2 clock cycles for correct fifo reset operation before inserting item into fifo | |
| // 'reset_previously' is used together with 'reset' to identify falling edge of 'reset' | |
| reg reset_previously; | |
| always @(posedge clk) reset_previously <= reset; | |
| // note that flits from the same data packet cannot be interleaved | |
| // among different virtual channels | |
| // Why ? Because of head flit and tail flit indication | |
| // let FLIT_DATA_WIDTH = 16 in the discussion below: | |
| // let HEAD_TAIL = 2 to indicate flit type | |
| // let FLIT_TOTAL_WIDTH = HEAD_TAIL + FLIT_DATA_WIDTH | |
| // 18-bit head flit format as follows: {01, prev_vc, destination_node, 12 bits of data_payload} | |
| // prev_vc consumes 1 bit, destination_node consumes 3 bits (8 nodes in total), | |
| // so we are left with 12 bits in the head flit | |
| // these 12 bits could be data payload as well | |
| // 18-bit body flit format as follows: {10, prev_vc, 15 bits of data_payload} | |
| // 18-bit tail flit format as follows: {00, prev_vc, 15 bits of data_payload} | |
| // So, a single body_flit or tail_flit could carry 15 bits of data payload | |
| // tail flit will deallocate all the virtual channels along the path to the destination nodes | |
| // for wormhole switching flow control purpose | |
| // basically each node itself need to remember(store) exactly which header | |
| // allocates which virtual channel, and this storing has to be coherent for | |
| // previous and current nodes due to wormhole switching requirement | |
| /* | |
| A vc allocation table for current node (imagine the use of linked-list data structure) | |
| Current_Port Current_VC Prev_VC BUSY FULL | |
| ACROSS 0 X X X | |
| ACROSS 1 X X X | |
| CLOCKWISE 0 X X X | |
| CLOCKWISE 1 X X X | |
| ANTI_CLOCKWISE 0 X X X | |
| ANTI_CLOCKWISE 1 X X X | |
| Note: | |
| 1. The head flit contains Prev_VC (no need for Prev_Port since we can deduce from Current_Port) | |
| 2. Once a Current_VC is reserved by head flit, the corresponding table entry is filled | |
| 3. Once a Current_VC is de-reserved by tail flit, the corresponding table entry is updated | |
| 4. BUSY and FULL signals are for Current_VC, not for Prev_VC | |
| 5. A table costs 36 bits (NUM_OF_ROWS*(2+1+1+1+1)) | |
| */ | |
| genvar port_num; | |
| genvar vc_num; | |
| generate | |
| for(port_num=0; port_num<NUM_OF_PORTS; port_num=port_num+1) | |
| begin : PORTS | |
| `ifdef FORMAL | |
| assign out_port_num[port_num*DIRECTION_WIDTH +: DIRECTION_WIDTH] = direction[port_num]; | |
| `endif | |
| // asserted whenever one of the virtual channels in each port is reserved | |
| assign req_port[port_num] = |req[port_num]; | |
| assign input_flit_type[port_num*HEAD_TAIL +: HEAD_TAIL] = | |
| flit_data_input[port_num][(FLIT_TOTAL_WIDTH-1) -: HEAD_TAIL] ; | |
| // virtual channel index at previous node | |
| wire prev_vc = | |
| flit_data_input[port_num][(FLIT_DATA_WIDTH-1) -: VIRTUAL_CHANNELS_BITWIDTH] ; | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] adjacent_nodes_vc_are_reserved_and_not_full; | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] granted_vc_enqueue; // to indicate which vc to reserve | |
| // remember that each ports have multiple vc | |
| // virtual channel (VC) incoming buffers round-robin arbitration (maps incoming data to vc) | |
| arbiter #(NUM_OF_VIRTUAL_CHANNELS) rr_arb_data_to_vc | |
| ( | |
| .clk(clk), | |
| .reset(reset), | |
| .req(current_node_is_ready[port_num*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]), | |
| .grant(granted_vc_enqueue) | |
| ); | |
| wire [NUM_OF_VIRTUAL_CHANNELS-1:0] previous_vc; | |
| for(vc_num=0; vc_num<NUM_OF_VIRTUAL_CHANNELS; vc_num=vc_num+1) | |
| begin : VIRTUAL_CHANNELS | |
| // ON/OFF flow control | |
| // to indicate whether flit data could come into the node | |
| // (vc buffer is not reserved) | |
| assign current_node_is_ready[port_num*NUM_OF_VIRTUAL_CHANNELS + vc_num] = | |
| vc_is_available[port_num][vc_num]; | |
| // (the next node has at least one available, non-reserved vc) OR | |
| // (any of the reserved vc (at next node) has sufficient buffer space) | |
| // AND (to prevent competition of virtual channels for CPU) | |
| wire dequeue_en = (((|adjacent_nodes_are_ready[dest_node[port_num]*NUM_OF_VIRTUAL_CHANNELS +: | |
| NUM_OF_VIRTUAL_CHANNELS]) || (|adjacent_nodes_vc_are_reserved_and_not_full)) | |
| && (!requests_from_multiple_ports || | |
| requests_from_multiple_ports && requests_in_ports_have_been_served[port_num])); | |
| assign adjacent_nodes_vc_are_reserved_and_not_full[vc_num] = | |
| ((!adjacent_nodes_are_ready[dest_node[port_num]*NUM_OF_VIRTUAL_CHANNELS + vc_num]) | |
| & (!adjacent_node_vc_are_full[dest_node[port_num]*NUM_OF_VIRTUAL_CHANNELS + vc_num])); | |
| assign previous_vc[vc_num] = (reset || vc_is_available[port_num][vc_num]) ? | |
| 1'b0 : prev_vc; | |
| // enqueues when 'data is valid' && ((available vc is granted permission) || | |
| // ('vc is reserved' by the same 'head flit')) && '!current vc is full' | |
| wire enqueue_en = (!reset & reset_previously) ? flit_data_input_are_valid[port_num] && (vc_num == 0) : | |
| flit_data_input_are_valid[port_num] && | |
| ((vc_is_available[port_num][vc_num] && granted_vc_enqueue[vc_num]) || | |
| (!vc_is_available[port_num][vc_num] && (prev_vc == previous_vc[vc_num]))) && | |
| (!current_node_vc_are_full[port_num*NUM_OF_VIRTUAL_CHANNELS + vc_num]); | |
| // virtual channel buffer in the form of strict FIFO ordering | |
| sync_fifo | |
| #( | |
| .WIDTH(FLIT_TOTAL_WIDTH), | |
| .SIZE(NODE_BUFFER_WIDTH/FLIT_DATA_WIDTH) | |
| ) | |
| fifo | |
| ( | |
| .clk(clk), .reset(reset), | |
| .full(current_node_vc_are_full[port_num*NUM_OF_VIRTUAL_CHANNELS + vc_num]), | |
| .enqueue_en(enqueue_en), | |
| .enqueue_value(data_input_to_vc[port_num][vc_num]), | |
| // buffer could be empty even it is reserved, due to flits not arriving yet | |
| .empty(vc_buffer_is_empty[port_num][vc_num]), | |
| .dequeue_en(dequeue_en), // enabled when the buffers at next node can take in flits | |
| .dequeue_value(data_output_from_vc[port_num][vc_num]) | |
| ); | |
| assign data_input_to_vc[port_num][vc_num] = flit_data_input[port_num]; | |
| assign vc_is_available[port_num][vc_num] = !req[port_num][vc_num]; | |
| always @(posedge clk) | |
| begin | |
| if(reset) req_previous[port_num][vc_num] <= 0; | |
| else req_previous[port_num][vc_num] <= req[port_num][vc_num]; | |
| end | |
| // NOT reserved yet for usage by other flit | |
| // remember that each header or head flit could only reserve ONE vc in each port | |
| assign vc_is_to_be_allocated[port_num][vc_num] = (!reset & reset_previously) ? | |
| ((flit_data_input_are_valid[port_num]) && (vc_num == 0)) : | |
| (granted_vc_enqueue[vc_num] && (vc_is_available[port_num][vc_num]) && | |
| ((input_flit_type[port_num*HEAD_TAIL +: HEAD_TAIL] == HEADER) || | |
| (input_flit_type[port_num*HEAD_TAIL +: HEAD_TAIL] == HEAD_FLIT))); | |
| // vc is already reserved, waiting to be released by tail_flit | |
| assign vc_is_to_be_deallocated[port_num][vc_num] = | |
| (req_previous[port_num][vc_num] && | |
| (input_flit_type[port_num*HEAD_TAIL +: HEAD_TAIL] == TAIL_FLIT) && | |
| (prev_vc == vc_num)) && (requests_in_ports_have_been_served[port_num]); | |
| // virtual channel reservation logic block | |
| always @(posedge clk) | |
| begin | |
| if(reset & reset_previously) req[port_num][vc_num] <= vc_is_to_be_allocated[port_num][vc_num]; | |
| else if ((vc_is_to_be_allocated[port_num][vc_num] && !vc_is_to_be_deallocated[port_num][vc_num]) | |
| || (!vc_is_to_be_allocated[port_num][vc_num] && vc_is_to_be_deallocated[port_num][vc_num])) | |
| begin | |
| // HEAD_FLIT or HEADER will reserve the virtual channel | |
| // BODY_FLIT will not affect the channel reservation status | |
| // TAIL_FLIT will de-reserve the virtual channel reserved by HEAD_FLIT | |
| // HEADER will only reserves its virtual channel for single clock cycle | |
| // check the flit header to determine the flit nature | |
| case(input_flit_type[port_num*HEAD_TAIL +: HEAD_TAIL]) | |
| // body_flit | |
| // to keep 'req' asserted before the arrival of tail_flit | |
| BODY_FLIT : req[port_num][vc_num] <= 1; | |
| // tail_flit | |
| TAIL_FLIT : req[port_num][vc_num] <= 0; | |
| // head_flit | |
| HEAD_FLIT : req[port_num][vc_num] <= 1; | |
| // header flit_without_data_payload | |
| HEADER : req[port_num][vc_num] <= 1; | |
| default : req[port_num][vc_num] <= 0; | |
| endcase | |
| end | |
| //else req[port_num][vc_num] <= 0; | |
| end | |
| `ifdef FORMAL | |
| //always @(posedge clk) cover((vc_num == vc_new) || (vc_num == vc_old)); | |
| `endif | |
| end | |
| wire [(HEAD_TAIL-1) : 0] output_flit_type = | |
| node_data_from_cpu[(FLIT_TOTAL_WIDTH-1) -: HEAD_TAIL]; | |
| // for the purpose of stopping transaction flow when tail_flit is received | |
| wire stop_flow = (reset) ? | |
| (data_input[FLIT_DATA_WIDTH +: HEAD_TAIL] == TAIL_FLIT) : | |
| (output_flit_type == TAIL_FLIT); | |
| assign dest_node[port_num] = (reset) ? | |
| data_input[(FLIT_DATA_WIDTH-$clog2(NUM_OF_VIRTUAL_CHANNELS)-1) -: DEST_NODE_WIDTH] : | |
| flit_data_output[port_num][(FLIT_DATA_WIDTH-$clog2(NUM_OF_VIRTUAL_CHANNELS)-1) -: DEST_NODE_WIDTH]; | |
| // path routing computation block for each input ports | |
| router #(NUM_OF_NODES) rt | |
| ( | |
| //.clk(clk), | |
| // see the math logic in router.v on why we set it to 'current_node' for tail_flit | |
| .dest_node((stop_flow) ? current_node : dest_node[port_num]), | |
| .current_node(current_node), | |
| .direction(direction[port_num]) | |
| ); | |
| always @(posedge clk) valid_output_previously[port_num] <= valid_output[port_num]; | |
| // for aligning correctly with 'flit_data_output' in the same clock cycle | |
| assign flit_data_output_are_valid[port_num] = valid_output[port_num]; | |
| // needs some backpressure logic here | |
| assign valid_output[port_num] = (reset) ? | |
| (direction[port_num] == port_num) && | |
| ((output_flit_type == HEAD_FLIT) || (output_flit_type == HEADER)) : | |
| (direction[port_num] == port_num) && | |
| (((output_flit_type == HEAD_FLIT) || (output_flit_type == HEADER)) || | |
| (valid_output_previously[port_num] && | |
| (output_flit_type == BODY_FLIT))); | |
| always @(*) | |
| begin | |
| //flit_data_output[port_num] <= 0; // clears data in all channels first | |
| if(reset) | |
| begin | |
| if(valid_output[port_num]) | |
| flit_data_output[port_num] = data_input; // initial data input for NoC | |
| else flit_data_output[port_num] = 0; // clears data in all channels | |
| end | |
| else if(valid_output[port_num]) begin | |
| // needs some backpressure logic here | |
| // sends out data from cpu to physical channel | |
| flit_data_output[port_num] = node_data_from_cpu; | |
| end | |
| end | |
| end | |
| endgenerate | |
| endmodule |
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| // https://www.reddit.com/r/algorithms/comments/au94ak/spidergon_networksonchips/ | |
| module spidergon_top | |
| #( | |
| `ifdef FORMAL | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=8, | |
| parameter NODE_BUFFER_WIDTH=16, | |
| `else | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=16, | |
| parameter NODE_BUFFER_WIDTH=32, // a single vc buffer can hold 2 flits at one time | |
| `endif | |
| parameter NUM_OF_VIRTUAL_CHANNELS=2 // 2 vc for each input ports of each node | |
| ) | |
| (clk, reset, data_input, data_output); | |
| // the most significant two bits are to indicate head and/or tail flits, | |
| // followed by dest_node and flit_data_payload | |
| // See http://www.lisnoc.org/packets.html | |
| // 01 = head_flit , 10 = data_flit (body_flit), 00 = tail_flit, 11 = flit_without_data_payload | |
| localparam HEAD_FLIT = 'b01; | |
| localparam HEADER = 'b11; // flit_without_data_payload | |
| localparam BODY_FLIT = 'b10; | |
| localparam TAIL_FLIT = 'b00; | |
| localparam HEAD_TAIL = 2; | |
| parameter DEST_NODE_WIDTH = $clog2(NUM_OF_NODES); | |
| localparam FLIT_TOTAL_WIDTH = HEAD_TAIL+FLIT_DATA_WIDTH; | |
| localparam DIRECTION_WIDTH = 2; // $clog2(NUM_OF_PORTS) | |
| localparam NUM_OF_PORTS = 3; // clockwise, anti-clockwise, across | |
| localparam STOP = 3; | |
| localparam ACROSS = 2; | |
| localparam CLOCKWISE = 1; | |
| localparam ANTI_CLOCKWISE = 0; | |
| // for user application mapping, this value must be smaller than NUM_OF_NODES | |
| localparam NUM_OF_INPUTS = 16; | |
| input clk, reset; | |
| input [NUM_OF_NODES*FLIT_TOTAL_WIDTH-1:0] data_input; // for initial input data of each nodes | |
| output signed [FLIT_DATA_WIDTH-1:0] data_output; | |
| reg [FLIT_TOTAL_WIDTH-1:0] node_data_from_cpu [NUM_OF_NODES-1:0]; | |
| wire [FLIT_TOTAL_WIDTH-1:0] node_data_to_cpu [NUM_OF_NODES-1:0]; | |
| wire [FLIT_TOTAL_WIDTH-1:0] flit_data_input [NUM_OF_NODES-1:0][NUM_OF_PORTS-1:0]; | |
| wire [FLIT_TOTAL_WIDTH-1:0] flit_data_output [NUM_OF_NODES-1:0][NUM_OF_PORTS-1:0]; | |
| wire [NUM_OF_PORTS-1:0] flit_data_input_are_valid [NUM_OF_NODES-1:0]; | |
| wire [NUM_OF_PORTS-1:0] flit_data_output_are_valid [NUM_OF_NODES-1:0]; | |
| // is the node ready to accept new head flit | |
| wire [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] current_node_is_ready [NUM_OF_NODES-1:0]; | |
| wire [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] adjacent_nodes_are_ready [NUM_OF_NODES-1:0]; | |
| // to control the flow, acts as traffic light for the data flits | |
| wire [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] current_node_vc_are_full[NUM_OF_NODES-1:0]; | |
| wire [NUM_OF_PORTS*NUM_OF_VIRTUAL_CHANNELS-1:0] adjacent_node_vc_are_full[NUM_OF_NODES-1:0]; | |
| // Final result output from user application mapping | |
| assign data_output = flit_data_output[NUM_OF_NODES-1][NUM_OF_PORTS-1][FLIT_DATA_WIDTH-1:0]; | |
| `ifdef FORMAL | |
| initial assume(reset); | |
| reg first_clock_had_passed; | |
| initial first_clock_had_passed = 0; | |
| always @(posedge clk) first_clock_had_passed <= 1; | |
| wire [NUM_OF_NODES-1:0] packet_arrived_at_dest; | |
| reg [NUM_OF_NODES-1:0] data_packet_contains_header; | |
| reg [NUM_OF_NODES-1:0] destination_address_matches; | |
| initial data_packet_contains_header = 0; | |
| initial destination_address_matches = 0; | |
| wire [NUM_OF_PORTS*HEAD_TAIL-1:0] input_flit_type [NUM_OF_NODES-1:0]; | |
| wire [NUM_OF_PORTS*DIRECTION_WIDTH-1:0] out_port_num [NUM_OF_NODES-1:0]; | |
| `endif | |
| generate | |
| // generates all the nodes of spidergon as well as the connecting edges between nodes | |
| genvar node_num; | |
| for(node_num = 0; node_num < NUM_OF_NODES; node_num = node_num + 1) | |
| begin : NODES | |
| if(node_num == 0) | |
| begin | |
| assign flit_data_input[node_num][ANTI_CLOCKWISE] = flit_data_output[NUM_OF_NODES-1][CLOCKWISE]; | |
| assign flit_data_input_are_valid[node_num][ANTI_CLOCKWISE] = | |
| flit_data_output_are_valid[NUM_OF_NODES-1][CLOCKWISE]; | |
| assign adjacent_node_vc_are_full[node_num][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[NUM_OF_NODES-1][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[NUM_OF_NODES-1][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| else begin | |
| assign flit_data_input[node_num][ANTI_CLOCKWISE] = flit_data_output[node_num-1][CLOCKWISE]; | |
| assign flit_data_input_are_valid[node_num][ANTI_CLOCKWISE] = | |
| flit_data_output_are_valid[node_num-1][CLOCKWISE]; | |
| assign adjacent_node_vc_are_full[node_num][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[node_num-1][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[node_num-1][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| if(node_num == (NUM_OF_NODES-1)) | |
| begin | |
| assign flit_data_input[node_num][CLOCKWISE] = flit_data_output[0][ANTI_CLOCKWISE]; | |
| assign flit_data_input_are_valid[node_num][CLOCKWISE] = | |
| flit_data_output_are_valid[0][ANTI_CLOCKWISE]; | |
| assign adjacent_node_vc_are_full[node_num][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[0][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[0][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| else begin | |
| assign flit_data_input[node_num][CLOCKWISE] = flit_data_output[node_num+1][ANTI_CLOCKWISE]; | |
| assign flit_data_input_are_valid[node_num][CLOCKWISE] = | |
| flit_data_output_are_valid[node_num+1][ANTI_CLOCKWISE]; | |
| assign adjacent_node_vc_are_full[node_num][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[node_num+1][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[node_num+1][ANTI_CLOCKWISE*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| if(node_num >= (NUM_OF_NODES>>1)) | |
| begin | |
| assign flit_data_input[node_num][ACROSS] = flit_data_output[node_num-(NUM_OF_NODES>>1)][ACROSS]; | |
| assign flit_data_input_are_valid[node_num][ACROSS] = | |
| flit_data_output_are_valid[node_num-(NUM_OF_NODES>>1)][ACROSS]; | |
| assign adjacent_node_vc_are_full[node_num][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[node_num-(NUM_OF_NODES>>1)][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[node_num-(NUM_OF_NODES>>1)][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| else begin | |
| assign flit_data_input[node_num][ACROSS] = flit_data_output[node_num+(NUM_OF_NODES>>1)][ACROSS]; | |
| assign flit_data_input_are_valid[node_num][ACROSS] = | |
| flit_data_output_are_valid[node_num+(NUM_OF_NODES>>1)][ACROSS]; | |
| assign adjacent_node_vc_are_full[node_num][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_vc_are_full[node_num+(NUM_OF_NODES>>1)][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| assign adjacent_nodes_are_ready[node_num][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS] = | |
| current_node_is_ready[node_num+(NUM_OF_NODES>>1)][ACROSS*NUM_OF_VIRTUAL_CHANNELS +: NUM_OF_VIRTUAL_CHANNELS]; | |
| end | |
| spidergon_node | |
| #( | |
| .NUM_OF_NODES(NUM_OF_NODES), | |
| .FLIT_DATA_WIDTH(FLIT_DATA_WIDTH), | |
| .NODE_BUFFER_WIDTH(NODE_BUFFER_WIDTH), | |
| .NODE_IDENTIFIER(node_num), | |
| .NUM_OF_VIRTUAL_CHANNELS(NUM_OF_VIRTUAL_CHANNELS) | |
| ) | |
| SPnode | |
| ( | |
| .clk(clk), .reset(reset), | |
| `ifdef FORMAL | |
| .input_flit_type(input_flit_type[node_num]), | |
| .out_port_num(out_port_num[node_num]), | |
| `endif | |
| .flit_data_input_across(flit_data_input[node_num][ACROSS]), | |
| .flit_data_input_clockwise(flit_data_input[node_num][CLOCKWISE]), | |
| .flit_data_input_anticlockwise(flit_data_input[node_num][ANTI_CLOCKWISE]), | |
| .flit_data_input_are_valid(flit_data_input_are_valid[node_num]), | |
| .flit_data_output_across(flit_data_output[node_num][ACROSS]), | |
| .flit_data_output_clockwise(flit_data_output[node_num][CLOCKWISE]), | |
| .flit_data_output_anticlockwise(flit_data_output[node_num][ANTI_CLOCKWISE]), | |
| .node_data_from_cpu(node_data_from_cpu[node_num]), | |
| .node_data_to_cpu(node_data_to_cpu[node_num]), | |
| .data_input(data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH]), | |
| // http://www.lisnoc.org/flowcontrol.html ON/OFF flow control | |
| // sender node asserts 'valid' signal when it has data to send to its neighbouring node | |
| // receipient node asserts 'ready' signal when it has available buffer space | |
| // 'ready' output signals | |
| .current_node_is_ready(current_node_is_ready[node_num]), | |
| // 'valid' output signals | |
| .flit_data_output_are_valid(flit_data_output_are_valid[node_num]), | |
| // 'ready' input signals from next immediate nodes in transit along the transmission path | |
| .adjacent_nodes_are_ready(adjacent_nodes_are_ready[node_num]), | |
| // backpressure signals | |
| .current_node_vc_are_full(current_node_vc_are_full[node_num]), // output | |
| .adjacent_node_vc_are_full(adjacent_node_vc_are_full[node_num]) // input | |
| ); | |
| // What about packet-retransmission due to data CRC integrity error ? | |
| // will implement this later because the consequences of such a rare failure | |
| // are not high enough to justify effort to mitigate it now | |
| // See the overall spidergon hardware architecture at https://i.imgur.com/6d9E1JT.png | |
| // for Spidergon NoC functional verification and testing only, | |
| // use user-defined module below otherwise | |
| always @(posedge clk) | |
| node_data_from_cpu[node_num] <= node_data_to_cpu[node_num]; | |
| // user-defined module (arithmetic operations) within each Spidergon node | |
| /*spidergon_node_cpu SP_cpu()*/ | |
| `ifdef FORMAL | |
| initial assume(data_input[((node_num+1)*FLIT_TOTAL_WIDTH-1) -: HEAD_TAIL] == HEADER); | |
| // multi-hop verification for deadlock check | |
| integer dest_ports, source_node_num; | |
| always @(posedge clk) | |
| begin | |
| if(reset) data_packet_contains_header[node_num] <= 0; | |
| else begin | |
| for(dest_ports = 0; dest_ports < NUM_OF_PORTS; dest_ports = dest_ports + 1) | |
| begin | |
| if((input_flit_type[node_num][dest_ports*HEAD_TAIL +: HEAD_TAIL] == HEAD_FLIT) || | |
| (input_flit_type[node_num][dest_ports*HEAD_TAIL +: HEAD_TAIL] == HEADER)) | |
| data_packet_contains_header[node_num] <= 1; | |
| end | |
| end | |
| end | |
| always @(posedge clk) | |
| begin | |
| if(reset) destination_address_matches[node_num] <= 0; | |
| else begin | |
| for(source_node_num = 1; source_node_num<=NUM_OF_NODES; | |
| source_node_num = source_node_num + 1) | |
| begin | |
| if(node_num == | |
| data_input[(source_node_num*FLIT_TOTAL_WIDTH-HEAD_TAIL-$clog2(NUM_OF_VIRTUAL_CHANNELS)-1) -: DEST_NODE_WIDTH]) | |
| destination_address_matches[node_num] <= 1; | |
| end | |
| end | |
| end | |
| assign packet_arrived_at_dest[node_num] = (first_clock_had_passed && | |
| (data_packet_contains_header[node_num]) && (destination_address_matches[node_num])); | |
| integer port_num; | |
| always @(posedge clk) | |
| begin | |
| if(first_clock_had_passed && $past(reset)) | |
| begin | |
| for(port_num=0; port_num<NUM_OF_PORTS; port_num=port_num+1) | |
| begin | |
| if(port_num == out_port_num[node_num][port_num*DIRECTION_WIDTH +: DIRECTION_WIDTH]) | |
| assert(flit_data_output[node_num][port_num] == node_data_from_cpu[node_num]); | |
| else assert(flit_data_output[node_num][port_num] == 0); | |
| end | |
| end | |
| else if(packet_arrived_at_dest[node_num]) begin // reaching destination node | |
| // use 'b1xx since a node can receive packets from | |
| // all three incoming ports in the same clock cyle | |
| case (flit_data_input_are_valid[node_num]) | |
| 'bxx1 : assert(flit_data_input[node_num][ACROSS] == | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH]); | |
| 'bx1x : assert(flit_data_input[node_num][CLOCKWISE] == | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH]); | |
| 'b1xx : assert(flit_data_input[node_num][ANTI_CLOCKWISE] == | |
| data_input[node_num*FLIT_TOTAL_WIDTH +: FLIT_TOTAL_WIDTH]); | |
| //default : assert(1);// don't care when it is 'b000 since no data is received yet | |
| endcase | |
| end | |
| // verify the correctness of single-hop routing between two neighbour nodes | |
| else begin | |
| //assert(); | |
| end | |
| end | |
| // single data packet traversing the NoC and reached its destination successfully | |
| always @(posedge clk) cover(packet_arrived_at_dest[node_num]); | |
| always @(posedge clk) cover(data_packet_contains_header[node_num]); | |
| //always @(posedge clk) cover(destination_address_matches[node_num]); | |
| `endif | |
| end | |
| endgenerate | |
| `ifdef FORMAL | |
| // multiple data packets traversing the NoC and reached their destination successfully | |
| always @(posedge clk) cover(&packet_arrived_at_dest); | |
| `endif | |
| endmodule |
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| [tasks] | |
| proof | |
| cover | |
| [options] | |
| proof: mode prove | |
| proof: depth 10 | |
| cover: mode cover | |
| cover: depth 20 | |
| cover: append 3 | |
| [engines] | |
| smtbmc yices | |
| # smtbmc boolector | |
| # abc pdr | |
| # aiger avy | |
| # aiger suprove | |
| [script] | |
| read_verilog -formal -sv sync_fifo.v | |
| prep -top sync_fifo | |
| [files] | |
| sync_fifo.v |
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| // Credit : https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/sync_fifo.sv | |
| // | |
| // Copyright 2011-2015 Jeff Bush | |
| // | |
| // Licensed under the Apache License, Version 2.0 (the "License"); | |
| // you may not use this file except in compliance with the License. | |
| // You may obtain a copy of the License at | |
| // | |
| // http://www.apache.org/licenses/LICENSE-2.0 | |
| // | |
| // Unless required by applicable law or agreed to in writing, software | |
| // distributed under the License is distributed on an "AS IS" BASIS, | |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |
| // See the License for the specific language governing permissions and | |
| // limitations under the License. | |
| // | |
| // | |
| // First-in, first-out queue, with synchronous read/write | |
| // - SIZE must be a power of two and greater than or equal to 4. | |
| // - almost_full asserts when there are ALMOST_FULL_THRESHOLD or more entries | |
| // queued. | |
| // - almost_empty asserts when there are ALMOST_EMPTY_THRESHOLD or fewer | |
| // entries queued. | |
| // - almost_full is still asserted when full is asserted, as is almost_empty | |
| // when empty is asserted. | |
| // - flush takes precedence over enqueue/dequeue if it is asserted | |
| // simultaneously. It is synchronous, unlike reset. | |
| // - It is not legal to assert enqueue when the FIFO is full or dequeue when it | |
| // is empty (The former is true even if there is a dequeue and enqueue in the | |
| // same cycle, which wouldn't change the count). Doing this will trigger an | |
| // error in the simulator and have incorrect behavior in synthesis. | |
| // - dequeue_value will contain the next value to be dequeued even if dequeue_en is | |
| // not asserted. | |
| // | |
| module sync_fifo | |
| #(parameter WIDTH = 4, | |
| parameter SIZE = 8 | |
| //parameter ALMOST_FULL_THRESHOLD = SIZE, | |
| //parameter ALMOST_EMPTY_THRESHOLD = 1 | |
| ) | |
| (input clk, | |
| input reset, | |
| output full, | |
| //output reg almost_full, | |
| input enqueue_en, | |
| input [WIDTH - 1:0] enqueue_value, | |
| output empty, | |
| //output reg almost_empty, | |
| input dequeue_en, | |
| output [WIDTH - 1:0] dequeue_value); | |
| parameter ADDR_WIDTH = $clog2(SIZE); | |
| // read and write pointers need one extra MSB bit to differentiate between empty and full | |
| // you can confirm this using count = wr_addr - rd_addr; | |
| reg[ADDR_WIDTH:0] rd_addr; | |
| reg[ADDR_WIDTH:0] wr_addr; | |
| reg[WIDTH - 1:0] data[SIZE - 1:0]; | |
| `ifdef FORMAL | |
| initial rd_addr = 0; | |
| initial wr_addr = 0; | |
| `endif | |
| wire[ADDR_WIDTH:0] count = wr_addr - rd_addr; | |
| //assign almost_full = count >= (ADDR_WIDTH + 1)'(ALMOST_FULL_THRESHOLD); | |
| //assign almost_empty = count <= (ADDR_WIDTH + 1)'(ALMOST_EMPTY_THRESHOLD); | |
| assign full = (count == SIZE[ADDR_WIDTH:0]); | |
| assign empty = count == 0; | |
| assign dequeue_value = data[rd_addr[ADDR_WIDTH-1:0]]; // passed verilator width warning | |
| integer index; | |
| always @(posedge clk) | |
| begin | |
| if (reset) | |
| begin | |
| rd_addr <= 0; | |
| wr_addr <= 0; | |
| for(index=0; index<SIZE; index=index+1) | |
| data[index] <= 0; | |
| end | |
| else begin | |
| // https://twitter.com/zipcpu/status/1143134086950789120 | |
| // if enqueue_en and dequeue_en and full at the same time, nothing is added, one item is removed, | |
| // but count is not modified. Same for empty. | |
| // https://zipcpu.com/blog/2017/07/29/fifo.html | |
| // https://zipcpu.com/tutorial/lsn-10-fifo.pdf | |
| case( {(dequeue_en && !empty), (enqueue_en && !full) }) | |
| 'b00 : begin | |
| wr_addr <= wr_addr; | |
| rd_addr <= rd_addr; | |
| end | |
| 'b01 : begin | |
| wr_addr <= wr_addr + 1; | |
| data[wr_addr[ADDR_WIDTH-1:0]] <= enqueue_value; // passed verilator width warning | |
| rd_addr <= rd_addr; | |
| end | |
| 'b10 : begin | |
| wr_addr <= wr_addr; | |
| rd_addr <= rd_addr + 1; | |
| end | |
| 'b11 : begin | |
| wr_addr <= wr_addr + 1; | |
| data[wr_addr[ADDR_WIDTH-1:0]] <= enqueue_value; // passed verilator width warning | |
| rd_addr <= rd_addr + 1; | |
| end | |
| default: begin | |
| wr_addr <= wr_addr; | |
| rd_addr <= rd_addr; | |
| end | |
| endcase | |
| end | |
| end | |
| // All the following formal proofs are modified from https://github.com/promach/afifo/blob/master/async_fifo.sv | |
| // and sfifo.v in http://zipcpu.com/tutorial/ex-10-fifo.zip | |
| /*See https://zipcpu.com/blog/2018/07/06/afifo.html for a formal proof of afifo in general*/ | |
| `ifdef FORMAL | |
| reg first_clock_had_passed; | |
| initial first_clock_had_passed = 0; | |
| always @(posedge clk) | |
| first_clock_had_passed <= 1; | |
| initial assume(reset); | |
| always @(posedge clk) | |
| begin | |
| if(first_clock_had_passed && $past(reset)) | |
| begin | |
| assert(rd_addr == 0); | |
| assert(!full); | |
| assert(wr_addr == 0); | |
| assert(empty); | |
| end | |
| else if(first_clock_had_passed) | |
| begin | |
| assert(count == (wr_addr - rd_addr)); | |
| assert(count <= SIZE); | |
| assert(full == (count == SIZE)); | |
| assert(empty == (count == 0)); | |
| end | |
| end | |
| always @(posedge clk) | |
| begin | |
| if (first_clock_had_passed) | |
| begin | |
| if($past(reset)) | |
| begin | |
| assert(count == 0); | |
| assert(!full); | |
| assert(empty); | |
| assert(dequeue_value == 0); | |
| end | |
| end | |
| end | |
| `endif | |
| `ifdef FORMAL | |
| //////////////////////////////////////////////////// | |
| // | |
| // Some cover statements, to make sure valuable states | |
| // are even reachable | |
| // | |
| //////////////////////////////////////////////////// | |
| // | |
| // Make sure a reset is possible | |
| always @(posedge clk) | |
| cover(reset); | |
| always @(posedge clk) | |
| if (first_clock_had_passed) | |
| cover((empty)&&(!$past(empty))); | |
| always @(*) | |
| if (first_clock_had_passed) | |
| cover(full); | |
| always @(posedge clk) | |
| if (first_clock_had_passed) | |
| cover($past(full)&&($past(enqueue_en))&&(full)); | |
| always @(posedge clk) | |
| if (first_clock_had_passed) | |
| cover($past(full)&&(!full)); | |
| always @(posedge clk) | |
| cover((full)&&(enqueue_en)); | |
| always @(posedge clk) | |
| cover(enqueue_en); | |
| always @(posedge clk) | |
| cover((empty)&&(dequeue_en)); | |
| always @(posedge clk) | |
| if (first_clock_had_passed) | |
| cover($past(!empty)&&($past(dequeue_en))&&(empty)); | |
| `endif | |
| `ifdef FORMAL | |
| /* twin-write test */ | |
| // write two pieces of different data into the synchronous fifo | |
| // then read them back from the synchronous fifo | |
| wire [WIDTH - 1:0] first_data = $anyconst; | |
| wire [WIDTH - 1:0] second_data = $anyconst; | |
| always @(*) assume(first_data != 0); | |
| always @(*) assume(second_data != 0); | |
| always @(*) assume(first_data != second_data); | |
| // for induction verification | |
| wire [ADDR_WIDTH : 0] f_first_addr = $anyconst; | |
| reg [ADDR_WIDTH : 0] f_second_addr; | |
| always @(*) f_second_addr <= f_first_addr + 1; | |
| wire wr = (enqueue_en && !full); | |
| wire rd = (dequeue_en && !empty); | |
| localparam IDLE = 0; | |
| localparam FIRST_DATA_IS_WRITTEN = 1; | |
| localparam SECOND_DATA_IS_WRITTEN = 2; | |
| localparam FIRST_DATA_IS_READ = 3; | |
| reg [1:0] f_state; | |
| initial f_state = IDLE; | |
| // See http://zipcpu.com/tutorial/lsn-10-fifo.pdf#page=21 for understanding the state machine | |
| always @(posedge clk) | |
| begin | |
| if(reset) f_state <= IDLE; | |
| else begin | |
| case(f_state) | |
| IDLE: | |
| if (wr && (wr_addr == f_first_addr) && (enqueue_value == first_data)) | |
| // Wrote first value | |
| f_state <= FIRST_DATA_IS_WRITTEN; | |
| FIRST_DATA_IS_WRITTEN: | |
| if (rd && rd_addr == f_first_addr) | |
| // Test sprung early | |
| f_state <= IDLE; | |
| else if (wr) | |
| f_state <= (enqueue_value == second_data) ? SECOND_DATA_IS_WRITTEN : IDLE; | |
| SECOND_DATA_IS_WRITTEN: | |
| if (dequeue_en && rd_addr == f_first_addr) | |
| f_state <= FIRST_DATA_IS_READ; | |
| FIRST_DATA_IS_READ: | |
| if (dequeue_en) // second data is read, thus goes back idling | |
| f_state <= IDLE; | |
| endcase | |
| end | |
| end | |
| reg f_first_addr_in_fifo, f_second_addr_in_fifo; | |
| reg [ADDR_WIDTH :0] f_distance_to_first, f_distance_to_second; | |
| always @(*) | |
| begin | |
| f_distance_to_first <= (f_first_addr - rd_addr); | |
| f_first_addr_in_fifo <= 0; | |
| if ((count != 0) && (f_distance_to_first < count)) | |
| f_first_addr_in_fifo <= 1; | |
| else | |
| f_first_addr_in_fifo <= 0; | |
| end | |
| always @(*) | |
| begin | |
| f_distance_to_second <= (f_second_addr - rd_addr); | |
| if ((count != 0) && (f_distance_to_second < count)) | |
| f_second_addr_in_fifo <= 1; | |
| else | |
| f_second_addr_in_fifo <= 0; | |
| end | |
| always @(posedge clk) | |
| begin | |
| case(f_state) | |
| IDLE: | |
| begin | |
| end | |
| FIRST_DATA_IS_WRITTEN: | |
| begin | |
| assert(f_first_addr_in_fifo); | |
| assert(data[f_first_addr] == first_data); | |
| assert(wr_addr == f_second_addr); | |
| end | |
| SECOND_DATA_IS_WRITTEN: | |
| begin | |
| assert(f_first_addr_in_fifo); | |
| assert(data[f_first_addr] == first_data); | |
| assert(f_second_addr_in_fifo); | |
| assert(data[f_second_addr] == second_data); | |
| if (dequeue_en && rd_addr == f_first_addr) | |
| assert(dequeue_value == first_data); | |
| end | |
| FIRST_DATA_IS_READ: | |
| begin | |
| assert(f_second_addr_in_fifo); | |
| assert(data[f_second_addr] == second_data); | |
| assert(dequeue_value == second_data); | |
| end | |
| endcase | |
| end | |
| `endif | |
| endmodule |
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| module test_spidergon | |
| #( | |
| `ifdef FORMAL | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=8, | |
| parameter NODE_BUFFER_WIDTH=16, | |
| `else | |
| parameter NUM_OF_NODES=8, | |
| parameter FLIT_DATA_WIDTH=16, | |
| parameter NODE_BUFFER_WIDTH=32, // a single vc buffer can hold 2 flits at one time | |
| `endif | |
| parameter NUM_OF_VIRTUAL_CHANNELS=2 // 2 vc for each input ports of each node | |
| ); | |
| reg clk, reset; | |
| // Instantiate design under test | |
| NoC | |
| #( | |
| .NUM_OF_NODES(NUM_OF_NODES), | |
| .FLIT_DATA_WIDTH(FLIT_DATA_WIDTH), | |
| .NODE_BUFFER_WIDTH(NODE_BUFFER_WIDTH), | |
| .NUM_OF_VIRTUAL_CHANNELS(NUM_OF_VIRTUAL_CHANNELS) | |
| ) | |
| noc(.clk(clk), .reset(reset)); | |
| initial begin | |
| // Dump waves | |
| $dumpfile("spidergon.vcd"); | |
| $dumpvars(0, test_spidergon); | |
| clk = 0; | |
| reset = 0; | |
| end | |
| always #5 clk = !clk; | |
| initial begin | |
| @(posedge clk); | |
| @(posedge clk); | |
| $display("Reset flop."); | |
| reset = 1; | |
| @(posedge clk); | |
| @(posedge clk); // reset is extended for one more clock cycle | |
| reset = 0; | |
| @(posedge clk); | |
| #100 $finish; | |
| end | |
| endmodule |
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