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buttercutter/CMOS_Inverter.sch

Last active January 31, 2019 07:57
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CMOS_Inverter.sch
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
C 50000 46900 1 0 0 asic-pmos-1.sym
{
T 51400 47700 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 50900 47700 5 10 1 1 0 0 1
refdes=M2
T 50900 47500 5 8 1 1 0 0 1
model-name=P1
T 50900 47200 5 8 1 0 0 0 1
w=3u
T 50900 47000 5 8 1 0 0 0 1
l=0.4u
T 50000 46900 5 10 1 0 0 0 1
m=5
}
N 50700 47400 50800 47400 4
N 50600 47900 50600 48200 4
{
T 50400 48300 5 10 1 1 0 0 1
netname=Vdd
}
C 50000 45200 1 0 0 asic-nmos-1.sym
{
T 51400 46000 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 50900 46000 5 10 1 1 0 0 1
refdes=M1
T 50900 45800 5 8 1 1 0 0 1
model-name=N1
T 50900 45500 5 8 1 0 0 0 1
w=3u
T 50900 45300 5 8 1 0 0 0 1
l=1.2u
T 50000 45200 5 10 1 0 0 0 1
m=5
}
N 50700 45700 50800 45700 4
N 50800 45100 50800 45700 4
N 50600 44900 50600 45200 4
{
T 50700 44800 5 10 1 1 0 0 1
netname=Vss
}
N 49700 47400 49700 45700 4
N 50000 47400 49700 47400 4
N 50000 45700 49700 45700 4
N 50600 46900 50600 46200 4
N 50600 45100 50800 45100 4
N 50800 47400 50800 48000 4
N 50800 48000 50600 48000 4
C 49100 46400 1 0 0 in-1.sym
{
T 49100 46700 5 10 0 0 0 0 1
device=INPUT
T 49100 46700 5 10 1 1 0 0 1
refdes=IN
T 49100 46400 5 10 0 0 0 0 1
pinseq=1
}
C 50600 46400 1 0 0 out-1.sym
{
T 50600 46700 5 10 0 0 0 0 1
device=OUTPUT
T 50700 46600 5 10 1 1 0 0 1
refdes=OUT
T 50600 46400 5 10 0 0 0 0 1
pinseq=2
}
T 46200 49200 8 10 1 1 0 0 1
spice-prolog=.subckt INV1 %up
Raw
gyrator.asc
Version 4
SHEET 1 2240 2444
WIRE 256 -48 240 -48
WIRE 448 -48 256 -48
WIRE 864 -48 448 -48
WIRE 880 -48 864 -48
WIRE 1200 -48 880 -48
WIRE 1216 -48 1200 -48
WIRE 880 -32 880 -48
WIRE 1200 -32 1200 -48
WIRE 240 0 240 -48
WIRE 864 16 864 -48
WIRE 880 16 864 16
WIRE 1216 16 1216 -48
WIRE 1216 16 1200 16
WIRE 256 48 256 -48
WIRE 256 48 240 48
WIRE 960 48 928 48
WIRE 1152 48 960 48
WIRE 192 80 160 80
WIRE 880 112 880 64
WIRE 960 112 960 48
WIRE 960 112 880 112
WIRE 1200 144 1200 64
WIRE 240 192 240 96
WIRE 384 192 240 192
WIRE 656 192 384 192
WIRE 800 192 656 192
WIRE 880 208 880 112
WIRE 1200 208 1200 144
WIRE 112 224 0 224
WIRE 160 224 160 80
WIRE 160 224 112 224
WIRE 240 224 240 192
WIRE 656 256 656 192
WIRE 896 256 880 256
WIRE 1200 256 1184 256
WIRE 0 272 0 224
WIRE 256 272 240 272
WIRE 448 288 448 -48
WIRE 800 288 800 192
WIRE 832 288 800 288
WIRE 1360 288 1248 288
WIRE 160 304 160 224
WIRE 192 304 160 304
WIRE 1360 304 1360 288
WIRE 880 320 880 304
WIRE 896 320 896 256
WIRE 896 320 880 320
WIRE 1184 320 1184 256
WIRE 1200 320 1200 304
WIRE 1200 320 1184 320
WIRE 896 336 896 320
WIRE 1008 336 896 336
WIRE 1184 336 1184 320
WIRE 1184 336 1088 336
WIRE 240 352 240 320
WIRE 256 352 256 272
WIRE 256 352 240 352
WIRE 0 416 0 352
WIRE 256 416 256 352
WIRE 256 416 0 416
WIRE 352 416 256 416
WIRE 384 416 384 272
WIRE 384 416 352 416
WIRE 448 416 448 368
WIRE 448 416 384 416
WIRE 656 416 656 320
WIRE 656 416 448 416
WIRE 896 416 656 416
WIRE 1184 416 896 416
WIRE 1360 416 1360 384
WIRE 1360 416 1184 416
WIRE 352 448 352 416
FLAG 352 448 0
FLAG 112 224 in
FLAG 240 192 out
FLAG 1200 144 in
SYMBOL nmos4 192 224 R0
SYMATTR InstName M1
SYMATTR Value n1
SYMATTR Value2 l=0.18u w=5u
SYMBOL voltage 448 272 R0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL pmos4 192 0 R0
SYMATTR InstName M2
SYMATTR Value p1
SYMATTR Value2 l=0.18u w=15u
SYMBOL current 0 272 R0
WINDOW 123 24 102 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 0
SYMBOL current 384 192 R0
WINDOW 123 24 102 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName I2
SYMATTR Value 0
SYMBOL nmos4 832 208 R0
SYMATTR InstName M3
SYMATTR Value n1
SYMATTR Value2 l=0.18u w=10u
SYMBOL nmos4 1248 208 M0
SYMATTR InstName M4
SYMATTR Value n1
SYMATTR Value2 l=0.18u w=10u
SYMBOL pmos4 1152 -32 R0
SYMATTR InstName M5
SYMATTR Value p1
SYMATTR Value2 l=0.18u w=30u
SYMBOL pmos4 928 -32 M0
SYMATTR InstName M6
SYMATTR Value p1
SYMATTR Value2 l=0.18u w=30u
SYMBOL voltage 1360 288 R0
SYMATTR InstName V2
SYMATTR Value 0.9
SYMBOL cap 640 256 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL current 1184 336 R0
WINDOW 123 24 102 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName I4
SYMATTR Value 100µ
SYMBOL current 896 336 R0
WINDOW 123 24 102 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName I5
SYMATTR Value 100µ
SYMBOL res 1104 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
TEXT 48 480 Left 2 ;.dc v1 0 1.8
TEXT 48 448 Left 2 !.op
TEXT 552 472 Left 2 !.ac dec 101 10k 10g
TEXT 264 496 Left 2 !.options TEMP=25\n.model n1 NMOS\n.model p1 PMOS
TEXT 544 536 Left 2 !.include tsmc180nmcmos.lib
Raw
mosfet_018.lib
* modified for use with LTSpice; DM 8/19/2008
*
* 0.18u CMOS process
*
* NMOS transistor model name: NM
* PMOS transistor model name: PM
*-----------------------------------------------------------------------
.subckt NM D G S B
+params: W=10u L=1u
M1 D G S B NM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends
* ----------------------------------------------------------------------
* NMOS transistor model
* ----------------------------------------------------------------------
.MODEL NM NMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : LTspice
* model : MOS BSIM3v3
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.354505
+K1 = 0.5733393 K2 = 3.177172E-3 K3 = 27.3563303
+K3B = -10 W0 = 2.341477E-5 NLX = 1.906617E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6751718 DVT1 = 0.4282625 DVT2 = 0.036004
+U0 = 327.3736992 UA = -4.52726E-11 UB = 4.46532E-19
+UC = -4.74051E-11 VSAT = 8.785346E4 A0 = 1.6897405
+AGS = 0.2908676 B0 = -8.224961E-9 B1 = -1E-7
+KETA = 0.021238 A1 = 8.00349E-4 A2 = 1
+RDSW = 105 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 5e-9 LINT = 2.351737E-8
+DWG = 1.610448E-9
+DWB = -5.108595E-9 VOFF = -0.0652968 NFACTOR = 2.4901845
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0231564 ETAB = -0.058499
+DSUB = 0.9467118 PCLM = 0.8512348 PDIBLC1 = 0.0929526
+PDIBLC2 = 0.01 PDIBLCB = -0.1 DROUT = 0.5224026
+PSCBE1 = 7.979323E10 PSCBE2 = 1.522921E-9 PVAG = 0.01
+DELTA = 0.01 RSH = 6.8 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.7E-10 CGSO = 7.7E-10 CGBO = 1E-12
+CJ = 1.010083E-3 PB = 0.7344298 MJ = 0.3565066
+CJSW = 2.441707E-10 PBSW = 0.8005503 MJSW = 0.1327842
+CJSWG = 3.3E-10 PBSWG = 0.8005503 MJSWG = 0.1327842
+CF = 0 PVTH0 = 1.307195E-3 PRDSW = -5
+PK2 = -1.022757E-3 WKETA = -4.466285E-4 LKETA = -9.715157E-3
+PU0 = 12.2704847 PUA = 4.421816E-11 PUB = 0
+PVSAT = 1.707461E3 PETA0 = 1E-4 PKETA = 2.348777E-3
*-----------------------------------------------------------------------
.subckt PM D G S B
+params: W=10u L=1u
M1 D G S B PM L={L} W={W} AS={1.1u*W} PS={2.2u+W} AD={1.1u*W} PD={2.2u+W}
.ends
* ----------------------------------------------------------------------
* PMOS transistor model
* ----------------------------------------------------------------------
.MODEL PM PMOS LEVEL=49
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : LTSPICE
* model : MOS BSIM3v3
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4120614
+K1 = 0.5590154 K2 = 0.0353896 K3 = 0
+K3B = 7.3774572 W0 = 1E-6 NLX = 1.103367E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4301522 DVT1 = 0.2156888 DVT2 = 0.1
+U0 = 128.7704538 UA = 1.908676E-9 UB = 1.686179E-21
+UC = -9.31329E-11 VSAT = 1.658944E5 A0 = 1.6076505
+AGS = 0.3740519 B0 = 1.711294E-6 B1 = 4.946873E-6
+KETA = 0.0210951 A1 = 0.0244939 A2 = 1
+RDSW = 127.0442882 PRWG = 0.5 PRWB = -0.5
+WR = 1 WINT = 5.928484E-10 LINT = 3.468805E-8
+DWG = -2.453074E-8
+DWB = 6.408778E-9 VOFF = -0.0974174 NFACTOR = 1.9740447
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1847491 ETAB = -0.2531172
+DSUB = 1.5 PCLM = 4.8842961 PDIBLC1 = 0.0156227
+PDIBLC2 = 0.1 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 1.733878E9 PSCBE2 = 5.002842E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.11E-10 CGSO = 7.11E-10 CGBO = 1E-12
+CJ = 1.179334E-3 PB = 0.8545261 MJ = 0.4117753
+CJSW = 2.215877E-10 PBSW = 0.6162997 MJSW = 0.2678074
+CJSWG = 4.22E-10 PBSWG = 0.6162997 MJSWG = 0.2678074
+CF = 0 PVTH0 = 2.283319E-3 PRDSW = 5.6431992
+PK2 = 2.813503E-3 WKETA = 2.438158E-3 LKETA = -0.0116078
+PU0 = -2.2514581 PUA = -7.62392E-11 PUB = 4.502298E-24
+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.047892E-4
* ----------------------------------------------------------------------
Raw
test_cmos_inverter.asc
Version 4
SHEET 1 2264 2956
WIRE 256 -48 240 -48
WIRE 528 -48 256 -48
WIRE 240 0 240 -48
WIRE 256 48 256 -48
WIRE 256 48 240 48
WIRE 192 80 160 80
WIRE 160 160 160 80
WIRE 240 160 240 96
WIRE 240 192 240 160
WIRE 272 192 240 192
WIRE 384 192 272 192
WIRE 112 224 0 224
WIRE 160 224 160 160
WIRE 160 224 112 224
WIRE 240 224 240 192
WIRE 0 272 0 224
WIRE 256 272 240 272
WIRE 528 288 528 -48
WIRE 160 304 160 224
WIRE 192 304 160 304
WIRE 240 352 240 320
WIRE 256 352 256 272
WIRE 256 352 240 352
WIRE 0 416 0 352
WIRE 256 416 256 352
WIRE 256 416 0 416
WIRE 352 416 256 416
WIRE 384 416 384 272
WIRE 384 416 352 416
WIRE 528 416 528 368
WIRE 528 416 384 416
WIRE 352 448 352 416
FLAG 352 448 0
FLAG 112 224 in
FLAG 272 192 out
SYMBOL nmos4 192 224 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M1
SYMATTR Value TSMC180nmN
SYMATTR Value2 L=3u W=1.2u
SYMBOL voltage 528 272 R0
SYMATTR InstName V1
SYMATTR Value 2.0
SYMBOL pmos4 192 0 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M2
SYMATTR Value TSMC180nmP
SYMATTR Value2 L=3u W=0.4u
SYMBOL current 0 272 R0
WINDOW 123 24 102 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 0
SYMBOL res 256 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 2 135 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL current 384 192 R0
WINDOW 123 39 50 Left 2
WINDOW 3 68 23 Left 2
SYMATTR Value2 AC 0
SYMATTR Value 0
SYMATTR InstName I2
TEXT 864 176 Left 2 !.op
TEXT 872 200 Left 2 !.ac dec 100 1 10g
TEXT 816 328 Left 2 !.include tsmc180nmcmos.lib
TEXT 808 256 Left 2 !;.dc I1 -165n 165n 1n
Raw
test_CMOS_Inverter.sch
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
C 48500 48300 1 0 0 vdc-1.sym
{
T 49200 49150 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 49200 49350 5 10 0 0 0 0 1
footprint=none
T 49200 48950 5 10 1 1 0 0 1
refdes=Vd
T 49200 48750 5 10 1 1 0 0 1
value='SUPPLY'
}
C 48700 48000 1 0 0 gnd-1.sym
C 50400 48300 1 0 0 vdc-1.sym
{
T 51100 49150 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 51100 49350 5 10 0 0 0 0 1
footprint=none
T 51100 49450 5 10 1 1 0 0 1
refdes=Vs
T 51100 49250 5 10 1 1 0 0 1
value=0V
}
C 50600 48000 1 0 0 gnd-1.sym
N 50700 49800 50700 49500 4
{
T 50700 49800 5 10 1 1 0 0 1
netname=Vss
}
N 48800 49900 48800 49500 4
{
T 48800 49900 5 10 1 1 0 0 1
netname=Vdd
}
C 42300 48100 1 0 0 spice-directive-1.sym
{
T 42400 48400 5 10 0 1 0 0 1
device=directive
T 42400 48500 5 10 1 1 0 0 1
refdes=A2
T 42300 48100 5 10 1 1 0 0 1
value=.GLOBAL Vdd Vss
}
C 44900 49100 1 0 0 spice-directive-1.sym
{
T 45000 49400 5 10 0 1 0 0 1
device=directive
T 45000 49500 5 10 1 1 0 0 1
refdes=A1
T 44900 49100 5 10 1 1 0 0 1
value=.INCLUDE CMOS_Inverter.net
}
C 42300 49100 1 0 0 spice-directive-1.sym
{
T 42400 49400 5 10 0 1 0 0 1
device=directive
T 42400 49500 5 10 1 1 0 0 1
refdes=A5
T 42400 49000 5 10 1 1 0 0 2
value=.PARAM SUPPLY=3.3v
.csparam vcd='SUPPLY'
}
C 44900 48100 1 0 0 spice-directive-1.sym
{
T 45000 48400 5 10 0 1 0 0 1
device=directive
T 45000 48500 5 10 1 1 0 0 1
refdes=A4
T 44900 47400 5 10 1 1 0 0 4
value=.options TEMP=25
.include tsmc180nmcmos.lib
.model n1 NMOS
.model p1 PMOS
}
T 42300 40200 9 10 1 0 0 0 37
spice-epilog=.control
save all @@m.x1.m1[gm]
save all @@m.x1.m2[gm]
save all @@m.x1.m1[gds]
save all @@m.x1.m2[gds]
op
print all
dc vin 0 $&vcd 0.01
plot vout
let d1=deriv(vout)
let d2=deriv(vin)
let d1d2=d1/d2
plot d1d2
ac dec 100 1 10G
plot loglog abs(vout/vin)
alter Rs3=0.0001
ac dec 100 1 10G
let Gm=(i(v_ip_out))/Vin
alter Rs3=1e20
plot xlog Gm
let ac_phase=unwrap((phase(vout)-phase(vin))*180/pi)
plot xlog ac_phase
alter Rs1=1e20
alter Rs2=0.0001
alter Rf=1Meg
dc Iin -165nA 165nA 1nA
plot vout
let d3=deriv(vout)
let d4=deriv(vin)
let d3d4=d3/d4
plot d3d4
ac dec 100 1 10G
plot loglog abs(vout/vin)
let ac_phase=unwrap((phase(vout)-phase(vin))*180/pi)
plot xlog ac_phase
.endc
T 44700 50200 9 14 1 0 0 0 1
Tests for X1 (CMOS Inverter) circuit block
N 51000 45900 52200 45900 4
{
T 51500 45900 5 10 0 0 0 0 1
netname=Vout
}
C 53300 46200 1 180 0 INV1-1.sym
{
T 52700 45500 5 10 1 1 180 0 1
refdes=X1
T 52500 44500 5 10 0 1 180 0 1
device=INV1
T 52500 44700 5 10 0 0 180 0 1
model-name=INV1
T 52500 45500 5 10 0 0 180 0 1
symversion=1.0
T 52500 46200 5 10 0 0 180 0 1
footprint=none
T 53300 46200 5 10 0 0 0 0 1
source=CMOS_Inverter.sch
}
C 51200 44200 1 0 0 gnd-1.sym
N 51300 44700 51300 44500 4
C 53800 44800 1 270 0 voltage-1.sym
{
T 54300 44700 5 10 0 0 270 0 1
device=VOLTAGE_SOURCE
T 53400 44400 5 10 1 1 0 0 1
refdes=Vin
T 52200 44000 5 10 1 1 0 0 1
value=DC 'SUPPLY/2' AC 1
}
C 53900 43400 1 0 0 gnd-1.sym
N 54000 43900 54000 43700 4
C 52300 46500 1 0 0 resistor-1.sym
{
T 52600 46900 5 10 0 0 0 0 1
device=RESISTOR
T 52500 46800 5 10 1 1 0 0 1
refdes=Rf
T 53000 46700 5 10 1 1 0 0 1
value=1e20
}
N 52300 46600 51900 46600 4
N 51900 46600 51900 45900 4
N 53200 46600 53700 46600 4
C 54100 44900 1 90 0 resistor-1.sym
{
T 53700 45200 5 10 0 0 90 0 1
device=RESISTOR
T 53800 45700 5 10 1 1 180 0 1
refdes=Rs1
T 53300 45200 5 10 1 1 0 0 1
value=0.0001
}
N 54000 44900 54000 44800 4
{
T 54000 44900 5 10 0 0 0 0 1
netname=Vin_source
}
N 54000 45900 54000 45800 4
C 55100 43400 1 0 1 gnd-1.sym
N 55000 43900 55000 43700 4
C 54900 44900 1 270 1 resistor-1.sym
{
T 55300 45200 5 10 0 0 90 2 1
device=RESISTOR
T 55200 45700 5 10 1 1 180 6 1
refdes=Rs2
T 55700 45200 5 10 1 1 0 6 1
value=1e20
}
N 55000 44900 55000 44800 4
{
T 55000 44900 5 10 0 0 0 0 1
netname=Iin_source
}
N 55000 45900 55000 45800 4
N 53700 46600 53700 45900 4
C 55200 44800 1 90 1 current-1.sym
{
T 54200 44200 5 10 0 0 270 2 1
device=CURRENT_SOURCE
T 55500 44500 5 10 1 1 0 6 1
refdes=Iin
T 55300 44200 5 10 1 1 180 6 1
value=DC 0 AC 1
}
N 53300 45900 55000 45900 4
{
T 54300 45900 5 10 0 0 0 0 1
netname=vin
}
C 51500 45600 1 90 1 current-1.sym
{
T 50500 45000 5 10 0 0 270 2 1
device=CURRENT_SOURCE
T 51800 45300 5 10 1 1 0 6 1
refdes=Iout
T 51600 45000 5 10 1 1 180 6 1
value=DC 0 AC 0
}
N 51300 45900 51300 45600 4
C 50100 45800 1 0 0 resistor-1.sym
{
T 50400 46200 5 10 0 0 0 0 1
device=RESISTOR
T 50300 46100 5 10 1 1 0 0 1
refdes=Rs3
T 50800 46000 5 10 1 1 0 0 1
value=1e20
}
C 49800 43300 1 0 0 gnd-1.sym
N 49900 43600 49900 43900 4
C 49700 44800 1 270 0 capacitor-1.sym
{
T 50400 44600 5 10 0 0 270 0 1
device=CAPACITOR
T 50200 44300 5 10 1 1 0 0 1
refdes=Cout
T 50600 44600 5 10 0 0 270 0 1
symversion=0.1
T 50100 44000 5 10 1 1 0 0 1
value=1n
}
N 49900 45000 49900 44800 4
C 50100 45000 1 90 0 current_probe.sym
{
T 49600 45000 5 10 0 0 90 0 1
device=CURRENT_PROBE
T 50500 45130 5 6 1 1 180 0 1
refdes=V_IP_out
T 49400 45000 5 10 0 0 90 0 1
value=DC 0V
}
N 50100 45900 49900 45900 4
N 49900 45900 49900 45600 4
Raw
tsmc180nmcmos.lib
* PSPICE TSMC180nm.lib file RWN 04/18/2010
* library file for transistor parameters for TMSC 0.18 micron process
* uses BIM parameters added 01/15/98
* can configure and attach to Nbreak and Pbreak transistors in PSpice
****
****************** 180nm TSMC parameters *************
*T14B SPICE BSIM3 VERSION 3.1 PARAMETERS
* downloaded from MOSIS 04/18/10
*http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/
* tsmc-018/t92y_mm_non_epi_thk_mtl_params.txt
*SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8
* DATE: Jun 8/01
* LOT: T14B WAF: 06
* Temperature_parameters=Default
*$
.MODEL TSMC180nmN NMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.354505
+K1 = 0.5733393 K2 = 3.177172E-3 K3 = 27.3563303
+K3B = -10 W0 = 2.341477E-5 NLX = 1.906617E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.6751718 DVT1 = 0.4282625 DVT2 = 0.036004
+U0 = 327.3736992 UA = -4.52726E-11 UB = 4.46532E-19
+UC = -4.74051E-11 VSAT = 8.785346E4 A0 = 1.6897405
+AGS = 0.2908676 B0 = -8.224961E-9 B1 = -1E-7
+KETA = 0.021238 A1 = 8.00349E-4 A2 = 1
+RDSW = 105 PRWG = 0.5 PRWB = -0.2
+WR = 1 WINT = 0 LINT = 1.351737E-8
*+XL = -2E-8 XW = -1E-8
+ DWG = 1.610448E-9
+DWB = -5.108595E-9 VOFF = -0.0652968 NFACTOR = 2.4901845
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0231564 ETAB = -0.058499
+DSUB = 0.9467118 PCLM = 0.8512348 PDIBLC1 = 0.0929526
+PDIBLC2 = 0.01 PDIBLCB = -0.1 DROUT = 0.5224026
+PSCBE1 = 7.979323E10 PSCBE2 = 1.522921E-9 PVAG = 0.01
+DELTA = 0.01 RSH = 6.8 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.7E-10 CGSO = 7.7E-10 CGBO = 1E-12
+CJ = 1.010083E-3 PB = 0.7344298 MJ = 0.3565066
+CJSW = 2.441707E-10 PBSW = 0.8005503 MJSW = 0.1327842
+CJSWG = 3.3E-10 PBSWG = 0.8005503 MJSWG = 0.1327842
+CF = 0 PVTH0 = 1.307195E-3 PRDSW = -5
+PK2 = -1.022757E-3 WKETA = -4.466285E-4 LKETA = -9.715157E-3
+PU0 = 12.2704847 PUA = 4.421816E-11 PUB = 0
+PVSAT = 1.707461E3 PETA0 = 1E-4 PKETA = 2.348777E-3 )
*
*$
.MODEL TSMC180nmP PMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4120614
+K1 = 0.5590154 K2 = 0.0353896 K3 = 0
+K3B = 7.3774572 W0 = 1E-6 NLX = 1.103367E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.4301522 DVT1 = 0.2156888 DVT2 = 0.1
+U0 = 128.7704538 UA = 1.908676E-9 UB = 1.686179E-21
+UC = -9.31329E-11 VSAT = 1.658944E5 A0 = 1.6076505
+AGS = 0.3740519 B0 = 1.711294E-6 B1 = 4.946873E-6
+KETA = 0.0210951 A1 = 0.0244939 A2 = 1
+RDSW = 127.0442882 PRWG = 0.5 PRWB = -0.5
+WR = 1 WINT = 5.428484E-10 LINT = 2.468805E-8
*+XL = -2E-8 XW = -1E-8
+DWG = -2.453074E-8
+DWB = 6.408778E-9 VOFF = -0.0974174 NFACTOR = 1.9740447
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1847491 ETAB = -0.2531172
+DSUB = 1.5 PCLM = 4.8842961 PDIBLC1 = 0.0156227
+PDIBLC2 = 0.1 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 1.733878E9 PSCBE2 = 5.002842E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.11E-10 CGSO = 7.11E-10 CGBO = 1E-12
+CJ = 1.179334E-3 PB = 0.8545261 MJ = 0.4117753
+CJSW = 2.215877E-10 PBSW = 0.6162997 MJSW = 0.2678074
+CJSWG = 4.22E-10 PBSWG = 0.6162997 MJSWG = 0.2678074
+CF = 0 PVTH0 = 2.283319E-3 PRDSW = 5.6431992
+PK2 = 2.813503E-3 WKETA = 2.438158E-3 LKETA = -0.0116078
+PU0 = -2.2514581 PUA = -7.62392E-11 PUB = 4.502298E-24
+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.047892E-4 )
*
*.ENDS
*$
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