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buttercutter / HLS_kernel_taylor.v
Created April 6, 2018 05:26
HLS generated verilog RTL code for taylor series of 1/(1-x)
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7vx485tffg1761-2,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=4.108000,HLS_SYN_LAT=13,HLS_SYN_TPT=9,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=937,HLS_SYN_LUT=380}" *)
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buttercutter / host.cpp
Last active June 11, 2018 06:30
C++ test code of HLS computation kernel for both Xillybus and RIFFA PCIe framework
// g++ -g -pedantic -Wall -Werror -Wextra -fsanitize=address -fno-omit-frame-pointer host.cpp -o host `pkg-config --cflags --libs opencv`
#include <opencv2/core/core.hpp>
//#include <opencv2/imgcodecs/imgcodecs.hpp>
#include <opencv2/highgui/highgui.hpp>
#include <unistd.h>
#include <fcntl.h>
#include <iostream>
#include <fstream> // std::ifstream, std::ofstream
#include <string>
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buttercutter / gist:3bc2842ea3d554c74f93a6a405442acd
Created April 28, 2018 16:31 — forked from tonyc/gist:1384523
Using strace and lsof

Using strace and lsof to debug blocked processes

You can use strace on a specific pid to figure out what a specific process is doing, e.g.:

strace -fp <pid>

You might see something like:

select(9, [3 5 8], [], [], {0, 999999}) = 0 (Timeout)

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buttercutter / zynq-common.h
Created April 30, 2018 16:11
/*
* (C) Copyright 2012 Michal Simek <[email protected]>
* (C) Copyright 2013 Xilinx, Inc.
*
* Common configuration options for all Zynq boards.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQ_COMMON_H
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buttercutter / compiler-gcc.h
Created April 30, 2018 16:35
#ifndef __LINUX_COMPILER_H
#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
#endif
/*
* Common definitions for all gcc versions go here.
*/
#define GCC_VERSION (__GNUC__ * 10000 \
+ __GNUC_MINOR__ * 100 \
+ __GNUC_PATCHLEVEL__)
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buttercutter / xillydemo.v
Last active June 6, 2018 14:08
verilog code for HLS kernel interfacing xillybus
//`define LOOPBACK 1
module xillydemo(PCIE_PERST_B_LS, PCIE_REFCLK_N, PCIE_REFCLK_P, PCIE_RX_N, PCIE_RX_P, GPIO_LED, PCIE_TX_N, PCIE_TX_P);
localparam STREAM_WIDTH = 128;
input PCIE_PERST_B_LS;
input PCIE_REFCLK_N;
input PCIE_REFCLK_P;
input [7:0] PCIE_RX_N;
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buttercutter / sync_fifo.sby
Last active August 27, 2020 16:24
FIFO with first-word-fall-through mechanism
[tasks]
proof
cover
[options]
proof: mode prove
proof: depth 10
cover: mode cover
cover: depth 40
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buttercutter / rgb2yuv_ila_data_file.gtkw
Last active May 31, 2018 08:07
rgb2yuv ILA waveform (to be viewed using gtkwave software) using xillybus pcie framework
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu May 31 08:06:13 2018
[*]
[dumpfile] "/home/phung/Documents/fpga_overlay/xillybus-eval-xl-virtexultrascale-2.0a/rgb2yuv_ila_data_file.vcd"
[dumpfile_mtime] "Thu May 31 08:00:47 2018"
[dumpfile_size] 170395
[savefile] "/home/phung/Documents/fpga_overlay/xillybus-eval-xl-virtexultrascale-2.0a/rgb2yuv_ila_data_file.gtkw"
[timestart] 0
[size] 1920 1130
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buttercutter / mxp_filters.ipynb
Last active June 20, 2018 02:48
Python code for Vector Processor MXP. See https://github.com/Xilinx/PYNQ/issues/641
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@buttercutter
buttercutter / PKGBUILD for SymbiYosys
Created June 14, 2018 13:16
Arch Linux installation PKGBUILD for https://github.com/YosysHQ/SymbiYosys
# Maintainer: promach
_gitname=SymbiYosys
pkgname=${_gitname}-git
pkgver=r114.983f066
pkgrel=1
pkgdesc="SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows"
arch=('x86_64')
url="https://github.com/cliffordwolf/SymbiYosys.git"
license=('GPL')
depends=('yosys')