gistfile1.diff

diff -r 530cb0bd2428 pypy/jit/backend/arm/codebuilder.py
--- a/pypy/jit/backend/arm/codebuilder.py  Thu Jan 24 18:30:38 2013 +0100
+++ b/pypy/jit/backend/arm/codebuilder.py	Thu Jan 24 20:08:12 2013 +0100
@@ -1,5 +1,5 @@
 from pypy.jit.backend.arm import arch
-from pypy.jit.backend.arm import conditions as cond
+from pypy.jit.backend.arm import conditions
 from pypy.jit.backend.arm import registers as reg
 from pypy.jit.backend.arm.arch import (WORD, FUNC_ALIGN)
 from pypy.jit.backend.arm.instruction_builder import define_instructions
@@ -19,7 +19,7 @@
 def binary_helper_call(name):
     function = getattr(arch, 'arm_%s' % name)
 
-    def f(self, c=cond.AL):
+    def f(self, c=conditions.AL):
         """Generates a call to a helper function, takes its
         arguments in r0 and r1, result is placed in r0"""
         addr = rffi.cast(lltype.Signed, function)
@@ -39,12 +39,12 @@
     def NOP(self):
         self.MOV_rr(0, 0)
 
-    def PUSH(self, regs, cond=cond.AL):
+    def PUSH(self, regs, cond=conditions.AL):
         assert reg.sp.value not in regs
         instr = self._encode_reg_list(cond << 28 | 0x92D << 16, regs)
         self.write32(instr)
 
-    def VPUSH(self, regs, cond=cond.AL):
+    def VPUSH(self, regs, cond=conditions.AL):
         nregs = len(regs)
         assert nregs > 0 and nregs <= 16
         freg = regs[0]
@@ -59,7 +59,7 @@
                 | nregs)
         self.write32(instr)
 
-    def VPOP(self, regs, cond=cond.AL):
+    def VPOP(self, regs, cond=conditions.AL):
         nregs = len(regs)
         assert nregs > 0 and nregs <= 16
         freg = regs[0]
@@ -74,7 +74,7 @@
                 | nregs)
         self.write32(instr)
 
-    def VMOV_rc(self, rt, rt2, dm, cond=cond.AL):
+    def VMOV_rc(self, rt, rt2, dm, cond=conditions.AL):
         """This instruction copies two words from two ARM core registers into a
         doubleword extension register, or from a doubleword extension register
         to two ARM core registers.
@@ -92,7 +92,7 @@
         self.write32(instr)
 
     # VMOV<c> <Dm>, <Rt>, <Rt2>
-    def VMOV_cr(self, dm, rt, rt2, cond=cond.AL):
+    def VMOV_cr(self, dm, rt, rt2, cond=conditions.AL):
         """This instruction copies two words from two ARM core registers into a
         doubleword extension register, or from a doubleword extension register
         to two ARM core registers.
@@ -109,7 +109,7 @@
                 | (dm & 0xF))
         self.write32(instr)
 
-    def VMOV_cc(self, dd, dm, cond=cond.AL):
+    def VMOV_cc(self, dd, dm, cond=conditions.AL):
         sz = 1  # for 64-bit mode
         instr = (cond << 28
                 | 0xEB << 20
@@ -120,12 +120,12 @@
                 | (dm & 0xF))
         self.write32(instr)
 
-    def VCVT_float_to_int(self, target, source, cond=cond.AL):
+    def VCVT_float_to_int(self, target, source, cond=conditions.AL):
         opc2 = 0x5
         sz = 1
         self._VCVT(target, source, cond, opc2, sz)
 
-    def VCVT_int_to_float(self, target, source, cond=cond.AL):
+    def VCVT_int_to_float(self, target, source, cond=conditions.AL):
         self._VCVT(target, source, cond, 0, 1)
 
     def _VCVT(self, target, source, cond, opc2, sz):
@@ -159,64 +159,45 @@
                 | (source & 0xF))
         self.write32(instr)
 
-    def VCVT_f64_f32(self, target, source, cond=cond.AL):
+    def VCVT_f64_f32(self, target, source, cond=conditions.AL):
         self._VCVT_single_double(target, source, cond, 1)
 
-    def VCVT_f32_f64(self, target, source, cond=cond.AL):
+    def VCVT_f32_f64(self, target, source, cond=conditions.AL):
         self._VCVT_single_double(target, source, cond, 0)
 
-    def POP(self, regs, cond=cond.AL):
+    def POP(self, regs, cond=conditions.AL):
         instr = self._encode_reg_list(cond << 28 | 0x8BD << 16, regs)
         self.write32(instr)
 
     def BKPT(self):
         """Unconditional breakpoint"""
-        self.write32(cond.AL << 28 | 0x1200070)
+        self.write32(conditions.AL << 28 | 0x1200070)
 
     # corresponds to the instruction vmrs APSR_nzcv, fpscr
-    def VMRS(self, cond=cond.AL):
+    def VMRS(self, cond=conditions.AL):
         self.write32(cond << 28 | 0xEF1FA10)
 
-    def B(self, target, c=cond.AL):
+    def B(self, target, c=conditions.AL):
         self.gen_load_int(reg.ip.value, target, cond=c)
         self.BX(reg.ip.value, c=c)
 
-    def BX(self, reg, c=cond.AL):
+    def BX(self, reg, c=conditions.AL):
         self.write32(c << 28 | 0x12FFF1 << 4 | (reg & 0xF))
 
-    def B_offs(self, target_ofs, c=cond.AL):
+    def B_offs(self, target_ofs, c=conditions.AL):
         pos = self.currpos()
         target_ofs = target_ofs - (pos + arch.PC_OFFSET)
         assert target_ofs & 0x3 == 0
         self.write32(c << 28 | 0xA << 24 | (target_ofs >> 2) & 0xFFFFFF)
 
-    def BL(self, addr, c=cond.AL):
+    def BL(self, addr, c=conditions.AL):
         target = rffi.cast(rffi.INT, addr)
         self.gen_load_int(reg.ip.value, target, cond=c)
         self.BLX(reg.ip.value, c)
 
-    def BLX(self, reg, c=cond.AL):
+    def BLX(self, reg, c=conditions.AL):
         self.write32(c << 28 | 0x12FFF3 << 4 | (reg & 0xF))
 
-    def MOVT_ri(self, rd, imm16, c=cond.AL):
-        """Move Top writes an immediate value to the top halfword of the
-        destination register. It does not affect the contents of the bottom
-        halfword."""
-        self.write32(c << 28
-                    | 0x3 << 24
-                    | (1 << 22)
-                    | ((imm16 >> 12) & 0xF) << 16
-                    | (rd & 0xF) << 12
-                    | imm16 & 0xFFF)
-
-    def MOVW_ri(self, rd, imm16, c=cond.AL):
-        """Encoding A2 of MOV, that allow to load a 16 bit constant"""
-        self.write32(c << 28
-                    | 0x3 << 24
-                    | ((imm16 >> 12) & 0xF) << 16
-                    | (rd & 0xF) << 12
-                    | imm16 & 0xFFF)
-
     DIV = binary_helper_call('int_div')
     MOD = binary_helper_call('int_mod')
     UDIV = binary_helper_call('uint_div')
@@ -243,17 +224,41 @@
         raise NotImplementedError
 
     def currpos(self):
-        raise NotImplementedError
+	raise NotImplementedError
 
-    def gen_load_int(self, r, value, cond=cond.AL):
+   #size_of_gen_load_int = 4 * WORD
+    ofs_shift = zip(range(8, 25, 8), range(12, 0, -4))
+    def _load_by_shifting(self, r, value, c=conditions.AL):
+        # to be sure it is only called for the correct cases
+        assert c != conditions.AL or 0 <= value <= 0xFFFF
+        self.MOV_ri(r, (value & 0xFF), cond=c)
+        for offset, shift in self.ofs_shift:
+            b = (value >> offset) & 0xFF
+            if b == 0:
+                continue
+            t = b | (shift << 8)
+            self.ORR_ri(r, r, imm=t, cond=c)
+
+    def gen_load_int(self, r, value, cond=conditions.AL):
         """r is the register number, value is the value to be loaded to the
         register"""
-        bottom = value & 0xFFFF
-        top = value >> 16
-        self.MOVW_ri(r, bottom, cond)
-        if top:
-            self.MOVT_ri(r, top, cond)
-    size_of_gen_load_int = 2 * WORD
+        if c != conditions.AL or 0 <= value <= 0xFFFF:
+            self._load_by_shifting(r, value, c)
+        else:
+            self.LDR_ri(r, reg.pc.value)
+            self.MOV_rr(reg.pc.value, reg.pc.value)
+            self.write32(value)
+    size_of_gen_load_int = 3 * WORD
+
+#    def gen_load_int(self, r, value, cond=conditions.AL):
+#        """r is the register number, value is the value to be loaded to the
+#        register"""
+#        bottom = value & 0xFFFF
+#        top = value >> 16
+#        self.MOVW_ri(r, bottom, cond)
+#        if top:
+#            self.MOVT_ri(r, top, cond)
+#    size_of_gen_load_int = 2 * WORD
 
 
 class OverwritingBuilder(AbstractARMv7Builder):