Spit out a grid using VHDL and Spartan 3 FPGA board

gistfile1.txt

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:18:22 12/13/2009 
-- Design Name: 
-- Module Name:    vga - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga is
  port(clk50_in  : in std_logic;
       red_out   : out std_logic;
       green_out : out std_logic;
       blue_out  : out std_logic;
       hs_out    : out std_logic;
       vs_out    : out std_logic;
   	AN3 : inout  STD_LOGIC;
		AN2 : inout  STD_LOGIC;
		AN1 : inout  STD_LOGIC;
		AN0 : inout  STD_LOGIC;
		LED : out  STD_LOGIC_VECTOR (7 downto 0)
		 
		 );
end vga;

architecture Behavioral of vga is

signal clk25              : std_logic;
signal horizontal_counter : std_logic_vector (9 downto 0);
signal vertical_counter   : std_logic_vector (9 downto 0);
signal CTR 				     : STD_LOGIC_VECTOR(12 downto 0);

begin

-- generate a 25Mhz clock
process (clk50_in)
begin
  if clk50_in'event and clk50_in='1' then
    if (clk25 = '0') then
      clk25 <= '1';
    else
      clk25 <= '0';
    end if;
	     
	if (CTR="0000000000000") then
	  if (AN0='0') then 
		 AN0 <= '1';	 
		 LED <= "11000000";             
		 AN1 <= '0';
	  elsif (AN1='0') then 
		 AN1 <= '1';	 	 
		 LED <= "11000000";             
		 AN2 <= '0';
	  elsif (AN2='0') then 
		 AN2 <= '1';	 
		 LED <= "10000000";             
		 AN3 <= '0';
	  elsif (AN3='0') then 
		 AN3 <= '1';
		 LED <= "00001110";             
		 AN0 <= '0';
	  end if;
	end if;
	CTR<=CTR+"0000000000001";
	if (CTR > "1000000000000") then   -- counter reaches 2^13
	  CTR<="0000000000000";
	end if;    
  end if;
end process;

process (clk25) 
begin
  if clk25'event and clk25 = '1' then
    if (horizontal_counter >= "0010010000" ) -- 144
    and (horizontal_counter < "1100010000" ) -- 784
    and (vertical_counter >= "0000100111" ) -- 39
    and (vertical_counter < "1000000111" ) -- 519
    then
	                           --"0010010000"
		if (horizontal_counter >= "0111010000") then
			red_out <= horizontal_counter(1) 
						and vertical_counter(1);
			green_out <= horizontal_counter(1) 
						and vertical_counter(1);
			blue_out <= horizontal_counter(1) 
						and vertical_counter(1);
		else
			red_out <= horizontal_counter(2) 
						and vertical_counter(2);
			green_out <= horizontal_counter(2) 
						and vertical_counter(2);
			blue_out <= horizontal_counter(2) 
						and vertical_counter(2);
		end if;
    else
      red_out <= '0';
      green_out <= '0';
      blue_out <= '0';
    end if;
    if (horizontal_counter > "0000000000" )
      and (horizontal_counter < "0001100001" ) -- 96+1
    then
      hs_out <= '0';
    else
      hs_out <= '1';
    end if;
    if (vertical_counter > "0000000000" )
      and (vertical_counter < "0000000011" ) -- 2+1
    then
      vs_out <= '0';
    else
      vs_out <= '1';
    end if;
    horizontal_counter <= horizontal_counter+"0000000001";
    if (horizontal_counter="1100100000") then
      vertical_counter <= vertical_counter+"0000000001";
      horizontal_counter <= "0000000000";
    end if;
    if (vertical_counter="1000001001") then		    
      vertical_counter <= "0000000000";
    end if;
  end if;
end process;

end Behavioral;