Octave ISA

octave-isa

========
Core ISA
========
000 :    Jump MEM[RS] NZP (previous operation)
       This is a relative jump.

0010 :    LoadIH R0 <- I (Load 4 bit immediate into R0 lower bits)
0011 :    LoadIL R0 <- I (Load 4 bit immediate into R0 upper bits)

0100:    Add RD <- RD + RS
0101:    Div RD <- RD / RS

0110:    And RD <- RD & RS
0111:    Xor RD <- RD ^ RS

1000:    Load RD <- MEM[RS]
1001:    Store MEM[RD] <- RS

101 :    Stack Operations (implicit operand R0)

110 :    Input RD <- Device

111 :    Output Device <- RS

================
Stack Operations
================
01: add    16
02: sub    16
03: mul    16
04: div    16
05: mod    16
06: neg    16
07: and    16
08: or    16
09: xor    16
10: not    16
11: add    32
12: sub    32
13: mul    32
14: div    32
15: mod    32
16: neg    32
17: and    32
18: or    32
19: xor    32
20: not    32
21: call (store pc and jump)
22: trap (disable interrupts, store state, and jump)
23: ret (jump to value on stack, can also be used for long jump)
24: iret (enable interrupts, restore state, and return)

Interrupt instructions use a 16 bit stack value as the memory address of the interrupt handler. Setting the handler address to FFFF disables the interrupt, because that address is guaranteed to be >= the stack pointer, and therefore an invalid location to jump to.

25: int0 enable (disable if val is FFFF)
26: int1 enable (disable if val is FFFF)
27: int2 enable (disable if val is FFFF)
28: int3 enable (disable if val is FFFF)
29: int4 enable (disable if val is FFFF)
30: int5 enable (disable if val is FFFF)
31: int6 enable (disable if val is FFFF)
32: int7 enable (disable if val is FFFF)