Created
April 30, 2021 22:59
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static const struct display_timing tianma_tm050rdzg03_timing = { | |
.pixelclock = { 29500000, 30000000, 50000000 }, | |
.hactive = { 800, 800, 800 }, | |
.hfront_porch = { 1, 40, 255 }, | |
.hback_porch = { 88, 88, 88 }, | |
.hsync_len = { 1, 48, 255 }, | |
.vactive = { 480, 480, 480 }, | |
.vfront_porch = { 1, 13, 255 }, | |
.vback_porch = { 32, 32, 32 }, | |
.vsync_len = { 3, 3, 255 }, | |
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
}; | |
static const struct panel_desc tianma_tm050rdzg03 = { | |
.timings = &tianma_tm050rdzg03_timing, | |
.num_timings = 1, | |
.bpc = 8, | |
.size = { | |
.width = 108, | |
.height = 65, | |
}, | |
.bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, | |
}; |
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