reservation_station.sv

`timescale 1ns / 1ps

module reservation_station
	#(parameter int RS_ID, int DATA_WIDTH)
	(
        input logic clk,
        input logic rst,

        register_file register_file,
        issue_bus issue,

        output logic Busy,
        output logic Polled,

        CDB_Arbiter CDB
    );

	operation_specification Op;
	register_file.register j, k;

	assign Resolved = Busy && !j.is_virtual && !k.is_virtual;

	always_comb begin
		if (rst || !issue.valid) begin
			Polled = 0;
		end
		else if (issue.rs_id != RS_ID) begin
			Polled = 'Z;
		end
		else begin
			Polled = !Busy;
		end
	end

	always_ff @(posedge clk) begin
		if (rst) begin
			Busy <= 0;
		end

		if (Polled) begin
			Op <= issue.op;
			Busy <= 1;

			case (issue.op.encoding)
				R_FORMAT : begin
					j <= register_file.read(issue.op.insn.R.rs1);
					k <= register_file.read(issue.op.insn.R.rs2);
				end
				I_FORMAT : begin
					j <= register_file.read(issue.op.insn.I.rs1);
					k <= issue.op.insn.I.imm;
				end
				S_FORMAT, B_FORMAT : begin
					j <= register_file.read(issue.op.insn.SB.rs1);
					k <= register_file.read(issue.op.insn.SB.rs2);
				end
			endcase
		end

		if (cdb.fu_acknowledgements[RS_ID]) begin
			Busy <= 0;
		end

		if (Busy && CDB.valid) begin
			if (j.is_virtual && j.data.rs_id == CDB.rs_id)
				j.data <= '{
					is_virtual: 1'b0,
					data: '{
						value: CDB.result
					}
				};

			if (k.is_virtual && k.data.rs_id == CDB.rs_id)
				k.data <= '{
					is_virtual: 1'b0,
					data: '{
						value: CDB.result
					}
				};
		end

	end
endmodule