Test.Delayed

gistfile1.hs

module Test.Delayed
  where

import CLaSH.Prelude
import CLaSH.Prelude.Explicit
import Data.Functor

import Clocks
import Delayed

-- LFSR: Linear Feedback Shift Register
lfsr' :: BitVector 16 -> BitVector 16
lfsr' s = fb ++# slice d15 d1 s
  where
    fb = s!5 `xor` s!3 `xor` s!2 `xor` s!0

lfsr :: BitVector 16 -> SClock clk -> Signal' clk Bool -> Signal' clk Bit
lfsr seed clk en = msb <$> r
  where r = regEn' clk seed en (lfsr' <$> r)

-- Counter that counts to a specified limit
counterLimit clk limit = s
  where
    s  = register' clk 0 s'
    s' = mux (s .<. signal limit) (s + 1) 0

-- Generate 2 bitstreams with the pattern:
--
-- "0000_xxxx_xxxx_xxxx_0000"
-- "0000_yyyy_yyyy_yyyy_0000"
--
-- where 'x' and 'y' are random, yet distinct, data
testInput :: (Signal' AD20 (BitVector 2), Signal' System50 (BitVector 2), Signal' DA36 Bit)
testInput = (mux genRandom ((++#) <$> r1 <*> r2) 0,0,0)
  where
    cnt       = counterLimit ad20 20
    -- use random data for bits [4:15]
    genRandom = cnt .>. 3 .&&. cnt .<. 16
    r1        = lfsr 0xACE1 ad20 genRandom
    r2        = lfsr 0x4645 ad20 genRandom

expectedOutput' :: Integer -> Integer -> (Signal' AD20 Bit, Signal' DA36 Bit, Signal' DA36 Bit) -> Signal' DA36 Bool
expectedOutput' stopWhen fifoDepth (adCs,daCs,daData) = adCsCompare
  where
    -- cs repeats the pattern: "0000_0000_0000_0000_0000_0000_0000_1111"
    dacsReg = register' da36
                ($$(bLit "0000_0000_0000_0000_0000_0000_0000_0000_1111") :: BitVector 36)
                (rotateL <$> dacsReg <*> 1)

    adcsReg = register' ad20
            ($$(bLit "0000_0000_0000_0000_1111") :: BitVector 20)
            (rotateL <$> adcsReg <*> 1)

    cnt       = counterLimit da36 36
    genRandom = cnt .<. 12
    r1        = lfsr 0x4645 da36 genRandom
    r1SR      = regEn' da36 0 genRandom ((++#) <$> (slice d10 d0 <$> r1SR) <*> r1)

    (dataVal,_) = da4 (sr2 r1SR,0)

    -- Assert that the 'cs' signal is equal to the expected 'csReg[31]' signal
    adCsCompare = assert (unsafeSynchronizer ad20 da36 adCs)
                         (unsafeSynchronizer ad20 da36 (msb <$> adcsReg))
                         daCsCompare
    daCsCompare = assert daCs (msb <$> dacsReg) dataCompare
    -- Assert that the 'daData' signal is equal to the expected 'dataVal' signal
    dataCompare = assert daData dataVal end
    --dataCompare = end

    -- Stop verifying when we have counted 'stopWhen' amount of 32-bit words
    endCount = counterLimit da36 ((stopWhen * 32)+2)
    end = (endCount .>. signal (stopWhen * 32))

expectedOutput :: (Signal' AD20 Bit, Signal' DA36 Bit, Signal' DA36 Bit) -> Signal' DA36 Bool
expectedOutput = expectedOutput' 9 3


runTest = sampleN 130 $ expectedOutput $ topEntity testInput

snd3 (_,y,_) = y