Live clock trimming on iCE40 UP5K

top.v

module top (
    output P1_2
);
    wire clk;
    assign P1_2 = clk;

    reg [9:0] trim;

    // Configure the HFOSC
	SB_HFOSC #(
        .CLKHF_DIV("0b00"), // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
        .TRIM_EN("0b1")
    ) u_hfosc (
       	.CLKHFPU(1'b1),
       	.CLKHFEN(1'b1),
        .CLKHF(clk),

        .TRIM9(trim[9]),
        .TRIM8(trim[8]),
        .TRIM7(trim[7]),
        .TRIM6(trim[6]),
        .TRIM5(trim[5]),
        .TRIM4(trim[4]),
        .TRIM3(trim[3]),
        .TRIM2(trim[2]),
        .TRIM1(trim[1]),
        .TRIM0(trim[0])
    );

    reg [16:0] cnt;

    always @(posedge clk) begin
        cnt <= cnt + 1;
        if(cnt == 0) begin
            trim <= trim + 1;
        end
    end

endmodule