HLS Blackbox Test

swap_endian.cpp

#include <hls_stream.h>
#include <ap_int.h>


void swap_endian(hls::stream<ap_uint<32> >& in, hls::stream<ap_uint<32> >& out)
{
    ap_uint<32> data;
    in >> data;
    out << (data.range(7, 0), data.range(15, 8), data.range(23, 16), data.range(31, 24));
}

swap_endian.json

{
    "c_function_name": "swap_endian",
    "rtl_top_module_name": "swap_endian",
    "c_files": [{"c_file": "swap_endian.cpp", "cflag":""}],
    "rtl_files": ["swap_endian.v"],
    "c_parameters": [
        {"c_name": "in", "c_port_direction": "in", "rtl_ports": {"FIFO_empty_flag": "in_empty_n", "FIFO_read_enable": "in_re", "FIFO_data_read_in": "in_data"}},
        {"c_name": "out", "c_port_direction": "out", "rtl_ports": {"FIFO_full_flag": "out_full_n", "FIFO_write_enable": "out_we", "FIFO_data_write_out": "out_data"}}
    ],
    "c_return": {
        "c_port_direction": "out",
        "rtl_ports": {
            "data_write_out": "ap_return"
        }
    },
    "rtl_common_signal": {
        "module_clock": "clock",
        "module_reset": "reset",
        "module_clock_enable": "clock_enable",
        "ap_ctrl_chain_protocol_idle":     "ap_idle",
        "ap_ctrl_chain_protocol_start":    "ap_start",
        "ap_ctrl_chain_protocol_ready":    "ap_ready",
        "ap_ctrl_chain_protocol_done":     "ap_done",
        "ap_ctrl_chain_protocol_continue": "ap_continue"
    },
    "rtl_performance": {
        "latency": 0,
        "II": 1
    },
    "rtl_resource_usage": {
        "FF": 0,
        "LUT": 100,
        "BRAM": 0,
        "URAM": 0,
        "DSP": 0
    }
}

swap_endian.v

module swap_endian(
    input   wire        clock,
    input   wire        reset,
    input   wire        clock_enable,
    input   wire [31:0] in_data,
    input   wire        in_re,
    output  wire        in_empty_n,
    output  wire [31:0] out_data,
    output  wire        out_we,
    input   wire        out_full_n,

    output  wire        ap_return,
    output  wire        ap_idle,
    input   wire        ap_start,
    output  wire        ap_ready,
    output  wire        ap_done,
    input   wire        ap_continue
);

assign ap_return = 1;
assign ap_idle   = 1;
assign ap_ready  = 1;
assign ap_done   = 1;

assign out_data  = {in_data[7:0], in_data[15:8], in_data[23:16], in_data[31:24]};
assign out_we =  in_re && clock_enable;
assign in_empty_n  =  out_full_n || !clock_enable;

endmodule

test.cpp

#include <ap_int.h>
#include <hls_stream.h>

void swap_endian(hls::stream<ap_uint<32> >& in, hls::stream<ap_uint<32> >& out);

static void copy_stream(hls::stream<ap_uint<32> >& in, hls::stream<ap_uint<32> >& out)
{
#pragma HLS PIPELINE II=1
	ap_uint<32> data;
	in >> data;
	out << data;
}
void cmod_test(hls::stream<ap_uint<32> >& in, hls::stream<ap_uint<32> >& out)
{
#pragma HLS DATAFLOW
	hls::stream< ap_uint<32> > in_;
	hls::stream< ap_uint<32> > out_;

	copy_stream(in, in_);
	swap_endian(in_, out_);
	copy_stream(out_, out);
}