Created
August 17, 2022 01:58
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| final static int RegDst = 0; | |
| final static int ALUSrc = 1; | |
| final static int MemtoReg = 2; | |
| final static int RegWrite = 3; | |
| final static int MemRead= 4; | |
| final static int MemWrite = 5; | |
| final static int Branch = 6; | |
| final static int ALUOp1 = 7; | |
| final static int ALUOp0 = 8; | |
| public static circuit[] main_control(circuit[] opcode) | |
| { | |
| circuit[] ans = new circuit[9]; | |
| ans[RegDst] = and(not(opcode[0]),and(not(opcode[1]),and(not(opcode[2]), | |
| and(not(opcode[3]),and(not(opcode[4]),not(opcode[5])))))); | |
| ans[ALUSrc] = and(opcode[5],and(not(opcode[4]),and(not(opcode[2]),and(opcode[\ | |
| 1], | |
| opcode[0])))); | |
| ans[MemtoReg] = and(opcode[5],and(not(opcode[4]),and(not(opcode[3]), | |
| and(not(opcode[2]),and(opcode[1],opcode[0]))))); | |
| ans[RegWrite] = and(not(opcode[4]),and(not(opcode[3]),not(opcode[2]))); | |
| ans[MemRead] = and(opcode[5],and(not(opcode[4]),and(not(opcode[3]), | |
| and(not(opcode[2]),and(opcode[1],opcode[0]))))); | |
| ans[MemWrite] = and(opcode[5],and(not(opcode[4]),and(opcode[3], | |
| and(not(opcode[2]),and(opcode[1],opcode[0]))))); | |
| ans[Branch] = and(not(opcode[5]),and(not(opcode[4]),and(not(opcode[3]), | |
| and(opcode[2],and(not(opcode[1]),not(opcode[0])))))); | |
| ans[ALUOp1] = and(not(opcode[0]),and(not(opcode[1]),and(not(opcode[2]), | |
| and(not(opcode[3]),and(not(opcode[4]),not(opcode[5])))))); | |
| ans[ALUOp0] = and(not(opcode[5]),and(not(opcode[4]),and(not(opcode[3]), | |
| and(opcode[2],and(not(opcode[1]),not(opcode[0])))))); | |
| return ans; | |
| } |
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