Rockchip does not publish documentation about the contents of the (PMU)SGRF register block in the RK3399. This document attempts to compile what is known through various documents, code drops and experiments.
Unless otherwise noted, SGRF registers are 16 bits wide and are accessed with 32-bit accesses (and 4-byte alignment), where the upper half is a write mask. Registers are identified by their offset, e. g. :reg:`R0x1C` would refer to the 8th register in the block. Bit ranges such as :reg:`R0x40[10:13]` are inclusive. Bit positions are counted from 0, the least significant bit.
