knightrider.vh

`timescale 1ns / 1ps

module knightrider(
    input rst,
    input clk,
    input ce,
    output [7:0] out
    );
	 
	parameter START = 8'b00001110;
	parameter END   = 8'b01110000;	 

	reg dir;
	reg ld;

	shiftreg_8 shr (
		 .din(1'b0), 
		 .dload(START), 
		 .data(out), 
		 .rst(rst), 
		 .ce(ce), 
		 .clk(clk), 
		 .dir(dir), 
		 .ld(ld)
		 );
	
	always @ (posedge clk) begin
		case(out)
			8'b0: begin
				dir <= 0;
				ld <= 1;
			end
			START: begin
				ld <= 0;			
				dir <= 0;
			end
			END: begin 
				ld <= 0;
				dir <= 1;
			end
		endcase
	end

endmodule