Created
March 3, 2016 02:41
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| 03:39:07+414 [ ] Element with id `start_archlinux2` not found | |
| 03:39:07+414 [ ] Element with id `start_freedos_test` not found | |
| 03:39:07+414 [ ] Element with id `start_kolibrios-fallback` not found | |
| 03:39:07+414 [ ] Element with id `start_dexos` not found | |
| 03:39:07+414 [ ] Element with id `start_dsl` not found | |
| 03:39:07+414 [ ] Element with id `start_ttylinux` not found | |
| 03:39:07+414 [ ] Element with id `start_9pboot` not found | |
| 03:39:07+414 [ ] Element with id `start_windows98_boot` not found | |
| 03:39:07+414 [ ] Element with id `start_windows98` not found | |
| 03:39:07+414 [ ] Element with id `start_windows31` not found | |
| 03:39:07+414 [ ] Element with id `start_windows30` not found | |
| 03:39:07+414 [ ] Element with id `start_windows30_quick` not found | |
| 03:39:07+477 [IO ] mmap_register addr=0x08000000 size=0xF8000000 | |
| 03:39:07+481 [IO ] mmap_register addr=0xFFF00000 size=0x00100000 | |
| 03:39:07+482 [PCI ] PCI register bdf=0x0 (82441FX PMC) | |
| 03:39:07+482 [PCI ] PCI register bdf=0x8 (82371SB PIIX3 ISA) | |
| 03:39:07+482 [IO ] mmap_register addr=0xFEE00000 size=0x00100000 | |
| 03:39:07+482 [IO ] mmap_register addr=0xFEC00000 size=0x00020000 | |
| 03:39:07+483 [PCI ] PCI register bdf=0x38 (acpi) | |
| 03:39:07+483 [RTC ] cmos 0x38 <- 0x21 | |
| 03:39:07+483 [RTC ] cmos 0x3D <- 0x13 | |
| 03:39:07+483 [RTC ] cmos 0x15 <- 0x80 | |
| 03:39:07+483 [RTC ] cmos 0x16 <- 0x2 | |
| 03:39:07+483 [RTC ] cmos 0x17 <- 0xFF | |
| 03:39:07+483 [RTC ] cmos 0x18 <- 0xFF | |
| 03:39:07+483 [RTC ] cmos 0x30 <- 0xFF | |
| 03:39:07+483 [RTC ] cmos 0x31 <- 0xFF | |
| 03:39:07+483 [RTC ] cmos 0x34 <- 0x0 | |
| 03:39:07+483 [RTC ] cmos 0x35 <- 0x7 | |
| 03:39:07+483 [RTC ] cmos 0x5B <- 0x0 | |
| 03:39:07+483 [RTC ] cmos 0x5C <- 0x0 | |
| 03:39:07+483 [RTC ] cmos 0x5D <- 0x0 | |
| 03:39:07+483 [RTC ] cmos 0x14 <- 0x2F | |
| 03:39:07+483 [RTC ] cmos 0x5F <- 0x0 | |
| 03:39:07+483 [PCI ] PCI register bdf=0x90 (vga) | |
| 03:39:07+485 [IO ] mmap_register addr=0x000A0000 size=0x00020000 | |
| 03:39:07+485 [IO ] mmap_register addr=0xE0000000 size=0x00800000 | |
| 03:39:07+486 [RTC ] cmos 0x10 <- 0x40 | |
| 03:39:07+487 [RTC ] cmos 0x39 <- 0x1 | |
| 03:39:07+487 [RTC ] cmos 0x12 <- 0xF0 | |
| 03:39:07+487 [RTC ] cmos 0x1B <- 0xCF | |
| 03:39:07+487 [RTC ] cmos 0x1C <- 0xF3 | |
| 03:39:07+487 [RTC ] cmos 0x1D <- 0x10 | |
| 03:39:07+487 [RTC ] cmos 0x1E <- 0xFF | |
| 03:39:07+487 [RTC ] cmos 0x1F <- 0xFF | |
| 03:39:07+487 [RTC ] cmos 0x20 <- 0xC8 | |
| 03:39:07+487 [RTC ] cmos 0x21 <- 0xCF | |
| 03:39:07+487 [RTC ] cmos 0x22 <- 0xF3 | |
| 03:39:07+487 [RTC ] cmos 0x23 <- 0x3F | |
| 03:39:07+488 [PCI ] PCI register bdf=0xF0 (ide0) | |
| 03:39:07+488 [PCI ] PCI register bdf=0x28 (ne2k) | |
| 03:39:07+488 [NET ] Mac: 0x00:0x22:0x15:0x28:0x0D:0x1A | |
| 03:39:07+489 [PCI ] PCI register bdf=0x30 (virtio) | |
| 03:39:07+498 [RTC ] cmos read from index 0xF | |
| 03:39:07+508 [BIOS] SeaBIOS (version 1.7.5.2-20150319_155624-eevee) | |
| 03:39:07+514 [BIOS] enabling shadow ram | |
| 03:39:07+514 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+515 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+515 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| Previous message repeated 2 times | |
| 03:39:07+516 [PCI ] PCI data2: 0x33 addr=0x80000058 | |
| 03:39:07+516 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:07+516 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:07+516 [PCI ] PCI data3: 0x33 addr=0x80000058 | |
| 03:39:07+517 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x0058 value=0x33330000 | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] PCI data0: 0x33 addr=0x8000005C | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] PCI data1: 0x33 addr=0x8000005C | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] PCI data2: 0x33 addr=0x8000005C | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:07+517 [PCI ] PCI data3: 0x33 addr=0x8000005C | |
| 03:39:07+518 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x005C value=0x33333333 | |
| 03:39:07+663 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:07+663 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:07+663 [PCI ] PCI data1: 0x30 addr=0x80000058 | |
| 03:39:07+733 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+733 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+733 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:39:07+733 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:39:07+733 [RTC ] cmos read from index 0x34 | |
| 03:39:07+733 [RTC ] cmos read from index 0x35 | |
| 03:39:07+735 [BIOS] Add to e820 map: 00000000 08000000 1 | |
| 03:39:07+741 [BIOS] Add to e820 map: fffc0000 00040000 2 | |
| 03:39:07+744 [BIOS] RamSize: 0x08000000 [cmos] | |
| 03:39:07+746 [BIOS] malloc preinit | |
| 03:39:07+749 [BIOS] Add to e820 map: 000a0000 00050000 -1 | |
| 03:39:07+749 [BIOS] Add to e820 map: 000f0000 00010000 2 | |
| 03:39:07+751 [BIOS] Add to e820 map: 07fc0000 00040000 2 | |
| 03:39:07+757 [BIOS] _malloc zone=0x000eebcc size=59520 align=10 ret=0x07fb16c0 (detail=0x07fbff40) | |
| 03:39:07+758 [BIOS] Relocating init from 0x000e03d9 to 0x07fb16c0 (size 59520) | |
| 03:39:07+764 [BIOS] malloc init | |
| 03:39:07+772 [IO ] write16 port #0x0510 <- 0x0000 (PORT_QEMU_CFG_CTL) | |
| 03:39:07+772 [IO ] read8 port #0x0511 (PORT_QEMU_CFG_DATA) | |
| 03:39:07+772 [BIOS] init ivt | |
| 03:39:07+772 [RTC ] cmos write index 0xF: 0x0 | |
| 03:39:07+778 [BIOS] init bda | |
| 03:39:07+780 [BIOS] Add to e820 map: 0009fc00 00000400 2 | |
| 03:39:07+781 [RTC ] cmos read from index 0x38 | |
| 03:39:07+781 [RTC ] cmos read from index 0x3D | |
| 03:39:07+781 [RTC ] cmos read from index 0x38 | |
| 03:39:07+781 [BIOS] init bios32 | |
| 03:39:07+781 [BIOS] init PMM | |
| 03:39:07+782 [BIOS] init PNPBIOS table | |
| 03:39:07+782 [BIOS] init keyboard | |
| 03:39:07+782 [BIOS] init mouse | |
| 03:39:07+783 [IO ] write8 port #0x000D <- 0x00 (PORT_DMA1_MASTER_CLEAR) | |
| 03:39:07+783 [IO ] write8 port #0x00DA <- 0x00 (PORT_DMA2_MASTER_CLEAR) | |
| 03:39:07+783 [IO ] write8 port #0x00D6 <- 0xC0 (PORT_DMA2_MODE_REG) | |
| 03:39:07+783 [IO ] write8 port #0x00D4 <- 0x00 (PORT_DMA2_MASK_REG) | |
| 03:39:07+783 [BIOS] init pic | |
| 03:39:07+783 [BIOS] math cp init | |
| 03:39:07+784 [IO ] write8 port #0x0061 <- 0x31 (PORT_PS2_CTRLB) | |
| 03:39:07+786 [IO ] write8 port #0x0061 <- 0x30 (PORT_PS2_CTRLB) | |
| 03:39:07+789 [BIOS] tsc calibrate start=2563072 end=2576629 diff=13557 | |
| 03:39:07+790 [BIOS] CPU Mhz=7 | |
| 03:39:07+790 [BIOS] init timer | |
| 03:39:07+790 [RTC ] Periodic interrupt, a=0x26 t=0.9765625 | |
| 03:39:07+790 [RTC ] cmos b=0x02 | |
| 03:39:07+790 [RTC ] cmos reg C read | |
| 03:39:07+790 [BIOS] pci setup | |
| 03:39:07+791 [BIOS] === PCI bus & bridge init === | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+791 [BIOS] PCI: pci_bios_init_bus_rec bus = 0x0 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x00 0x80002800 -> 0x802910EC | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x08 0x80002808 -> 0x02000000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x0C 0x8000280C -> 0x00000000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x00 0x80003000 -> 0x10091AF4 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x08 0x80003008 -> 0x00020000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x0C 0x8000300C -> 0x00000000 | |
| 03:39:07+791 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:39:07+792 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:39:07+792 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:39:07+792 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:39:07+792 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:39:07+792 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:39:07+793 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x00 0x80002800 -> 0x802910EC | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x08 0x80002808 -> 0x02000000 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x0C 0x8000280C -> 0x00000000 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x00 0x80003000 -> 0x10091AF4 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x08 0x80003008 -> 0x00020000 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x0C 0x8000300C -> 0x00000000 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:39:07+794 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:39:07+795 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:39:07+796 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:39:07+796 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:39:07+799 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:07+799 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:39:07+799 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:07+799 [BIOS] === PCI device probing === | |
| 03:39:07+799 [BIOS] PCI probe | |
| 03:39:07+800 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+802 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb1610 (detail=0x07fb1630) | |
| 03:39:07+802 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+802 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:07+802 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:07+803 [BIOS] PCI device 00:00.0 (vd=8086:1237 c=0600) | |
| 03:39:07+803 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:07+803 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:39:07+805 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb15c0 (detail=0x07fb15e0) | |
| 03:39:07+805 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:39:07+805 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:39:07+806 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:39:07+808 [BIOS] PCI device 00:01.0 (vd=8086:7000 c=0601) | |
| 03:39:07+808 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:39:07+808 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x00 0x80002800 -> 0x802910EC | |
| 03:39:07+809 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb1570 (detail=0x07fb1590) | |
| 03:39:07+809 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x00 0x80002800 -> 0x802910EC | |
| 03:39:07+809 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x08 0x80002808 -> 0x02000000 | |
| 03:39:07+809 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x0C 0x8000280C -> 0x00000000 | |
| 03:39:07+810 [BIOS] PCI device 00:05.0 (vd=10ec:8029 c=0200) | |
| 03:39:07+810 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x0C 0x8000280C -> 0x00000000 | |
| 03:39:07+810 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x00 0x80003000 -> 0x10091AF4 | |
| 03:39:07+812 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb1520 (detail=0x07fb1540) | |
| 03:39:07+812 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x00 0x80003000 -> 0x10091AF4 | |
| 03:39:07+812 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x08 0x80003008 -> 0x00020000 | |
| 03:39:07+812 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x0C 0x8000300C -> 0x00000000 | |
| 03:39:07+813 [BIOS] PCI device 00:06.0 (vd=1af4:1009 c=0002) | |
| 03:39:07+813 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x0C 0x8000300C -> 0x00000000 | |
| 03:39:07+813 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:39:07+815 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb14d0 (detail=0x07fb14f0) | |
| 03:39:07+816 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:39:07+816 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:39:07+816 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:39:07+816 [BIOS] PCI device 00:07.0 (vd=8086:7113 c=0680) | |
| 03:39:07+816 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:39:07+816 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:39:07+817 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb1480 (detail=0x07fb14a0) | |
| 03:39:07+817 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:39:07+817 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:39:07+817 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:39:07+817 [BIOS] PCI device 00:12.0 (vd=10de:0a20 c=0300) | |
| 03:39:07+817 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:39:07+817 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:07+818 [BIOS] _malloc zone=0x07fbfeb3 size=32 align=10 ret=0x07fb1430 (detail=0x07fb1450) | |
| 03:39:07+818 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:07+818 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:39:07+819 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:07+820 [BIOS] PCI device 00:1e.0 (vd=8086:3a20 c=0101) | |
| 03:39:07+820 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:07+820 [BIOS] Found 7 PCI devices (max PCI bus is 00) | |
| 03:39:07+820 [BIOS] === PCI new allocation pass #1 === | |
| 03:39:07+820 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb13d0 (detail=0x07fb1400) | |
| 03:39:07+820 [BIOS] PCI: check devices | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000010 | |
| 03:39:07+821 [PCI ] BAR0 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000010 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000010 | |
| 03:39:07+821 [PCI ] BAR0 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000014 | |
| 03:39:07+821 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000014 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000014 | |
| 03:39:07+821 [PCI ] BAR1 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000018 | |
| 03:39:07+821 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000018 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000018 | |
| 03:39:07+821 [PCI ] BAR2 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x8000001C | |
| 03:39:07+821 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x8000001C | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x8000001C | |
| 03:39:07+821 [PCI ] BAR3 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000020 | |
| 03:39:07+821 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000020 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000020 | |
| 03:39:07+821 [PCI ] BAR4 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0xFF addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data1: 0xFF addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000024 | |
| 03:39:07+821 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000024 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000024 | |
| 03:39:07+821 [PCI ] BAR5 exists=n changed to 0x0 dev=0x00 (82441FX PMC) | |
| 03:39:07+821 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0x00000000 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0x00000000 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data1: 0xF8 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data2: 0xFF addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data3: 0xFF addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFFFFF800 | |
| 03:39:07+821 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFFFFF800 | |
| 03:39:07+821 [PCI ] PCI data0: 0x00 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data1: 0x00 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data2: 0x00 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI data3: 0x00 addr=0x80000030 | |
| 03:39:07+821 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x0030 value=0x00000000 | |
| 03:39:07+822 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1370 (detail=0x07fb13a0) | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x10 0x80000810 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x10 0x80000810 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x80000810 | |
| 03:39:07+822 [PCI ] BAR0 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x10 0x80000810 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x10 0x80000810 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0x00 addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data1: 0x00 addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data2: 0x00 addr=0x80000810 | |
| 03:39:07+822 [PCI ] PCI data3: 0x00 addr=0x80000810 | |
| 03:39:07+822 [PCI ] BAR0 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x14 0x80000814 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x14 0x80000814 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x80000814 | |
| 03:39:07+822 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x14 0x80000814 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x14 0x80000814 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0x00 addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data1: 0x00 addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data2: 0x00 addr=0x80000814 | |
| 03:39:07+822 [PCI ] PCI data3: 0x00 addr=0x80000814 | |
| 03:39:07+822 [PCI ] BAR1 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x18 0x80000818 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x18 0x80000818 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x80000818 | |
| 03:39:07+822 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x18 0x80000818 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x18 0x80000818 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0x00 addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data1: 0x00 addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data2: 0x00 addr=0x80000818 | |
| 03:39:07+822 [PCI ] PCI data3: 0x00 addr=0x80000818 | |
| 03:39:07+822 [PCI ] BAR2 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x1C 0x8000081C -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x1C 0x8000081C -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x8000081C | |
| 03:39:07+822 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x1C 0x8000081C -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x1C 0x8000081C -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0x00 addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data1: 0x00 addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data2: 0x00 addr=0x8000081C | |
| 03:39:07+822 [PCI ] PCI data3: 0x00 addr=0x8000081C | |
| 03:39:07+822 [PCI ] BAR3 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x20 0x80000820 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x20 0x80000820 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x80000820 | |
| 03:39:07+822 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x20 0x80000820 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x20 0x80000820 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0x00 addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data1: 0x00 addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data2: 0x00 addr=0x80000820 | |
| 03:39:07+822 [PCI ] PCI data3: 0x00 addr=0x80000820 | |
| 03:39:07+822 [PCI ] BAR4 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+822 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x24 0x80000824 -> 0x00000000 | |
| 03:39:07+822 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x24 0x80000824 -> 0x00000000 | |
| 03:39:07+822 [PCI ] PCI data0: 0xFF addr=0x80000824 | |
| 03:39:07+822 [PCI ] PCI data1: 0xFF addr=0x80000824 | |
| 03:39:07+822 [PCI ] PCI data2: 0xFF addr=0x80000824 | |
| 03:39:07+822 [PCI ] PCI data3: 0xFF addr=0x80000824 | |
| 03:39:07+823 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+823 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x24 0x80000824 -> 0x00000000 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x24 0x80000824 -> 0x00000000 | |
| 03:39:07+823 [PCI ] PCI data0: 0x00 addr=0x80000824 | |
| 03:39:07+823 [PCI ] PCI data1: 0x00 addr=0x80000824 | |
| 03:39:07+823 [PCI ] PCI data2: 0x00 addr=0x80000824 | |
| 03:39:07+823 [PCI ] PCI data3: 0x00 addr=0x80000824 | |
| 03:39:07+823 [PCI ] BAR5 exists=n changed to 0x0 dev=0x01 (82371SB PIIX3 ISA) | |
| 03:39:07+823 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0x00000000 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0x00000000 | |
| 03:39:07+823 [PCI ] PCI data0: 0x00 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data1: 0xF8 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data2: 0xFF addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data3: 0xFF addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI write dev=0x01 (82371SB PIIX3 ISA) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0xFFFFF800 | |
| 03:39:07+823 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0xFFFFF800 | |
| 03:39:07+823 [PCI ] PCI data0: 0x00 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data1: 0x00 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data2: 0x00 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI data3: 0x00 addr=0x80000830 | |
| 03:39:07+823 [PCI ] PCI write dev=0x01 (82371SB PIIX3 ISA) addr=0x0030 value=0x00000000 | |
| 03:39:07+824 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1310 (detail=0x07fb1340) | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0x00000301 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0x00000301 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002810 | |
| 03:39:07+824 [PCI ] BAR0 exists=y changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] io bar changed from 0x00000300 to 0x0000FFE0 size=32 | |
| 03:39:07+824 [ ] from=0x300 to=0xFFE0 count=32 | |
| 03:39:07+824 [PCI ] BAR effective value: 0xFFFFFFE1 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0xFFFFFFE1 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0xFFFFFFE1 | |
| 03:39:07+824 [PCI ] PCI data0: 0x01 addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data1: 0x03 addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x80002810 | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x80002810 | |
| 03:39:07+824 [PCI ] BAR0 exists=y changed to 0x301 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] io bar changed from 0x0000FFE0 to 0x00000300 size=32 | |
| 03:39:07+824 [ ] from=0xFFE0 to=0x300 count=32 | |
| 03:39:07+824 [PCI ] BAR effective value: 0x301 | |
| 03:39:07+824 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb12b0 (detail=0x07fb12e0) | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x14 0x80002814 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x14 0x80002814 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002814 | |
| 03:39:07+824 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x14 0x80002814 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x14 0x80002814 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x80002814 | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x80002814 | |
| 03:39:07+824 [PCI ] BAR1 exists=n changed to 0x0 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x18 0x80002818 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x18 0x80002818 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002818 | |
| 03:39:07+824 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x18 0x80002818 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x18 0x80002818 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x80002818 | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x80002818 | |
| 03:39:07+824 [PCI ] BAR2 exists=n changed to 0x0 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x1C 0x8000281C -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x1C 0x8000281C -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x8000281C | |
| 03:39:07+824 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x1C 0x8000281C -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x1C 0x8000281C -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x8000281C | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x8000281C | |
| 03:39:07+824 [PCI ] BAR3 exists=n changed to 0x0 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x20 0x80002820 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x20 0x80002820 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002820 | |
| 03:39:07+824 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x20 0x80002820 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x20 0x80002820 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x80002820 | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x80002820 | |
| 03:39:07+824 [PCI ] BAR4 exists=n changed to 0x0 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x24 0x80002824 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x24 0x80002824 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0xFF addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data1: 0xFF addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002824 | |
| 03:39:07+824 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x24 0x80002824 -> 0x00000000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x24 0x80002824 -> 0x00000000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data2: 0x00 addr=0x80002824 | |
| 03:39:07+824 [PCI ] PCI data3: 0x00 addr=0x80002824 | |
| 03:39:07+824 [PCI ] BAR5 exists=n changed to 0x0 dev=0x05 (ne2k) | |
| 03:39:07+824 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFEB80000 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFEB80000 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data1: 0xF8 addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data2: 0xFF addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFF addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI write dev=0x05 (ne2k) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFFFFF800 | |
| 03:39:07+824 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFFFFF800 | |
| 03:39:07+824 [PCI ] PCI data0: 0x00 addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data1: 0x00 addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data2: 0xB8 addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI data3: 0xFE addr=0x80002830 | |
| 03:39:07+824 [PCI ] PCI write dev=0x05 (ne2k) addr=0x0030 value=0xFEB80000 | |
| 03:39:07+825 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1250 (detail=0x07fb1280) | |
| 03:39:07+825 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0x0000A801 | |
| 03:39:07+825 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0x0000A801 | |
| 03:39:07+825 [PCI ] PCI data0: 0xFF addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data1: 0xFF addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data2: 0xFF addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data3: 0xFF addr=0x80003010 | |
| 03:39:07+825 [PCI ] BAR0 exists=y changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+825 [PCI ] io bar changed from 0x0000A800 to 0x0000FF00 size=256 | |
| 03:39:07+825 [ ] from=0xA800 to=0xFF00 count=256 | |
| 03:39:07+825 [PCI ] BAR effective value: 0xFFFFFF01 | |
| 03:39:07+825 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0xFFFFFF01 | |
| 03:39:07+825 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0xFFFFFF01 | |
| 03:39:07+825 [PCI ] PCI data0: 0x01 addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data1: 0xA8 addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data2: 0x00 addr=0x80003010 | |
| 03:39:07+825 [PCI ] PCI data3: 0x00 addr=0x80003010 | |
| 03:39:07+825 [PCI ] BAR0 exists=y changed to 0xA801 dev=0x06 (virtio) | |
| 03:39:07+825 [PCI ] io bar changed from 0x0000FF00 to 0x0000A800 size=256 | |
| 03:39:07+825 [ ] from=0xFF00 to=0xA800 count=256 | |
| 03:39:07+825 [PCI ] BAR effective value: 0xA801 | |
| 03:39:07+826 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb11f0 (detail=0x07fb1220) | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x14 0x80003014 -> 0xFEBF1000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x14 0x80003014 -> 0xFEBF1000 | |
| 03:39:07+826 [PCI ] PCI data0: 0xFF addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data1: 0xFF addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x80003014 | |
| 03:39:07+826 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x14 0x80003014 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x14 0x80003014 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data1: 0x10 addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data2: 0xBF addr=0x80003014 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFE addr=0x80003014 | |
| 03:39:07+826 [PCI ] BAR1 exists=n changed to 0xFEBF1000 dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x18 0x80003018 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x18 0x80003018 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0xFF addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data1: 0xFF addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x80003018 | |
| 03:39:07+826 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x18 0x80003018 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x18 0x80003018 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data1: 0x00 addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data2: 0x00 addr=0x80003018 | |
| 03:39:07+826 [PCI ] PCI data3: 0x00 addr=0x80003018 | |
| 03:39:07+826 [PCI ] BAR2 exists=n changed to 0x0 dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x1C 0x8000301C -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x1C 0x8000301C -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0xFF addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data1: 0xFF addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x8000301C | |
| 03:39:07+826 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x1C 0x8000301C -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x1C 0x8000301C -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data1: 0x00 addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data2: 0x00 addr=0x8000301C | |
| 03:39:07+826 [PCI ] PCI data3: 0x00 addr=0x8000301C | |
| 03:39:07+826 [PCI ] BAR3 exists=n changed to 0x0 dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x20 0x80003020 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x20 0x80003020 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0xFF addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data1: 0xFF addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x80003020 | |
| 03:39:07+826 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x20 0x80003020 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x20 0x80003020 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data1: 0x00 addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data2: 0x00 addr=0x80003020 | |
| 03:39:07+826 [PCI ] PCI data3: 0x00 addr=0x80003020 | |
| 03:39:07+826 [PCI ] BAR4 exists=n changed to 0x0 dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x24 0x80003024 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x24 0x80003024 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0xFF addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data1: 0xFF addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x80003024 | |
| 03:39:07+826 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x24 0x80003024 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x24 0x80003024 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data1: 0x00 addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data2: 0x00 addr=0x80003024 | |
| 03:39:07+826 [PCI ] PCI data3: 0x00 addr=0x80003024 | |
| 03:39:07+826 [PCI ] BAR5 exists=n changed to 0x0 dev=0x06 (virtio) | |
| 03:39:07+826 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0x00000000 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0x00000000 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data1: 0xF8 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data2: 0xFF addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data3: 0xFF addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI write dev=0x06 (virtio) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0xFFFFF800 | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0xFFFFF800 | |
| 03:39:07+826 [PCI ] PCI data0: 0x00 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data1: 0x00 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data2: 0x00 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI data3: 0x00 addr=0x80003030 | |
| 03:39:07+826 [PCI ] PCI write dev=0x06 (virtio) addr=0x0030 value=0x00000000 | |
| 03:39:07+826 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1190 (detail=0x07fb11c0) | |
| 03:39:07+826 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x10 0x80003810 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x10 0x80003810 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003810 | |
| 03:39:07+827 [PCI ] BAR0 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x10 0x80003810 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x10 0x80003810 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003810 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003810 | |
| 03:39:07+827 [PCI ] BAR0 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x14 0x80003814 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x14 0x80003814 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003814 | |
| 03:39:07+827 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x14 0x80003814 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x14 0x80003814 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003814 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003814 | |
| 03:39:07+827 [PCI ] BAR1 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x18 0x80003818 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x18 0x80003818 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003818 | |
| 03:39:07+827 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x18 0x80003818 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x18 0x80003818 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003818 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003818 | |
| 03:39:07+827 [PCI ] BAR2 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x1C 0x8000381C -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x1C 0x8000381C -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x8000381C | |
| 03:39:07+827 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x1C 0x8000381C -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x1C 0x8000381C -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x8000381C | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x8000381C | |
| 03:39:07+827 [PCI ] BAR3 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x20 0x80003820 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x20 0x80003820 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003820 | |
| 03:39:07+827 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x20 0x80003820 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x20 0x80003820 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003820 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003820 | |
| 03:39:07+827 [PCI ] BAR4 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x24 0x80003824 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x24 0x80003824 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0xFF addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data1: 0xFF addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003824 | |
| 03:39:07+827 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x24 0x80003824 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x24 0x80003824 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003824 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003824 | |
| 03:39:07+827 [PCI ] BAR5 exists=n changed to 0x0 dev=0x07 (acpi) | |
| 03:39:07+827 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0x00000000 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0x00000000 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data1: 0xF8 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data2: 0xFF addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data3: 0xFF addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI write dev=0x07 (acpi) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0xFFFFF800 | |
| 03:39:07+827 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0xFFFFF800 | |
| 03:39:07+827 [PCI ] PCI data0: 0x00 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data1: 0x00 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data2: 0x00 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI data3: 0x00 addr=0x80003830 | |
| 03:39:07+827 [PCI ] PCI write dev=0x07 (acpi) addr=0x0030 value=0x00000000 | |
| 03:39:07+828 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1130 (detail=0x07fb1160) | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x10 0x80009010 -> 0xE0000008 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x10 0x80009010 -> 0xE0000008 | |
| 03:39:07+828 [PCI ] PCI data0: 0xFF addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data1: 0xFF addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data2: 0xFF addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data3: 0xFF addr=0x80009010 | |
| 03:39:07+828 [PCI ] BAR0 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x10 0x80009010 -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x10 0x80009010 -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0x08 addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data1: 0x00 addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data2: 0x00 addr=0x80009010 | |
| 03:39:07+828 [PCI ] PCI data3: 0xE0 addr=0x80009010 | |
| 03:39:07+828 [PCI ] BAR0 exists=n changed to 0xE0000008 dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x14 0x80009014 -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x14 0x80009014 -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0xFF addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data1: 0xFF addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data2: 0xFF addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data3: 0xFF addr=0x80009014 | |
| 03:39:07+828 [PCI ] BAR1 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x14 0x80009014 -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x14 0x80009014 -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0x00 addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data1: 0x00 addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data2: 0x00 addr=0x80009014 | |
| 03:39:07+828 [PCI ] PCI data3: 0x00 addr=0x80009014 | |
| 03:39:07+828 [PCI ] BAR1 exists=n changed to 0x0 dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x18 0x80009018 -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x18 0x80009018 -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0xFF addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data1: 0xFF addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data2: 0xFF addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data3: 0xFF addr=0x80009018 | |
| 03:39:07+828 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x18 0x80009018 -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x18 0x80009018 -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0x00 addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data1: 0x00 addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data2: 0x00 addr=0x80009018 | |
| 03:39:07+828 [PCI ] PCI data3: 0x00 addr=0x80009018 | |
| 03:39:07+828 [PCI ] BAR2 exists=n changed to 0x0 dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x1C 0x8000901C -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x1C 0x8000901C -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0xFF addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data1: 0xFF addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data2: 0xFF addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data3: 0xFF addr=0x8000901C | |
| 03:39:07+828 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x1C 0x8000901C -> 0x00000000 | |
| 03:39:07+828 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x1C 0x8000901C -> 0x00000000 | |
| 03:39:07+828 [PCI ] PCI data0: 0x00 addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data1: 0x00 addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data2: 0x00 addr=0x8000901C | |
| 03:39:07+828 [PCI ] PCI data3: 0x00 addr=0x8000901C | |
| 03:39:07+828 [PCI ] BAR3 exists=n changed to 0x0 dev=0x12 (vga) | |
| 03:39:07+828 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x20 0x80009020 -> 0x00000000 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x20 0x80009020 -> 0x00000000 | |
| 03:39:07+829 [PCI ] PCI data0: 0xFF addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data1: 0xFF addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data2: 0xFF addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data3: 0xFF addr=0x80009020 | |
| 03:39:07+829 [PCI ] BAR4 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+829 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x20 0x80009020 -> 0x00000000 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x20 0x80009020 -> 0x00000000 | |
| 03:39:07+829 [PCI ] PCI data0: 0x00 addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data1: 0x00 addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data2: 0x00 addr=0x80009020 | |
| 03:39:07+829 [PCI ] PCI data3: 0x00 addr=0x80009020 | |
| 03:39:07+829 [PCI ] BAR4 exists=n changed to 0x0 dev=0x12 (vga) | |
| 03:39:07+829 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x24 0x80009024 -> 0x00000000 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x24 0x80009024 -> 0x00000000 | |
| 03:39:07+829 [PCI ] PCI data0: 0xFF addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data1: 0xFF addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data2: 0xFF addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data3: 0xFF addr=0x80009024 | |
| 03:39:07+829 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x12 (vga) | |
| 03:39:07+829 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x24 0x80009024 -> 0x00000000 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x24 0x80009024 -> 0x00000000 | |
| 03:39:07+829 [PCI ] PCI data0: 0x00 addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data1: 0x00 addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data2: 0x00 addr=0x80009024 | |
| 03:39:07+829 [PCI ] PCI data3: 0x00 addr=0x80009024 | |
| 03:39:07+829 [PCI ] BAR5 exists=n changed to 0x0 dev=0x12 (vga) | |
| 03:39:07+829 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0x00000000 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0x00000000 | |
| 03:39:07+829 [PCI ] PCI data0: 0x00 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data1: 0xF8 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data2: 0xFF addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data3: 0xFF addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI write dev=0x12 (vga) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0xFFFFF800 | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0xFFFFF800 | |
| 03:39:07+829 [PCI ] PCI data0: 0x00 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data1: 0x00 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data2: 0x00 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI data3: 0x00 addr=0x80009030 | |
| 03:39:07+829 [PCI ] PCI write dev=0x12 (vga) addr=0x0030 value=0x00000000 | |
| 03:39:07+829 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb10d0 (detail=0x07fb1100) | |
| 03:39:07+829 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:07+830 [PCI ] PCI data0: 0xFF addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data1: 0xFF addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data2: 0xFF addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data3: 0xFF addr=0x8000F010 | |
| 03:39:07+830 [PCI ] BAR0 exists=y changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+830 [PCI ] io bar changed from 0x000001F0 to 0x0000FFF8 size=8 | |
| 03:39:07+830 [ ] from=0x1F0 to=0xFFF8 count=8 | |
| 03:39:07+830 [PCI ] BAR effective value: 0xFFFFFFF9 | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0xFFFFFFF9 | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0xFFFFFFF9 | |
| 03:39:07+830 [PCI ] PCI data0: 0xF1 addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data1: 0x01 addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data2: 0x00 addr=0x8000F010 | |
| 03:39:07+830 [PCI ] PCI data3: 0x00 addr=0x8000F010 | |
| 03:39:07+830 [PCI ] BAR0 exists=y changed to 0x1F1 dev=0x1E (ide0) | |
| 03:39:07+830 [PCI ] io bar changed from 0x0000FFF8 to 0x000001F0 size=8 | |
| 03:39:07+830 [ ] from=0xFFF8 to=0x1F0 count=8 | |
| 03:39:07+830 [PCI ] BAR effective value: 0x1F1 | |
| 03:39:07+830 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1070 (detail=0x07fb10a0) | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:07+830 [PCI ] PCI data0: 0xFF addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data1: 0xFF addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data2: 0xFF addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data3: 0xFF addr=0x8000F014 | |
| 03:39:07+830 [PCI ] BAR1 exists=y changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+830 [PCI ] io bar changed from 0x000003F4 to 0x0000FFFC size=4 | |
| 03:39:07+830 [ ] from=0x3F4 to=0xFFFC count=4 | |
| 03:39:07+830 [PCI ] BAR effective value: 0xFFFFFFFD | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0xFFFFFFFD | |
| 03:39:07+830 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0xFFFFFFFD | |
| 03:39:07+830 [PCI ] PCI data0: 0xF5 addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data1: 0x03 addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data2: 0x00 addr=0x8000F014 | |
| 03:39:07+830 [PCI ] PCI data3: 0x00 addr=0x8000F014 | |
| 03:39:07+830 [PCI ] BAR1 exists=y changed to 0x3F5 dev=0x1E (ide0) | |
| 03:39:07+830 [PCI ] io bar changed from 0x0000FFFC to 0x000003F4 size=4 | |
| 03:39:07+830 [ ] from=0xFFFC to=0x3F4 count=4 | |
| 03:39:07+830 [PCI ] BAR effective value: 0x3F5 | |
| 03:39:07+831 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb1010 (detail=0x07fb1040) | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:07+831 [PCI ] PCI data0: 0xFF addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data1: 0xFF addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data2: 0xFF addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data3: 0xFF addr=0x8000F018 | |
| 03:39:07+831 [PCI ] BAR2 exists=n changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:07+831 [PCI ] PCI data0: 0x00 addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data1: 0x00 addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data2: 0x00 addr=0x8000F018 | |
| 03:39:07+831 [PCI ] PCI data3: 0x00 addr=0x8000F018 | |
| 03:39:07+831 [PCI ] BAR2 exists=n changed to 0x0 dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:07+831 [PCI ] PCI data0: 0xFF addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data1: 0xFF addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data2: 0xFF addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data3: 0xFF addr=0x8000F01C | |
| 03:39:07+831 [PCI ] BAR3 exists=n changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:07+831 [PCI ] PCI data0: 0x00 addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data1: 0x00 addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data2: 0x00 addr=0x8000F01C | |
| 03:39:07+831 [PCI ] PCI data3: 0x00 addr=0x8000F01C | |
| 03:39:07+831 [PCI ] BAR3 exists=n changed to 0x0 dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000B401 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000B401 | |
| 03:39:07+831 [PCI ] PCI data0: 0xFF addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data1: 0xFF addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data2: 0xFF addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data3: 0xFF addr=0x8000F020 | |
| 03:39:07+831 [PCI ] BAR4 exists=y changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] io bar changed from 0x0000B400 to 0x0000FFF0 size=16 | |
| 03:39:07+831 [ ] from=0xB400 to=0xFFF0 count=16 | |
| 03:39:07+831 [PCI ] BAR effective value: 0xFFFFFFF1 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0xFFFFFFF1 | |
| 03:39:07+831 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0xFFFFFFF1 | |
| 03:39:07+831 [PCI ] PCI data0: 0x01 addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data1: 0xB4 addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data2: 0x00 addr=0x8000F020 | |
| 03:39:07+831 [PCI ] PCI data3: 0x00 addr=0x8000F020 | |
| 03:39:07+831 [PCI ] BAR4 exists=y changed to 0xB401 dev=0x1E (ide0) | |
| 03:39:07+831 [PCI ] io bar changed from 0x0000FFF0 to 0x0000B400 size=16 | |
| 03:39:07+831 [ ] from=0xFFF0 to=0xB400 count=16 | |
| 03:39:07+831 [PCI ] BAR effective value: 0xB401 | |
| 03:39:07+832 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb0fb0 (detail=0x07fb0fe0) | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:07+832 [PCI ] PCI data0: 0xFF addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data1: 0xFF addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data2: 0xFF addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data3: 0xFF addr=0x8000F024 | |
| 03:39:07+832 [PCI ] BAR5 exists=n changed to 0xFFFFFFFF dev=0x1E (ide0) | |
| 03:39:07+832 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:07+832 [PCI ] PCI data0: 0x00 addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data1: 0x00 addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data2: 0x00 addr=0x8000F024 | |
| 03:39:07+832 [PCI ] PCI data3: 0x00 addr=0x8000F024 | |
| 03:39:07+832 [PCI ] BAR5 exists=n changed to 0x0 dev=0x1E (ide0) | |
| 03:39:07+832 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0x00000000 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0x00000000 | |
| 03:39:07+832 [PCI ] PCI data0: 0x00 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data1: 0xF8 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data2: 0xFF addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data3: 0xFF addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI write dev=0x1E (ide0) addr=0x0030 value=0xFFFFF800 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0xFFFFF800 | |
| 03:39:07+832 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0xFFFFF800 | |
| 03:39:07+832 [PCI ] PCI data0: 0x00 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data1: 0x00 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data2: 0x00 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI data3: 0x00 addr=0x8000F030 | |
| 03:39:07+832 [PCI ] PCI write dev=0x1E (ide0) addr=0x0030 value=0x00000000 | |
| 03:39:07+832 [BIOS] _malloc zone=0x07fbfeb3 size=40 align=10 ret=0x07fb0f50 (detail=0x07fb0f80) | |
| 03:39:07+832 [BIOS] === PCI new allocation pass #2 === | |
| 03:39:07+832 [BIOS] PCI: IO: c000 - c13b | |
| 03:39:07+833 [BIOS] PCI: 32: 0000000080000000 - 00000000fec00000 | |
| 03:39:07+834 [BIOS] PCI: map device bdf=00:06.0 bar 0, addr 0000c000, size 00000100 [io] | |
| 03:39:07+834 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0x0000A801 | |
| 03:39:07+834 [PCI ] PCI data0: 0x00 addr=0x80003010 | |
| 03:39:07+834 [PCI ] PCI data1: 0xC0 addr=0x80003010 | |
| 03:39:07+834 [PCI ] PCI data2: 0x00 addr=0x80003010 | |
| 03:39:07+834 [PCI ] PCI data3: 0x00 addr=0x80003010 | |
| 03:39:07+834 [PCI ] BAR0 exists=y changed to 0xC000 dev=0x06 (virtio) | |
| 03:39:07+834 [PCI ] io bar changed from 0x0000A800 to 0x0000C000 size=256 | |
| 03:39:07+834 [ ] from=0xA800 to=0xC000 count=256 | |
| 03:39:07+834 [PCI ] BAR effective value: 0xC001 | |
| 03:39:07+834 [BIOS] _free 0x07fb11f0 (detail=0x07fb1220) | |
| 03:39:07+834 [BIOS] PCI: map device bdf=00:05.0 bar 0, addr 0000c100, size 00000020 [io] | |
| 03:39:07+834 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0x00000301 | |
| 03:39:07+834 [PCI ] PCI data0: 0x00 addr=0x80002810 | |
| 03:39:07+834 [PCI ] PCI data1: 0xC1 addr=0x80002810 | |
| 03:39:07+834 [PCI ] PCI data2: 0x00 addr=0x80002810 | |
| 03:39:07+834 [PCI ] PCI data3: 0x00 addr=0x80002810 | |
| 03:39:07+834 [PCI ] BAR0 exists=y changed to 0xC100 dev=0x05 (ne2k) | |
| 03:39:07+834 [PCI ] io bar changed from 0x00000300 to 0x0000C100 size=32 | |
| 03:39:07+834 [ ] from=0x300 to=0xC100 count=32 | |
| 03:39:07+834 [PCI ] BAR effective value: 0xC101 | |
| 03:39:07+834 [BIOS] _free 0x07fb12b0 (detail=0x07fb12e0) | |
| 03:39:07+834 [BIOS] PCI: map device bdf=00:1e.0 bar 4, addr 0000c120, size 00000010 [io] | |
| 03:39:07+834 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000B401 | |
| 03:39:07+834 [PCI ] PCI data0: 0x20 addr=0x8000F020 | |
| 03:39:07+834 [PCI ] PCI data1: 0xC1 addr=0x8000F020 | |
| 03:39:07+834 [PCI ] PCI data2: 0x00 addr=0x8000F020 | |
| 03:39:07+834 [PCI ] PCI data3: 0x00 addr=0x8000F020 | |
| 03:39:07+834 [PCI ] BAR4 exists=y changed to 0xC120 dev=0x1E (ide0) | |
| 03:39:07+834 [PCI ] io bar changed from 0x0000B400 to 0x0000C120 size=16 | |
| 03:39:07+834 [ ] from=0xB400 to=0xC120 count=16 | |
| 03:39:07+834 [PCI ] BAR effective value: 0xC121 | |
| 03:39:07+834 [BIOS] _free 0x07fb0fb0 (detail=0x07fb0fe0) | |
| 03:39:07+835 [BIOS] PCI: map device bdf=00:1e.0 bar 0, addr 0000c130, size 00000008 [io] | |
| 03:39:07+835 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:07+835 [PCI ] PCI data0: 0x30 addr=0x8000F010 | |
| 03:39:07+835 [PCI ] PCI data1: 0xC1 addr=0x8000F010 | |
| 03:39:07+835 [PCI ] PCI data2: 0x00 addr=0x8000F010 | |
| 03:39:07+835 [PCI ] PCI data3: 0x00 addr=0x8000F010 | |
| 03:39:07+835 [PCI ] BAR0 exists=y changed to 0xC130 dev=0x1E (ide0) | |
| 03:39:07+835 [PCI ] io bar changed from 0x000001F0 to 0x0000C130 size=8 | |
| 03:39:07+835 [ ] from=0x1F0 to=0xC130 count=8 | |
| 03:39:07+835 [PCI ] BAR effective value: 0xC131 | |
| 03:39:07+835 [BIOS] _free 0x07fb1070 (detail=0x07fb10a0) | |
| 03:39:07+837 [BIOS] PCI: map device bdf=00:1e.0 bar 1, addr 0000c138, size 00000004 [io] | |
| 03:39:07+837 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:07+837 [PCI ] PCI data0: 0x38 addr=0x8000F014 | |
| 03:39:07+837 [PCI ] PCI data1: 0xC1 addr=0x8000F014 | |
| 03:39:07+837 [PCI ] PCI data2: 0x00 addr=0x8000F014 | |
| 03:39:07+837 [PCI ] PCI data3: 0x00 addr=0x8000F014 | |
| 03:39:07+837 [PCI ] BAR1 exists=y changed to 0xC138 dev=0x1E (ide0) | |
| 03:39:07+837 [PCI ] io bar changed from 0x000003F4 to 0x0000C138 size=4 | |
| 03:39:07+837 [ ] from=0x3F4 to=0xC138 count=4 | |
| 03:39:07+837 [PCI ] BAR effective value: 0xC139 | |
| 03:39:07+837 [BIOS] _free 0x07fb1010 (detail=0x07fb1040) | |
| 03:39:07+837 [BIOS] PCI: map device bdf=00:00.0 bar 6, addr febf9000, size 00001000 [mem] | |
| 03:39:07+837 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0x00000000 | |
| 03:39:07+837 [PCI ] PCI data0: 0x00 addr=0x80000030 | |
| 03:39:07+837 [PCI ] PCI data1: 0x90 addr=0x80000030 | |
| 03:39:07+837 [PCI ] PCI data2: 0xBF addr=0x80000030 | |
| 03:39:07+837 [PCI ] PCI data3: 0xFE addr=0x80000030 | |
| 03:39:07+837 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x0030 value=0xFEBF9000 | |
| 03:39:07+839 [BIOS] _free 0x07fb1370 (detail=0x07fb13a0) | |
| 03:39:07+839 [BIOS] PCI: map device bdf=00:01.0 bar 6, addr febfa000, size 00001000 [mem] | |
| 03:39:07+839 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0x00000000 | |
| 03:39:07+839 [PCI ] PCI data0: 0x00 addr=0x80000830 | |
| 03:39:07+839 [PCI ] PCI data1: 0xA0 addr=0x80000830 | |
| 03:39:07+839 [PCI ] PCI data2: 0xBF addr=0x80000830 | |
| 03:39:07+839 [PCI ] PCI data3: 0xFE addr=0x80000830 | |
| 03:39:07+839 [PCI ] PCI write dev=0x01 (82371SB PIIX3 ISA) addr=0x0030 value=0xFEBFA000 | |
| 03:39:07+839 [BIOS] _free 0x07fb1310 (detail=0x07fb1340) | |
| 03:39:07+840 [BIOS] PCI: map device bdf=00:05.0 bar 6, addr febfb000, size 00001000 [mem] | |
| 03:39:07+840 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFEB80000 | |
| 03:39:07+840 [PCI ] PCI data0: 0x00 addr=0x80002830 | |
| 03:39:07+840 [PCI ] PCI data1: 0xB0 addr=0x80002830 | |
| 03:39:07+840 [PCI ] PCI data2: 0xBF addr=0x80002830 | |
| 03:39:07+840 [PCI ] PCI data3: 0xFE addr=0x80002830 | |
| 03:39:07+840 [PCI ] PCI write dev=0x05 (ne2k) addr=0x0030 value=0xFEBFB000 | |
| 03:39:07+840 [BIOS] _free 0x07fb1250 (detail=0x07fb1280) | |
| 03:39:07+840 [BIOS] PCI: map device bdf=00:06.0 bar 6, addr febfc000, size 00001000 [mem] | |
| 03:39:07+840 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0x00000000 | |
| 03:39:07+840 [PCI ] PCI data0: 0x00 addr=0x80003030 | |
| 03:39:07+840 [PCI ] PCI data1: 0xC0 addr=0x80003030 | |
| 03:39:07+840 [PCI ] PCI data2: 0xBF addr=0x80003030 | |
| 03:39:07+840 [PCI ] PCI data3: 0xFE addr=0x80003030 | |
| 03:39:07+840 [PCI ] PCI write dev=0x06 (virtio) addr=0x0030 value=0xFEBFC000 | |
| 03:39:07+840 [BIOS] _free 0x07fb1190 (detail=0x07fb11c0) | |
| 03:39:07+840 [BIOS] PCI: map device bdf=00:07.0 bar 6, addr febfd000, size 00001000 [mem] | |
| 03:39:07+840 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0x00000000 | |
| 03:39:07+840 [PCI ] PCI data0: 0x00 addr=0x80003830 | |
| 03:39:07+840 [PCI ] PCI data1: 0xD0 addr=0x80003830 | |
| 03:39:07+840 [PCI ] PCI data2: 0xBF addr=0x80003830 | |
| 03:39:07+840 [PCI ] PCI data3: 0xFE addr=0x80003830 | |
| 03:39:07+840 [PCI ] PCI write dev=0x07 (acpi) addr=0x0030 value=0xFEBFD000 | |
| 03:39:07+840 [BIOS] _free 0x07fb1130 (detail=0x07fb1160) | |
| 03:39:07+841 [BIOS] PCI: map device bdf=00:12.0 bar 6, addr febfe000, size 00001000 [mem] | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0x00000000 | |
| 03:39:07+841 [PCI ] PCI data0: 0x00 addr=0x80009030 | |
| 03:39:07+841 [PCI ] PCI data1: 0xE0 addr=0x80009030 | |
| 03:39:07+841 [PCI ] PCI data2: 0xBF addr=0x80009030 | |
| 03:39:07+841 [PCI ] PCI data3: 0xFE addr=0x80009030 | |
| 03:39:07+841 [PCI ] PCI write dev=0x12 (vga) addr=0x0030 value=0xFEBFE000 | |
| 03:39:07+841 [BIOS] _free 0x07fb10d0 (detail=0x07fb1100) | |
| 03:39:07+841 [BIOS] PCI: map device bdf=00:1e.0 bar 6, addr febff000, size 00001000 [mem] | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0x00000000 | |
| 03:39:07+841 [PCI ] PCI data0: 0x00 addr=0x8000F030 | |
| 03:39:07+841 [PCI ] PCI data1: 0xF0 addr=0x8000F030 | |
| 03:39:07+841 [PCI ] PCI data2: 0xBF addr=0x8000F030 | |
| 03:39:07+841 [PCI ] PCI data3: 0xFE addr=0x8000F030 | |
| 03:39:07+841 [PCI ] PCI write dev=0x1E (ide0) addr=0x0030 value=0xFEBFF000 | |
| 03:39:07+841 [BIOS] _free 0x07fb0f50 (detail=0x07fb0f80) | |
| 03:39:07+841 [BIOS] PCI: init bdf=00:00.0 id=8086:1237 | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:39:07+841 [PCI ] PCI data0: 0x03 addr=0x80000004 | |
| 03:39:07+841 [PCI ] PCI data1: 0x01 addr=0x80000004 | |
| 03:39:07+841 [BIOS] PCI: init bdf=00:01.0 id=8086:7000 | |
| 03:39:07+841 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x3C 0x8000083C -> 0x00000000 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x60 0x80000860 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data0: 0x0A addr=0x80000860 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x60 0x80000860 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data1: 0x0A addr=0x80000860 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x60 0x80000860 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data2: 0x0B addr=0x80000860 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x60 0x80000860 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data3: 0x0B addr=0x80000860 | |
| 03:39:07+842 [PCI ] PCI write dev=0x01 (82371SB PIIX3 ISA) addr=0x0060 value=0x0B0B0A0A | |
| 03:39:07+842 [BIOS] PIIX3/PIIX4 init: elcr=00 0c | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:39:07+842 [PCI ] PCI data0: 0x07 addr=0x80000804 | |
| 03:39:07+842 [PCI ] PCI data1: 0x01 addr=0x80000804 | |
| 03:39:07+842 [BIOS] PCI: init bdf=00:05.0 id=10ec:8029 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x3C 0x8000283C -> 0x0000010B | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x3C 0x8000283C -> 0x0000010B | |
| 03:39:07+842 [PCI ] PCI data0: 0x0A addr=0x8000283C | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x04 0x80002804 -> 0x00000103 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x04 0x80002804 -> 0x00000103 | |
| 03:39:07+842 [PCI ] PCI data0: 0x03 addr=0x80002804 | |
| 03:39:07+842 [PCI ] PCI data1: 0x01 addr=0x80002804 | |
| 03:39:07+842 [BIOS] PCI: init bdf=00:06.0 id=1af4:1009 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x3C 0x8000303C -> 0x0000010C | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x3C 0x8000303C -> 0x0000010C | |
| 03:39:07+842 [PCI ] PCI data0: 0x0A addr=0x8000303C | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x04 0x80003004 -> 0x00100507 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x04 0x80003004 -> 0x00100507 | |
| 03:39:07+842 [PCI ] PCI data0: 0x07 addr=0x80003004 | |
| 03:39:07+842 [PCI ] PCI data1: 0x05 addr=0x80003004 | |
| 03:39:07+842 [BIOS] PCI: init bdf=00:07.0 id=8086:7113 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:39:07+842 [PCI ] PCI data0: 0x0B addr=0x8000383C | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:39:07+842 [PCI ] PCI data0: 0x09 addr=0x8000383C | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x40 0x80003840 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data0: 0x01 addr=0x80003840 | |
| 03:39:07+842 [PCI ] PCI data1: 0xB0 addr=0x80003840 | |
| 03:39:07+842 [PCI ] PCI data2: 0x00 addr=0x80003840 | |
| 03:39:07+842 [PCI ] PCI data3: 0x00 addr=0x80003840 | |
| 03:39:07+842 [PCI ] PCI write dev=0x07 (acpi) addr=0x0040 value=0x0000B001 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x80 0x80003880 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data0: 0x01 addr=0x80003880 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x90 0x80003890 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data0: 0x01 addr=0x80003890 | |
| 03:39:07+842 [PCI ] PCI data1: 0xB1 addr=0x80003890 | |
| 03:39:07+842 [PCI ] PCI data2: 0x00 addr=0x80003890 | |
| 03:39:07+842 [PCI ] PCI data3: 0x00 addr=0x80003890 | |
| 03:39:07+842 [PCI ] PCI write dev=0x07 (acpi) addr=0x0090 value=0x0000B101 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0xD0 0x800038D0 -> 0x00000000 (undef) | |
| 03:39:07+842 [PCI ] PCI data2: 0x09 addr=0x800038D0 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:39:07+842 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:39:07+842 [PCI ] PCI data0: 0x07 addr=0x80003804 | |
| 03:39:07+842 [PCI ] PCI data1: 0x01 addr=0x80003804 | |
| 03:39:07+843 [BIOS] PCI: init bdf=00:12.0 id=10de:0a20 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x3C 0x8000903C -> 0x0000010A | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x3C 0x8000903C -> 0x0000010A | |
| 03:39:07+843 [PCI ] PCI data0: 0x0A addr=0x8000903C | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:39:07+843 [PCI ] PCI data0: 0x07 addr=0x80009004 | |
| 03:39:07+843 [PCI ] PCI data1: 0x01 addr=0x80009004 | |
| 03:39:07+843 [BIOS] PCI: init bdf=00:1e.0 id=8086:3a20 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:07+843 [PCI ] PCI data0: 0x0A addr=0x8000F03C | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x0000C131 | |
| 03:39:07+843 [PCI ] PCI data0: 0xF0 addr=0x8000F010 | |
| 03:39:07+843 [PCI ] PCI data1: 0x01 addr=0x8000F010 | |
| 03:39:07+843 [PCI ] PCI data2: 0x00 addr=0x8000F010 | |
| 03:39:07+843 [PCI ] PCI data3: 0x00 addr=0x8000F010 | |
| 03:39:07+843 [PCI ] BAR0 exists=y changed to 0x1F0 dev=0x1E (ide0) | |
| 03:39:07+843 [PCI ] io bar changed from 0x0000C130 to 0x000001F0 size=8 | |
| 03:39:07+843 [ ] from=0xC130 to=0x1F0 count=8 | |
| 03:39:07+843 [PCI ] BAR effective value: 0x1F1 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x0000C139 | |
| 03:39:07+843 [PCI ] PCI data0: 0xF4 addr=0x8000F014 | |
| 03:39:07+843 [PCI ] PCI data1: 0x03 addr=0x8000F014 | |
| 03:39:07+843 [PCI ] PCI data2: 0x00 addr=0x8000F014 | |
| 03:39:07+843 [PCI ] PCI data3: 0x00 addr=0x8000F014 | |
| 03:39:07+843 [PCI ] BAR1 exists=y changed to 0x3F4 dev=0x1E (ide0) | |
| 03:39:07+843 [PCI ] io bar changed from 0x0000C138 to 0x000003F4 size=4 | |
| 03:39:07+843 [ ] from=0xC138 to=0x3F4 count=4 | |
| 03:39:07+843 [PCI ] BAR effective value: 0x3F5 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:07+843 [PCI ] PCI data0: 0x70 addr=0x8000F018 | |
| 03:39:07+843 [PCI ] PCI data1: 0x01 addr=0x8000F018 | |
| 03:39:07+843 [PCI ] PCI data2: 0x00 addr=0x8000F018 | |
| 03:39:07+843 [PCI ] PCI data3: 0x00 addr=0x8000F018 | |
| 03:39:07+843 [PCI ] BAR2 exists=n changed to 0x170 dev=0x1E (ide0) | |
| 03:39:07+843 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:07+843 [PCI ] PCI data0: 0x74 addr=0x8000F01C | |
| 03:39:07+843 [PCI ] PCI data1: 0x03 addr=0x8000F01C | |
| 03:39:07+843 [PCI ] PCI data2: 0x00 addr=0x8000F01C | |
| 03:39:07+843 [PCI ] PCI data3: 0x00 addr=0x8000F01C | |
| 03:39:07+843 [PCI ] BAR3 exists=n changed to 0x374 dev=0x1E (ide0) | |
| 03:39:07+843 [PCI ] BAR effective value: 0x0 | |
| 03:39:07+843 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:07+844 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:07+844 [PCI ] PCI data0: 0x07 addr=0x8000F004 | |
| 03:39:07+844 [PCI ] PCI data1: 0x01 addr=0x8000F004 | |
| 03:39:07+844 [BIOS] _free 0x07fb13d0 (detail=0x07fb1400) | |
| 03:39:07+844 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:39:07+844 [BIOS] PCI: Using 00:12.0 for primary VGA | |
| 03:39:07+844 [APIC] APIC read 0xF0 | |
| 03:39:07+844 [APIC] APIC write32 0xF0 <- 0x00000100 | |
| 03:39:07+844 [APIC] APIC write32 0x350 <- 0x00008700 | |
| 03:39:07+844 [APIC] APIC write32 0x360 <- 0x00008400 | |
| 03:39:07+844 [APIC] APIC write icr0: 0x000C4500 vector=0x00 destination_mode=0 delivery_mode=5 destination_shorthand=all without self | |
| 03:39:07+844 [APIC] APIC write icr0: 0x000C4610 vector=0x10 destination_mode=0 delivery_mode=6 destination_shorthand=all without self | |
| 03:39:07+844 [RTC ] cmos read from index 0x5F | |
| 03:39:07+844 [BIOS] Found 1 cpu(s) max supported 1 cpu(s) | |
| 03:39:07+844 [BIOS] init PIR table | |
| 03:39:07+846 [BIOS] _malloc zone=0x07fbfebb size=128 align=10 ret=0x000f5230 (detail=0x07fb1400) | |
| 03:39:07+846 [BIOS] Copying PIR from 0x07fbfcef to 0x000f5230 | |
| 03:39:07+846 [BIOS] init MPTable | |
| 03:39:07+847 [BIOS] _malloc zone=0x07fbfeb3 size=32768 align=10 ret=0x07fa93d0 (detail=0x07fb13d0) | |
| 03:39:07+847 [APIC] APIC read version | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x3C 0x8000083C -> 0x00000000 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x3C 0x8000083C -> 0x00000000 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x3C 0x8000283C -> 0x0000010B | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x3C 0x8000283C -> 0x0000010B | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x3C 0x8000303C -> 0x0000010C | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x3C 0x8000303C -> 0x0000010C | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x3C 0x8000903C -> 0x0000010A | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x3C 0x8000903C -> 0x0000010A | |
| 03:39:07+847 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:07+848 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:07+848 [BIOS] _malloc zone=0x07fbfebb size=256 align=10 ret=0x000f5130 (detail=0x07fa93a0) | |
| 03:39:07+848 [BIOS] Copying MPTABLE from 0x00006eb4/7fa93d0 to 0x000f5130 | |
| 03:39:07+848 [BIOS] _free 0x07fa93d0 (detail=0x07fb13d0) | |
| 03:39:07+849 [BIOS] init SMBIOS tables | |
| 03:39:07+849 [BIOS] _malloc zone=0x07fbfeb3 size=32768 align=10 ret=0x07fa93d0 (detail=0x07fb13d0) | |
| 03:39:07+889 [BIOS] _malloc zone=0x07fbfebb size=263 align=10 ret=0x000f5020 (detail=0x07fa9370) | |
| 03:39:07+890 [BIOS] _malloc zone=0x07fbfebb size=31 align=10 ret=0x000f5000 (detail=0x07fa9340) | |
| 03:39:07+890 [BIOS] Copying SMBIOS entry point from 0x00006eb4 to 0x000f5000 | |
| 03:39:07+890 [BIOS] _free 0x07fa93d0 (detail=0x07fb13d0) | |
| 03:39:07+890 [BIOS] load ACPI tables | |
| 03:39:07+890 [BIOS] init ACPI tables | |
| 03:39:07+891 [BIOS] _malloc zone=0x07fbfebf size=116 align=10 ret=0x07ffff80 (detail=0x07fb13d0) | |
| 03:39:07+891 [BIOS] _malloc zone=0x07fbfebf size=64 align=40 ret=0x07ffff40 (detail=0x07fb13a0) | |
| 03:39:07+891 [BIOS] _malloc zone=0x07fbfebf size=2073 align=10 ret=0x07fff720 (detail=0x07fb1370) | |
| 03:39:07+891 [IO ] read32 port #0xAE0C | |
| 03:39:07+895 [BIOS] _malloc zone=0x07fbfebf size=230 align=10 ret=0x07fff630 (detail=0x07fb1340) | |
| 03:39:07+895 [IO ] Read from unmapped memory space, addr=0xFED00000 | |
| 03:39:07+895 [IO ] Read from unmapped memory space, addr=0xFED00004 | |
| 03:39:07+895 [BIOS] _malloc zone=0x07fbfebf size=4405 align=10 ret=0x07ffe4f0 (detail=0x07fb1310) | |
| 03:39:07+896 [BIOS] ACPI DSDT=0x07ffe4f0 | |
| 03:39:07+897 [BIOS] _malloc zone=0x07fbfebf size=48 align=10 ret=0x07ffe4c0 (detail=0x07fb12e0) | |
| 03:39:07+898 [BIOS] _malloc zone=0x07fbfebb size=20 align=10 ret=0x000f4fe0 (detail=0x07fb12b0) | |
| 03:39:07+898 [BIOS] Copying ACPI RSDP from 0x00006dc8 to 0x000f4fe0 | |
| 03:39:07+898 [BIOS] Scan for VGA option rom | |
| 03:39:07+898 [BIOS] Checking rom 0x000c0000 (sig aa55 size 77) | |
| 03:39:07+911 [BIOS] Running option rom at c000:0003 | |
| 03:39:07+915 [BIOS] Start SeaVGABIOS (version 1.9.0-20160212_231317-eevee) | |
| 03:39:07+918 [BIOS] VGABUILD: gcc: (GCC) 5.3.0 binutils: (GNU Binutils) 2.25.1 | |
| 03:39:07+918 [BIOS] enter vga_post: | |
| 03:39:07+922 [BIOS] a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000 | |
| 03:39:07+928 [BIOS] si=00000000 di=000057b0 bp=00000000 sp=00006e6e cs=f000 ip=cb01 f=0000 | |
| 03:39:07+928 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:07+929 [BIOS] VBE DISPI: lfb_addr=e0000000, size 8 MB | |
| 03:39:07+940 [BIOS] Removing mode 189 | |
| 03:39:07+940 [BIOS] Removing mode 18b | |
| 03:39:07+940 [BIOS] Removing mode 18c | |
| 03:39:07+955 [BIOS] Attempting to allocate VGA stack via pmm call to f000:cb6a | |
| 03:39:07+955 [IO ] read8 port #0x0070 (PORT_CMOS_INDEX) | |
| 03:39:07+955 [RTC ] cmos read from index 0x7F | |
| 03:39:07+955 [RTC ] cmos read from index 0xF | |
| 03:39:07+955 [BIOS] pmm call arg1=0 | |
| 03:39:07+956 [BIOS] pmm00: length=20 handle=ffffffff flags=9 | |
| 03:39:07+958 [BIOS] _malloc zone=0x07fbfec3 size=512 align=10 ret=0x000ee1f0 (detail=0x07fb1280) | |
| 03:39:07+958 [RTC ] cmos read from index 0x7F | |
| 03:39:07+959 [BIOS] VGA stack allocated at ee1f0 | |
| 03:39:07+981 [RTC ] cmos read from index 0xF | |
| 03:39:07+982 [RTC ] cmos read from index 0xF | |
| 03:39:07+982 [BIOS] Turning on vga text mode console | |
| 03:39:07+982 [BIOS] set VGA mode 3 | |
| 03:39:07+982 [IO ] write8 port #0x03C6 <- 0xFF | |
| 03:39:08+002 [RTC ] cmos read from index 0xF | |
| Previous message repeated 48 times | |
| 03:39:08+026 [BIOS] SeaBIOS (version 1.7.5.2-20150319_155624-eevee) | |
| 03:39:08+027 [RTC ] cmos read from index 0xF | |
| 03:39:08+027 [RTC ] cmos read from index 0xF | |
| 03:39:08+027 [BIOS] _malloc zone=0x07fbfeb3 size=4096 align=1000 ret=0x07fb0000 (detail=0x07fb1250) | |
| 03:39:08+028 [BIOS] /07fb0000\ Start thread | |
| 03:39:08+028 [BIOS] |07fb0000| init usb | |
| 03:39:08+028 [BIOS] \07fb0000/ End thread | |
| 03:39:08+028 [BIOS] _free 0x07fb0000 (detail=0x07fb1250) | |
| 03:39:08+028 [BIOS] All threads complete. | |
| 03:39:08+028 [BIOS] init ps2port | |
| 03:39:08+028 [BIOS] _malloc zone=0x07fbfeb3 size=4096 align=1000 ret=0x07fb0000 (detail=0x07fb1250) | |
| 03:39:08+028 [BIOS] /07fb0000\ Start thread | |
| 03:39:08+028 [BIOS] |07fb0000| i8042_flush | |
| 03:39:08+028 [BIOS] |07fb0000| i8042_command cmd=1aa | |
| 03:39:08+028 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_wait_read | |
| 03:39:08+029 [BIOS] |07fb0000| i8042 param=55 | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_command cmd=1ab | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_wait_read | |
| 03:39:08+029 [BIOS] |07fb0000| i8042 param=0 | |
| 03:39:08+029 [BIOS] |07fb0000| ps2_command aux=0 cmd=2ff | |
| 03:39:08+029 [BIOS] |07fb0000| i8042 ctr old=30 new=30 | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+029 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+030 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+030 [BIOS] init lpt | |
| 03:39:08+030 [IO ] read8 port #0x037A | |
| 03:39:08+030 [IO ] write8 port #0x037A <- 0xDF | |
| 03:39:08+030 [IO ] write8 port #0x0378 <- 0xAA (PORT_LPT1) | |
| 03:39:08+030 [IO ] read8 port #0x0378 (PORT_LPT1) | |
| 03:39:08+030 [IO ] read8 port #0x027A | |
| 03:39:08+030 [IO ] write8 port #0x027A <- 0xDF | |
| 03:39:08+030 [IO ] write8 port #0x0278 <- 0xAA (PORT_LPT2) | |
| 03:39:08+030 [IO ] read8 port #0x0278 (PORT_LPT2) | |
| 03:39:08+030 [BIOS] Found 0 lpt ports | |
| 03:39:08+030 [BIOS] init serial | |
| 03:39:08+030 [SERI] interrupt enable: 0x2 | |
| 03:39:08+030 [SERI] read interrupt identification: 0x1 | |
| 03:39:08+030 [IO ] write8 port #0x02F9 <- 0x02 | |
| 03:39:08+030 [IO ] read8 port #0x02F9 | |
| 03:39:08+030 [IO ] write8 port #0x03E9 <- 0x02 | |
| 03:39:08+030 [IO ] read8 port #0x03E9 | |
| 03:39:08+030 [IO ] write8 port #0x02E9 <- 0x02 | |
| 03:39:08+030 [IO ] read8 port #0x02E9 | |
| 03:39:08+030 [BIOS] Found 0 serial ports | |
| 03:39:08+030 [BIOS] init floppy drives | |
| 03:39:08+030 [RTC ] cmos read from index 0x10 | |
| 03:39:08+030 [BIOS] _malloc zone=0x07fbfebb size=36 align=10 ret=0x000f4fb0 (detail=0x07fb1220) | |
| 03:39:08+030 [BIOS] _malloc zone=0x07fbfeb3 size=80 align=10 ret=0x07fb11a0 (detail=0x07fb11f0) | |
| 03:39:08+031 [BIOS] Searching bootorder for: /pci@i0cf8/isa@1/fdc@03f0/floppy@0 | |
| 03:39:08+031 [BIOS] _malloc zone=0x07fbfeb3 size=24 align=10 ret=0x07fb1150 (detail=0x07fb1170) | |
| 03:39:08+031 [BIOS] Registering bootable: Floppy [drive A] (type:1 prio:102 data:f4fb0) | |
| 03:39:08+031 [BIOS] init hard drives | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000C121 | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:08+031 [PCI ] PCI data0: 0x05 addr=0x8000F004 | |
| 03:39:08+031 [PCI ] PCI data1: 0x00 addr=0x8000F004 | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:08+031 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:08+032 [BIOS] _malloc zone=0x07fbfebb size=16 align=10 ret=0x000f4fa0 (detail=0x07fb1120) | |
| 03:39:08+032 [BIOS] ATA controller 1 at 1f0/3f4/c120 (irq 14 dev f0) | |
| 03:39:08+032 [BIOS] _malloc zone=0x07fbfeb3 size=4096 align=1000 ret=0x07faf000 (detail=0x07fb10f0) | |
| 03:39:08+032 [BIOS] /07faf000\ Start thread | |
| 03:39:08+032 [BIOS] |07faf000| powerup iobase=1f0 st=50 | |
| 03:39:08+033 [BIOS] |07faf000| powerup iobase=1f0 st=50 | |
| 03:39:08+033 [BIOS] |07faf000| ata_detect ata0-0: sc=55 sn=aa dh=a0 | |
| 03:39:08+033 [BIOS] |07faf000| ata_reset drive=0x07fafdc0 | |
| 03:39:08+033 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+033 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+033 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+033 [BIOS] |07fb0000| ps2_sendbyte aux=0 cmd=ff | |
| 03:39:08+033 [BIOS] |07fb0000| i8042_kbd_write c=255 | |
| 03:39:08+033 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+033 [BIOS] |07fb0000| ps2 read fa | |
| 03:39:08+033 [BIOS] |07fb0000| ps2 read aa | |
| 03:39:08+034 [BIOS] |07fb0000| ps2 read 0 | |
| 03:39:08+034 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+034 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+034 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+034 [BIOS] |07fb0000| ps2_command aux=0 cmd=f5 | |
| 03:39:08+034 [BIOS] |07fb0000| i8042 ctr old=30 new=30 | |
| 03:39:08+035 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+035 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+035 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+035 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:08+035 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:08+035 [BIOS] _malloc zone=0x07fbfebb size=16 align=10 ret=0x000f4f90 (detail=0x07fb10c0) | |
| 03:39:08+035 [BIOS] ATA controller 2 at 0/0/c128 (irq 14 dev f0) | |
| 03:39:08+035 [BIOS] _malloc zone=0x07fbfeb3 size=4096 align=1000 ret=0x07fae000 (detail=0x07fb1090) | |
| 03:39:08+035 [BIOS] /07fae000\ Start thread | |
| 03:39:08+035 [IO ] read8 port #0x0007 | |
| 03:39:08+035 [BIOS] |07fae000| powerup IDE floating | |
| 03:39:08+035 [IO ] write8 port #0x0006 <- 0xA0 | |
| 03:39:08+035 [IO ] read8 port #0x0007 | |
| 03:39:08+035 [BIOS] |07fae000| powerup IDE floating | |
| 03:39:08+035 [IO ] write8 port #0x0006 <- 0xA0 | |
| 03:39:08+035 [IO ] read8 port #0x0006 | |
| 03:39:08+035 [IO ] write8 port #0x0002 <- 0x55 | |
| 03:39:08+035 [IO ] write8 port #0x0003 <- 0xAA | |
| 03:39:08+035 [IO ] read8 port #0x0002 | |
| 03:39:08+035 [IO ] read8 port #0x0003 | |
| 03:39:08+036 [BIOS] |07fae000| ata_detect ata1-0: sc=ff sn=ff dh=ff | |
| 03:39:08+036 [IO ] read8 port #0x0007 | |
| 03:39:08+036 [BIOS] |07fae000| powerup IDE floating | |
| 03:39:08+036 [IO ] write8 port #0x0006 <- 0xB0 | |
| 03:39:08+036 [IO ] read8 port #0x0007 | |
| 03:39:08+036 [BIOS] |07fae000| powerup IDE floating | |
| 03:39:08+036 [IO ] write8 port #0x0006 <- 0xB0 | |
| 03:39:08+036 [IO ] read8 port #0x0006 | |
| 03:39:08+036 [IO ] write8 port #0x0002 <- 0x55 | |
| 03:39:08+036 [IO ] write8 port #0x0003 <- 0xAA | |
| 03:39:08+036 [IO ] read8 port #0x0002 | |
| 03:39:08+036 [IO ] read8 port #0x0003 | |
| 03:39:08+037 [BIOS] |07fae000| ata_detect ata1-1: sc=ff sn=ff dh=ff | |
| 03:39:08+037 [BIOS] \07fae000/ End thread | |
| 03:39:08+037 [BIOS] _free 0x07fae000 (detail=0x07fb1090) | |
| 03:39:08+037 [BIOS] |07faf000| ata_reset exit status=51 | |
| 03:39:08+038 [BIOS] |07faf000| send_cmd : DRQ not set (status 50) | |
| 03:39:08+039 [BIOS] |07faf000| _malloc zone=0x07fbfebb size=44 align=10 ret=0x000f4f60 (detail=0x07fb1090) | |
| 03:39:08+042 [BIOS] |07faf000| _malloc zone=0x07fbfeb3 size=80 align=10 ret=0x07fb1010 (detail=0x07fb1060) | |
| 03:39:08+042 [BIOS] |07faf000| ata0-0: v86 HD ATA-6 Hard-Disk (30720 MiBytes) | |
| 03:39:08+044 [BIOS] |07faf000| Searching bootorder for: /pci@i0cf8/*@1e/drive@0/disk@0 | |
| 03:39:08+044 [BIOS] |07faf000| _malloc zone=0x07fbfeb3 size=24 align=10 ret=0x07faefb0 (detail=0x07faefd0) | |
| 03:39:08+044 [BIOS] |07faf000| Registering bootable: ata0-0: v86 HD ATA-6 Hard-Disk (30720 MiBytes) (type:2 prio:103 data:f4f60) | |
| 03:39:08+044 [BIOS] |07faf000| ata_detect resetresult=6001 | |
| 03:39:08+044 [BIOS] |07faf000| powerup iobase=1f0 st=50 | |
| 03:39:08+044 [BIOS] |07faf000| powerup iobase=1f0 st=0 | |
| 03:39:08+044 [BIOS] |07faf000| ata_detect ata0-1: sc=55 sn=aa dh=b0 | |
| 03:39:08+045 [BIOS] |07faf000| send_cmd : DRQ not set (status 00) | |
| 03:39:08+045 [BIOS] \07faf000/ End thread | |
| 03:39:08+045 [BIOS] _free 0x07faf000 (detail=0x07fb10f0) | |
| 03:39:08+045 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+045 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+046 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+046 [BIOS] |07fb0000| ps2_sendbyte aux=0 cmd=f5 | |
| 03:39:08+046 [BIOS] |07fb0000| i8042_kbd_write c=245 | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+047 [BIOS] |07fb0000| ps2 read fa | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+047 [BIOS] |07fb0000| ps2_command aux=0 cmd=10f0 | |
| 03:39:08+047 [BIOS] |07fb0000| i8042 ctr old=30 new=30 | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+047 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+047 [BIOS] init ahci | |
| 03:39:08+048 [BIOS] init virtio-blk | |
| 03:39:08+048 [BIOS] init virtio-scsi | |
| 03:39:08+048 [BIOS] init lsi53c895a | |
| 03:39:08+048 [BIOS] init esp | |
| 03:39:08+048 [BIOS] init megasas | |
| 03:39:08+048 [BIOS] init pvscsi | |
| 03:39:08+048 [RTC ] cmos read from index 0xF | |
| 03:39:08+048 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+048 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+048 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+048 [BIOS] |07fb0000| ps2_sendbyte aux=0 cmd=f0 | |
| 03:39:08+048 [BIOS] |07fb0000| i8042_kbd_write c=240 | |
| 03:39:08+048 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+048 [BIOS] |07fb0000| ps2 read fa | |
| 03:39:08+049 [BIOS] |07fb0000| ps2_sendbyte aux=0 cmd=2 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_kbd_write c=2 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+049 [BIOS] |07fb0000| ps2 read fa | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+049 [BIOS] |07fb0000| ps2_command aux=0 cmd=f4 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042 ctr old=61 new=70 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+049 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+049 [RTC ] cmos read from index 0xF | |
| 03:39:08+050 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+050 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+050 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+050 [BIOS] |07fb0000| ps2_sendbyte aux=0 cmd=f4 | |
| 03:39:08+050 [BIOS] |07fb0000| i8042_kbd_write c=244 | |
| 03:39:08+050 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+051 [BIOS] |07fb0000| ps2 read fa | |
| 03:39:08+051 [BIOS] |07fb0000| i8042_command cmd=1060 | |
| 03:39:08+051 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+051 [BIOS] |07fb0000| i8042_wait_write | |
| 03:39:08+051 [BIOS] |07fb0000| PS2 keyboard initialized | |
| 03:39:08+051 [BIOS] \07fb0000/ End thread | |
| 03:39:08+051 [BIOS] _free 0x07fb0000 (detail=0x07fb1250) | |
| 03:39:08+051 [BIOS] All threads complete. | |
| 03:39:08+051 [BIOS] Scan for option roms | |
| 03:39:08+051 [BIOS] Checking rom 0x000ca000 (sig 0 size 0) | |
| 03:39:08+051 [BIOS] Checking rom 0x000ca800 (sig 0 size 0) | |
| 03:39:08+051 [BIOS] Checking rom 0x000cb000 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cb800 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cc000 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cc800 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cd000 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cd800 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000ce000 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000ce800 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cf000 (sig 0 size 0) | |
| 03:39:08+052 [BIOS] Checking rom 0x000cf800 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d0000 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d0800 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d1000 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d1800 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d2000 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d2800 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d3000 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d3800 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d4000 (sig 0 size 0) | |
| 03:39:08+053 [BIOS] Checking rom 0x000d4800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d5000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d5800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d6000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d6800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d7000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d7800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d8000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d8800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d9000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000d9800 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000da000 (sig 0 size 0) | |
| 03:39:08+054 [BIOS] Checking rom 0x000da800 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000db000 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000db800 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000dc000 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000dc800 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000dd000 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000dd800 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000de000 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000de800 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000df000 (sig 832d size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000df800 (sig 85aa size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000e0000 (sig 0 size 0) | |
| 03:39:08+055 [BIOS] Checking rom 0x000e0800 (sig c3c0 size 83) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e1000 (sig fa89 size 238) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e1800 (sig 2444 size 8) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e2000 (sig 0 size 131) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e2800 (sig f339 size 115) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e3000 (sig 0 size 185) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e3800 (sig b70f size 200) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e4000 (sig 244c size 28) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e4800 (sig 246c size 4) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e5000 (sig ffc3 size 255) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e5800 (sig eb73 size 4) | |
| 03:39:08+056 [BIOS] Checking rom 0x000e6000 (sig 30c6 size 15) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e6800 (sig 8d3a size 0) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e7000 (sig ff0e size 198) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e7800 (sig 9 size 0) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e8000 (sig 89c2 size 248) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e8800 (sig 824 size 139) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e9000 (sig 83f0 size 235) | |
| 03:39:08+057 [BIOS] Checking rom 0x000e9800 (sig 43c7 size 12) | |
| 03:39:08+057 [BIOS] Checking rom 0x000ea000 (sig 8974 size 68) | |
| 03:39:08+057 [BIOS] Checking rom 0x000ea800 (sig e989 size 211) | |
| 03:39:08+057 [BIOS] Checking rom 0x000eb000 (sig 14c4 size 49) | |
| 03:39:08+057 [BIOS] Checking rom 0x000eb800 (sig ee4 size 0) | |
| 03:39:08+058 [BIOS] Checking rom 0x000ec000 (sig dfe8 size 81) | |
| 03:39:08+058 [BIOS] Checking rom 0x000ec800 (sig 557 size 198) | |
| 03:39:08+058 [BIOS] Checking rom 0x000ed000 (sig 6572 size 115) | |
| 03:39:08+059 [BIOS] Checking rom 0x000ed800 (sig 505c size 83) | |
| 03:39:08+059 [BIOS] Searching bootorder for: HALT | |
| 03:39:08+059 [BIOS] Mapping floppy drive 0x000f4fb0 | |
| 03:39:08+059 [BIOS] Mapping hd drive 0x000f4f60 to 0 | |
| 03:39:08+059 [RTC ] cmos read from index 0x39 | |
| 03:39:08+059 [BIOS] drive 0x000f4f60: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=62914560 | |
| 03:39:08+059 [BIOS] finalize PMM | |
| 03:39:08+059 [BIOS] malloc finalize | |
| 03:39:08+109 [BIOS] Add to e820 map: 0009fc00 00000400 2 | |
| 03:39:08+110 [BIOS] Space available for UMB: ca000-ee000, f4ab0-f4f60 | |
| 03:39:08+110 [BIOS] Add to e820 map: 07fc0000 0003e000 1 | |
| 03:39:08+110 [BIOS] Returned 253952 bytes of ZoneHigh | |
| 03:39:08+110 [BIOS] e820 map has 6 items: | |
| 03:39:08+110 [BIOS] 0: 0000000000000000 - 000000000009fc00 = 1 RAM | |
| 03:39:08+111 [BIOS] 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED | |
| 03:39:08+111 [BIOS] 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED | |
| 03:39:08+111 [BIOS] 3: 0000000000100000 - 0000000007ffe000 = 1 RAM | |
| 03:39:08+111 [BIOS] 4: 0000000007ffe000 - 0000000008000000 = 2 RESERVED | |
| 03:39:08+111 [BIOS] 5: 00000000fffc0000 - 0000000100000000 = 2 RESERVED | |
| 03:39:08+133 [BIOS] locking shadow ram | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data2: 0x11 addr=0x80000058 | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data3: 0x11 addr=0x80000058 | |
| 03:39:08+133 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x0058 value=0x11110005 | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data0: 0x11 addr=0x8000005C | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data1: 0x11 addr=0x8000005C | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data2: 0x11 addr=0x8000005C | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x5C 0x8000005C -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data3: 0x31 addr=0x8000005C | |
| 03:39:08+133 [PCI ] PCI write dev=0x00 (82441FX PMC) addr=0x005C value=0x31111111 | |
| 03:39:08+133 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x58 0x80000058 -> 0x00000000 (undef) | |
| 03:39:08+133 [PCI ] PCI data1: 0x10 addr=0x80000058 | |
| 03:39:08+336 [BIOS] Jump to int19 | |
| 03:39:08+337 [RTC ] cmos read from index 0xF | |
| 03:39:08+337 [BIOS] enter handle_19: | |
| 03:39:08+337 [BIOS] NULL | |
| 03:39:08+337 [RTC ] cmos read from index 0xF | |
| Previous message repeated 21 times | |
| 03:39:08+346 [BIOS] Booting from Floppy... | |
| 03:39:08+346 [RTC ] cmos read from index 0xF | |
| 03:39:08+346 [RTC ] cmos read from index 0xF | |
| 03:39:08+346 [BIOS] Floppy_drive_recal 0 | |
| 03:39:08+346 [BIOS] Floppy_enable_controller | |
| 03:39:08+347 [IO ] write8 port #0x03F7 <- 0x00 (PORT_FD_DIR) | |
| 03:39:08+349 [BIOS] Floppy_media_sense on drive 0 found rate 0 | |
| 03:39:08+349 [DMA ] port A write: 0x6 | |
| 03:39:08+349 [DMA ] port 4 write 0 | |
| 03:39:08+349 [DMA ] port 4 write 124 | |
| 03:39:08+349 [DMA ] port 5 write 255 | |
| 03:39:08+349 [DMA ] port 5 write 1 | |
| 03:39:08+349 [DMA ] port B write: 0x46 | |
| 03:39:08+349 [DMA ] port A write: 0x2 | |
| 03:39:10+372 [BIOS] WARNING - Timeout at floppy_wait_irq:206! | |
| 03:39:10+372 [BIOS] Floppy_disable_controller | |
| 03:39:10+372 [BIOS] invalid basic_access:96: | |
| 03:39:10+372 [BIOS] a=00000200 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=df00 | |
| 03:39:10+373 [BIOS] si=00000000 di=00000000 bp=00000000 sp=0000fc50 cs=f000 ip=cb54 f=0202 | |
| 03:39:10+373 [RTC ] cmos read from index 0xF | |
| Previous message repeated 41 times | |
| 03:39:10+384 [BIOS] Boot failed: could not read the boot disk | |
| 03:39:10+384 [RTC ] cmos read from index 0xF | |
| 03:39:10+384 [RTC ] cmos read from index 0xF | |
| 03:39:10+384 [BIOS] | |
| 03:39:10+384 [RTC ] cmos read from index 0xF | |
| Previous message repeated 2 times | |
| 03:39:10+385 [BIOS] enter handle_18: | |
| 03:39:10+385 [BIOS] NULL | |
| 03:39:10+386 [RTC ] cmos read from index 0xF | |
| Previous message repeated 24 times | |
| 03:39:10+396 [BIOS] Booting from Hard Disk... | |
| 03:39:10+396 [RTC ] cmos read from index 0xF | |
| Previous message repeated 2 times | |
| 03:39:10+408 [BIOS] Booting from 0000:7c00 | |
| 03:39:29+647 [BIOS] stub handle_1012XX:1004: | |
| 03:39:29+647 [BIOS] a=00001202 b=00000301 c=00000000 d=00020000 ds=22f3 es=0000 ss=ee1f | |
| 03:39:29+648 [BIOS] si=00000000 di=000014ea bp=000014da sp=000001f6 cs=2000 ip=02fa f=0293 | |
| 03:39:29+648 [BIOS] set VGA mode 3 | |
| 03:39:29+648 [IO ] write8 port #0x03C6 <- 0xFF | |
| 03:39:29+667 [BIOS] stub handle_10XX:1147: | |
| 03:39:29+667 [BIOS] a=00002000 b=00000000 c=00000000 d=00020000 ds=22f3 es=22f3 ss=ee1f | |
| 03:39:29+667 [BIOS] si=00000000 di=000014ea bp=000014da sp=000001f6 cs=2000 ip=02fa f=0293 | |
| 03:39:29+671 [BIOS] i8042_command cmd=ae | |
| 03:39:29+671 [BIOS] i8042_wait_write | |
| 03:39:30+196 [BIOS] set VGA mode 12 | |
| 03:39:30+196 [IO ] write8 port #0x03C6 <- 0xFF | |
| 03:39:30+950 [BIOS] invalid handle_1ab10e:156: | |
| 03:39:30+950 [BIOS] a=4153b10e b=00000000 c=00000000 d=20491a49 ds=f000 es=1a49 ss=1a49 | |
| 03:39:30+951 [BIOS] si=00000000 di=00000d34 bp=00000d1c sp=00000d0c cs=1000 ip=77dd f=0246 | |
| 03:39:30+974 [BIOS] pnp call arg1=0 | |
| 03:39:30+975 [BIOS] invalid handle_legacy_disk:819: | |
| 03:39:30+975 [BIOS] a=0000153f b=00000000 c=00000001 d=00060081 ds=1a49 es=502b ss=df00 | |
| 03:39:30+975 [BIOS] si=0000145e di=000f0000 bp=00000d38 sp=0000fc50 cs=1000 ip=5dd4 f=0202 | |
| 03:39:30+977 [SERI] read line control: 0x0 | |
| 03:39:30+977 [SERI] line control: 0x80 | |
| 03:39:30+978 [SERI] baud rate: 0x0 | |
| 03:39:30+978 [SERI] line control: 0x0 | |
| 03:39:30+978 [SERI] interrupt enable: 0xF | |
| 03:39:30+978 [SERI] line control: 0x80 | |
| 03:39:30+978 [SERI] line control: 0x0 | |
| 03:39:30+978 [SERI] line control: 0x0 | |
| 03:39:30+978 [SERI] interrupt enable: 0x2 | |
| 03:39:30+978 [SERI] line control: 0x80 | |
| 03:39:30+978 [SERI] baud rate: 0xC | |
| 03:39:30+978 [SERI] line control: 0x0 | |
| 03:39:30+978 [SERI] read interrupt identification: 0x1 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] modem control: 0x8 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] interrupt enable: 0xF | |
| 03:39:30+978 [SERI] read interrupt identification: 0x1 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] modem control: 0x8 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] interrupt enable: 0xF | |
| 03:39:30+978 [SERI] read interrupt identification: 0x1 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] interrupt enable: 0x0 | |
| 03:39:30+978 [SERI] modem control: 0x0 | |
| 03:39:30+979 [IO ] read8 port #0x02FB | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0x80 | |
| 03:39:30+979 [IO ] read8 port #0x02F9 | |
| 03:39:30+979 [IO ] read8 port #0x02F8 (PORT_SERIAL2) | |
| 03:39:30+979 [IO ] write8 port #0x02F9 <- 0x00 | |
| 03:39:30+979 [IO ] write8 port #0x02F8 <- 0x0C (PORT_SERIAL2) | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0x00 | |
| 03:39:30+979 [IO ] read8 port #0x02F9 | |
| 03:39:30+979 [IO ] write8 port #0x02F9 <- 0x0F | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0x80 | |
| 03:39:30+979 [IO ] read8 port #0x02F9 | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0x00 | |
| 03:39:30+979 [IO ] write8 port #0x02F9 <- 0xFF | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0x80 | |
| 03:39:30+979 [IO ] write8 port #0x02F9 <- 0xFF | |
| 03:39:30+979 [IO ] write8 port #0x02F8 <- 0xFF (PORT_SERIAL2) | |
| 03:39:30+979 [IO ] write8 port #0x02FB <- 0xFF | |
| 03:39:30+979 [IO ] read8 port #0x03EB | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0x80 | |
| 03:39:30+979 [IO ] read8 port #0x03E9 | |
| 03:39:30+979 [IO ] read8 port #0x03E8 (PORT_SERIAL3) | |
| 03:39:30+979 [IO ] write8 port #0x03E9 <- 0x00 | |
| 03:39:30+979 [IO ] write8 port #0x03E8 <- 0x0C (PORT_SERIAL3) | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0x00 | |
| 03:39:30+979 [IO ] read8 port #0x03E9 | |
| 03:39:30+979 [IO ] write8 port #0x03E9 <- 0x0F | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0x80 | |
| 03:39:30+979 [IO ] read8 port #0x03E9 | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0x00 | |
| 03:39:30+979 [IO ] write8 port #0x03E9 <- 0xFF | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0x80 | |
| 03:39:30+979 [IO ] write8 port #0x03E9 <- 0xFF | |
| 03:39:30+979 [IO ] write8 port #0x03E8 <- 0xFF (PORT_SERIAL3) | |
| 03:39:30+979 [IO ] write8 port #0x03EB <- 0xFF | |
| 03:39:30+979 [IO ] read8 port #0x02EB | |
| 03:39:30+979 [IO ] write8 port #0x02EB <- 0x80 | |
| 03:39:30+979 [IO ] read8 port #0x02E9 | |
| 03:39:30+979 [IO ] read8 port #0x02E8 (PORT_SERIAL4) | |
| 03:39:30+979 [IO ] write8 port #0x02E9 <- 0x00 | |
| 03:39:30+980 [IO ] write8 port #0x02E8 <- 0x0C (PORT_SERIAL4) | |
| 03:39:30+981 [IO ] write8 port #0x02EB <- 0x00 | |
| 03:39:30+981 [IO ] read8 port #0x02E9 | |
| 03:39:30+981 [IO ] write8 port #0x02E9 <- 0x0F | |
| 03:39:30+981 [IO ] write8 port #0x02EB <- 0x80 | |
| 03:39:30+981 [IO ] read8 port #0x02E9 | |
| 03:39:30+981 [IO ] write8 port #0x02EB <- 0x00 | |
| 03:39:30+981 [IO ] write8 port #0x02E9 <- 0xFF | |
| 03:39:30+981 [IO ] write8 port #0x02EB <- 0x80 | |
| 03:39:30+981 [IO ] write8 port #0x02E9 <- 0xFF | |
| 03:39:30+981 [IO ] write8 port #0x02E8 <- 0xFF (PORT_SERIAL4) | |
| 03:39:30+981 [IO ] write8 port #0x02EB <- 0xFF | |
| 03:39:30+981 [BIOS] enter handle_11: | |
| 03:39:30+982 [BIOS] a=00000000 b=0000000c c=00000040 d=00060000 ds=1a49 es=0040 ss=df00 | |
| 03:39:30+982 [BIOS] si=00001338 di=000f0000 bp=00000d3c sp=0000fc50 cs=1000 ip=412e f=0246 | |
| 03:39:30+983 [IO ] read8 port #0x023E | |
| 03:39:30+983 [IO ] read8 port #0x023E | |
| 03:39:30+983 [IO ] read8 port #0x023A | |
| 03:39:30+983 [IO ] read8 port #0x023A | |
| 03:39:30+983 [IO ] read8 port #0x0236 | |
| 03:39:30+983 [IO ] read8 port #0x0236 | |
| 03:39:30+983 [IO ] read8 port #0x0232 | |
| 03:39:30+985 [IO ] read8 port #0x0232 | |
| 03:39:30+985 [BIOS] invalid handle_legacy_disk:819: | |
| 03:39:30+985 [BIOS] a=0000150b b=0000000b c=00000000 d=00065001 ds=1a49 es=5057 ss=df00 | |
| 03:39:30+985 [BIOS] si=0000502e di=000f55b4 bp=00000d3c sp=0000fc50 cs=1000 ip=55be f=0202 | |
| 03:39:30+985 [RTC ] cmos read from index 0x10 | |
| 03:39:31+050 [BIOS] unimplemented handle_15XX:340: | |
| 03:39:31+050 [BIOS] a=0000e980 b=00000085 c=0000506d d=47534943 ds=1a49 es=1a49 ss=df00 | |
| 03:39:31+051 [BIOS] si=0000502e di=000f0000 bp=00000ce8 sp=0000fc50 cs=1000 ip=01af f=0202 | |
| 03:39:41+137 [BIOS] i8042_command cmd=ae | |
| 03:39:41+137 [BIOS] i8042_wait_write | |
| 03:39:41+248 [BIOS] i8042_command cmd=ae | |
| 03:39:41+248 [BIOS] i8042_wait_write | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x28 0x80000028 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFEBF9000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x34 0x80000034 -> 0x00000000 | |
| 03:39:41+622 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x38 0x80000038 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x28 0x80000028 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFEBF9000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x34 0x80000034 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x38 0x80000038 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x28 0x80000028 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFEBF9000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x34 0x80000034 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x38 0x80000038 -> 0x00000000 | |
| 03:39:41+623 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000C121 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x28 0x8000F028 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x2C 0x8000F02C -> 0x82D41043 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0xFEBFF000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x34 0x8000F034 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x38 0x8000F038 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:41+624 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000C121 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x28 0x8000F028 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x2C 0x8000F02C -> 0x82D41043 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0xFEBFF000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x34 0x8000F034 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x38 0x8000F038 -> 0x00000000 | |
| 03:39:41+624 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:39:41+624 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:10+756 [ ] 0x003DD268 size=4 v=0x3AA83A9C | |
| 03:40:10+757 [ ] Error | |
| at Error (native) | |
| at dbg_trace (http://localhost/v86/src/log.js:92:13) | |
| at Memory.debug_write (http://localhost/v86/src/memory.js:89:9) | |
| at Memory.write_aligned32 (http://localhost/v86/src/memory.js:359:10) | |
| at movsd (http://localhost/v86/src/string.js:235:28) | |
| at Array.t.(anonymous function).cpu (http://localhost/v86/src/instructions.js:682:22) | |
| at CPU.do_op (http://localhost/v86/src/cpu.js:918:33) | |
| at Array.t.(anonymous function).cpu (http://localhost/v86/src/instructions.js:1251:9) | |
| at CPU.cycle (http://localhost/v86/src/cpu.js:893:23) | |
| at CPU.do_many_cycles2 (http://localhost/v86/src/cpu.js:807:18) | |
| 03:40:13+983 [BIOS] set VGA mode 3 | |
| 03:40:13+983 [IO ] write8 port #0x03C6 <- 0xFF | |
| 03:40:13+998 [APIC] IOAPIC write 0x1 <- 0x00000000 | |
| 03:40:13+998 [APIC] IOAPIC register write outside of range 0x1: 0x00000000 | |
| 03:40:13+998 [APIC] IOAPIC read32 0x1 | |
| 03:40:13+999 [APIC] unsupported read8 from apic: 0xFEE00030 | |
| 03:40:13+999 [APIC] APIC read version | |
| 03:40:13+999 [APIC] IOAPIC write 0x1 <- 0x00000000 | |
| 03:40:13+999 [APIC] IOAPIC register write outside of range 0x1: 0x00000000 | |
| 03:40:13+999 [APIC] IOAPIC read32 0x1 | |
| 03:40:13+999 [APIC] IOAPIC write 0x1 <- 0x00000000 | |
| 03:40:13+999 [APIC] IOAPIC register write outside of range 0x1: 0x00000000 | |
| 03:40:13+999 [APIC] IOAPIC read32 0x1 | |
| 03:40:13+999 [APIC] APIC write32 0xE0 <- 0xFFFFFFFF | |
| 03:40:13+999 [APIC] APIC write32 0xD0 <- 0x01000000 | |
| 03:40:13+999 [APIC] APIC write32 0xF0 <- 0x0000011F | |
| 03:40:13+999 [APIC] APIC write32 0x370 <- 0x000000E3 | |
| 03:40:13+999 [APIC] timer lvt: 0x000300FD | |
| 03:40:13+999 [APIC] APIC write32 0x340 <- 0x000100FE | |
| 03:40:13+999 [APIC] APIC write32 0x350 <- 0x0001001F | |
| 03:40:13+999 [APIC] APIC write32 0x360 <- 0x000184FF | |
| 03:40:13+999 [APIC] APIC write icr0: 0x00088500 vector=0x00 destination_mode=0 delivery_mode=5 destination_shorthand=all with self | |
| 03:40:14+004 [APIC] APIC read 0x20 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x0 | |
| 03:40:14+004 [APIC] IOAPIC write 0x0 <- 0x00000000 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x10 | |
| 03:40:14+004 [APIC] Read config irq=0x0 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x10 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x0 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x12 | |
| 03:40:14+004 [APIC] Read config irq=0x1 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x12 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x1 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x14 | |
| 03:40:14+004 [APIC] Read config irq=0x2 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x14 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x2 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x16 | |
| 03:40:14+004 [APIC] Read config irq=0x3 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x16 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x3 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x18 | |
| 03:40:14+004 [APIC] Read config irq=0x4 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x18 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x4 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x1A | |
| 03:40:14+004 [APIC] Read config irq=0x5 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x1A <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x5 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x1C | |
| 03:40:14+004 [APIC] Read config irq=0x6 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x1C <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x6 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x1E | |
| 03:40:14+004 [APIC] Read config irq=0x7 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x1E <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x7 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x20 | |
| 03:40:14+004 [APIC] Read config irq=0x8 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x20 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x8 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x22 | |
| 03:40:14+004 [APIC] Read config irq=0x9 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x22 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x9 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x24 | |
| 03:40:14+004 [APIC] Read config irq=0xA -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x24 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xA vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x26 | |
| 03:40:14+004 [APIC] Read config irq=0xB -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x26 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xB vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x28 | |
| 03:40:14+004 [APIC] Read config irq=0xC -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x28 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xC vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x2A | |
| 03:40:14+004 [APIC] Read config irq=0xD -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x2A <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xD vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x2C | |
| 03:40:14+004 [APIC] Read config irq=0xE -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x2C <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xE vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x2E | |
| 03:40:14+004 [APIC] Read config irq=0xF -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x2E <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0xF vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x30 | |
| 03:40:14+004 [APIC] Read config irq=0x10 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x30 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x10 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x32 | |
| 03:40:14+004 [APIC] Read config irq=0x11 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x32 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x11 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x34 | |
| 03:40:14+004 [APIC] Read config irq=0x12 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x34 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x12 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x36 | |
| 03:40:14+004 [APIC] Read config irq=0x13 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x36 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x13 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x38 | |
| 03:40:14+004 [APIC] Read config irq=0x14 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x38 <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x14 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x3A | |
| 03:40:14+004 [APIC] Read config irq=0x15 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x3A <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x15 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x3C | |
| 03:40:14+004 [APIC] Read config irq=0x16 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x3C <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x16 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] IOAPIC read32 0x3E | |
| 03:40:14+004 [APIC] Read config irq=0x17 -> 0x00010000 | |
| 03:40:14+004 [APIC] IOAPIC write 0x3E <- 0x000100FF | |
| 03:40:14+004 [APIC] Write config 0x000100FF irq=0x17 vector=0xFF delivery=0x0 destmode=0 is_level=0 disabled=1 | |
| 03:40:14+004 [APIC] timer lvt: 0x000300FD | |
| 03:40:14+004 [APIC] timer divider: 0x0000000B | |
| 03:40:14+004 [APIC] read timer initial count | |
| 03:40:14+132 [APIC] IOAPIC write 0x21 <- 0x01000000 | |
| 03:40:14+132 [APIC] Write destination 0x01000000 irq=0x8 dest=0x01 | |
| 03:40:14+132 [APIC] IOAPIC write 0x20 <- 0x000008D1 | |
| 03:40:14+132 [APIC] Write config 0x000008D1 irq=0x8 vector=0xD1 delivery=0x0 destmode=1 is_level=0 disabled=0 | |
| 03:40:14+136 [RTC ] Periodic interrupt, a=0x2A t=15.625 | |
| 03:40:14+136 [RTC ] cmos b=0x42 | |
| 03:40:14+136 [RTC ] cmos reg C read | |
| 03:40:14+137 [APIC] timer lvt: 0x000300FD | |
| 03:40:14+173 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:15+181 [APIC] APIC read icr0 | |
| 03:40:15+181 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+181 [APIC] APIC read icr0 | |
| 03:40:15+183 [RTC ] cmos reg C read | |
| 03:40:15+183 [RTC ] cmos reg C read | |
| 03:40:15+183 [APIC] APIC write32 0x360 <- 0x000004FF | |
| 03:40:15+192 [BIOS] set VGA mode 12 | |
| 03:40:15+194 [IO ] write8 port #0x03C6 <- 0xFF | |
| 03:40:15+218 [RTC ] cmos reg C read | |
| 03:40:15+218 [RTC ] cmos reg C read | |
| 03:40:15+218 [APIC] APIC read icr0 | |
| 03:40:15+218 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+218 [APIC] APIC read icr0 | |
| 03:40:15+238 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+248 [APIC] APIC read icr0 | |
| 03:40:15+248 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+248 [APIC] APIC read icr0 | |
| 03:40:15+262 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+708 [APIC] APIC read icr0 | |
| 03:40:15+708 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+708 [APIC] APIC read icr0 | |
| 03:40:15+716 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+730 [APIC] APIC read icr0 | |
| 03:40:15+730 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+730 [APIC] APIC read icr0 | |
| 03:40:15+746 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+762 [APIC] APIC read icr0 | |
| 03:40:15+762 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+762 [APIC] APIC read icr0 | |
| 03:40:15+788 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+793 [APIC] APIC read icr0 | |
| 03:40:15+793 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+793 [APIC] APIC read icr0 | |
| 03:40:15+808 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+824 [APIC] APIC read icr0 | |
| 03:40:15+824 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+824 [APIC] APIC read icr0 | |
| 03:40:15+841 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+855 [APIC] APIC read icr0 | |
| 03:40:15+855 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+855 [APIC] APIC read icr0 | |
| 03:40:15+871 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+888 [APIC] APIC read icr0 | |
| 03:40:15+888 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+888 [APIC] APIC read icr0 | |
| 03:40:15+903 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+919 [APIC] APIC read icr0 | |
| 03:40:15+919 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+919 [APIC] APIC read icr0 | |
| 03:40:15+935 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+950 [APIC] APIC read icr0 | |
| 03:40:15+950 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+950 [APIC] APIC read icr0 | |
| 03:40:15+965 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:15+981 [APIC] APIC read icr0 | |
| 03:40:15+981 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:15+981 [APIC] APIC read icr0 | |
| 03:40:15+996 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:16+012 [APIC] APIC read icr0 | |
| 03:40:16+012 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:16+012 [APIC] APIC read icr0 | |
| 03:40:16+027 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:16+048 [APIC] APIC read icr0 | |
| 03:40:16+048 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:16+048 [APIC] APIC read icr0 | |
| 03:40:16+056 [RTC ] cmos read from index 0x6 | |
| 03:40:16+057 [APIC] APIC read icr0 | |
| 03:40:16+057 [APIC] APIC write icr1: 0x01000000 | |
| 03:40:16+057 [APIC] APIC write icr0: 0x000008C1 vector=0xC1 destination_mode=1 delivery_mode=0 destination_shorthand=no | |
| 03:40:16+057 [APIC] APIC read icr0 | |
| 03:40:16+057 [APIC] APIC write32 0x340 <- 0x0000A0FE | |
| 03:40:16+058 [RTC ] cmos reg C read | |
| Previous message repeated 17 times | |
| 03:40:16+183 [APIC] APIC read icr0 | |
| 03:40:16+183 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:16+183 [APIC] APIC read icr0 | |
| 03:40:16+199 [RTC ] cmos reg C read | |
| 03:40:16+199 [RTC ] cmos reg C read | |
| 03:40:16+199 [APIC] APIC read icr0 | |
| 03:40:16+199 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:16+199 [APIC] APIC read icr0 | |
| 03:40:16+216 [RTC ] cmos reg C read | |
| Previous message repeated 289 times | |
| 03:40:18+467 [RTC ] cmos read from index 0x6 | |
| 03:40:18+480 [RTC ] cmos reg C read | |
| 03:40:18+483 [RTC ] cmos reg C read | |
| 03:40:18+483 [RTC ] cmos write index 0x0: 0x18 | |
| 03:40:18+483 [RTC ] cmos write index 0x2: 0x40 | |
| 03:40:18+483 [RTC ] cmos write index 0x4: 0x1 | |
| 03:40:18+483 [RTC ] cmos write index 0x6: 0x4 | |
| 03:40:18+483 [RTC ] cmos write index 0x7: 0x3 | |
| 03:40:18+483 [RTC ] cmos write index 0x8: 0x3 | |
| 03:40:18+483 [RTC ] cmos write index 0x32: 0x20 | |
| 03:40:18+483 [RTC ] cmos write index 0x9: 0x16 | |
| 03:40:18+496 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:18+518 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:40:18+518 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 256 times | |
| 03:40:18+528 [RTC ] cmos reg C read | |
| 03:40:18+528 [RTC ] cmos reg C read | |
| 03:40:18+528 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 546 times | |
| 03:40:18+544 [RTC ] cmos reg C read | |
| 03:40:18+544 [RTC ] cmos reg C read | |
| 03:40:18+544 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 395 times | |
| 03:40:18+559 [RTC ] cmos reg C read | |
| 03:40:18+559 [RTC ] cmos reg C read | |
| 03:40:18+559 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+574 [RTC ] cmos reg C read | |
| 03:40:18+574 [RTC ] cmos reg C read | |
| 03:40:18+574 [APIC] APIC read icr0 | |
| 03:40:18+574 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:18+574 [APIC] APIC read icr0 | |
| 03:40:18+574 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+590 [RTC ] cmos reg C read | |
| 03:40:18+590 [RTC ] cmos reg C read | |
| 03:40:18+590 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+605 [RTC ] cmos reg C read | |
| 03:40:18+605 [RTC ] cmos reg C read | |
| 03:40:18+605 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+622 [RTC ] cmos reg C read | |
| 03:40:18+622 [RTC ] cmos reg C read | |
| 03:40:18+622 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 496 times | |
| 03:40:18+637 [RTC ] cmos reg C read | |
| 03:40:18+637 [RTC ] cmos reg C read | |
| 03:40:18+637 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+653 [RTC ] cmos reg C read | |
| 03:40:18+653 [RTC ] cmos reg C read | |
| 03:40:18+653 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 496 times | |
| 03:40:18+668 [RTC ] cmos reg C read | |
| 03:40:18+668 [RTC ] cmos reg C read | |
| 03:40:18+668 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+683 [RTC ] cmos reg C read | |
| 03:40:18+683 [RTC ] cmos reg C read | |
| 03:40:18+683 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+699 [RTC ] cmos reg C read | |
| 03:40:18+699 [RTC ] cmos reg C read | |
| 03:40:18+699 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+716 [RTC ] cmos reg C read | |
| 03:40:18+716 [RTC ] cmos reg C read | |
| 03:40:18+716 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 446 times | |
| 03:40:18+730 [RTC ] cmos reg C read | |
| 03:40:18+730 [RTC ] cmos reg C read | |
| 03:40:18+730 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 545 times | |
| 03:40:18+746 [RTC ] cmos reg C read | |
| 03:40:18+746 [RTC ] cmos reg C read | |
| 03:40:18+746 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+763 [RTC ] cmos reg C read | |
| 03:40:18+763 [RTC ] cmos reg C read | |
| 03:40:18+763 [APIC] APIC read icr0 | |
| 03:40:18+763 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:18+763 [APIC] APIC read icr0 | |
| 03:40:18+763 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 313 times | |
| 03:40:18+777 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:18+794 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:40:18+794 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 458 times | |
| 03:40:18+809 [RTC ] cmos reg C read | |
| 03:40:18+809 [RTC ] cmos reg C read | |
| 03:40:18+809 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 496 times | |
| 03:40:18+824 [RTC ] cmos reg C read | |
| 03:40:18+824 [RTC ] cmos reg C read | |
| 03:40:18+824 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+840 [RTC ] cmos reg C read | |
| 03:40:18+840 [RTC ] cmos reg C read | |
| 03:40:18+840 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 496 times | |
| 03:40:18+855 [RTC ] cmos reg C read | |
| 03:40:18+855 [RTC ] cmos reg C read | |
| 03:40:18+855 [APIC] APIC read icr0 | |
| 03:40:18+855 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:18+855 [APIC] APIC read icr0 | |
| 03:40:18+855 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+871 [RTC ] cmos reg C read | |
| 03:40:18+872 [RTC ] cmos reg C read | |
| 03:40:18+872 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 545 times | |
| 03:40:18+888 [RTC ] cmos reg C read | |
| 03:40:18+888 [RTC ] cmos reg C read | |
| 03:40:18+888 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+903 [RTC ] cmos reg C read | |
| 03:40:18+903 [RTC ] cmos reg C read | |
| 03:40:18+903 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 545 times | |
| 03:40:18+919 [RTC ] cmos reg C read | |
| 03:40:18+919 [RTC ] cmos reg C read | |
| 03:40:18+919 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 445 times | |
| 03:40:18+933 [RTC ] cmos reg C read | |
| 03:40:18+934 [RTC ] cmos reg C read | |
| 03:40:18+934 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+949 [RTC ] cmos reg C read | |
| 03:40:18+949 [RTC ] cmos reg C read | |
| 03:40:18+949 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 545 times | |
| 03:40:18+965 [RTC ] cmos reg C read | |
| 03:40:18+966 [RTC ] cmos reg C read | |
| 03:40:18+966 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 495 times | |
| 03:40:18+980 [RTC ] cmos reg C read | |
| 03:40:18+981 [RTC ] cmos reg C read | |
| 03:40:18+981 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:18+997 [RTC ] cmos reg C read | |
| 03:40:18+997 [RTC ] cmos reg C read | |
| 03:40:18+997 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 496 times | |
| 03:40:19+012 [RTC ] cmos reg C read | |
| 03:40:19+012 [RTC ] cmos reg C read | |
| 03:40:19+012 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 544 times | |
| 03:40:19+028 [RTC ] cmos reg C read | |
| 03:40:19+028 [RTC ] cmos reg C read | |
| 03:40:19+028 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 458 times | |
| 03:40:19+044 [RTC ] cmos reg C read | |
| Previous message repeated 35 times | |
| 03:40:19+309 [APIC] APIC read icr0 | |
| 03:40:19+309 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:19+309 [APIC] APIC read icr0 | |
| 03:40:19+325 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:19+393 [APIC] APIC read icr0 | |
| 03:40:19+393 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:19+393 [APIC] APIC read icr0 | |
| 03:40:19+402 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:19+474 [APIC] APIC read icr0 | |
| 03:40:19+474 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:19+474 [APIC] APIC read icr0 | |
| 03:40:19+480 [RTC ] cmos reg C read | |
| Previous message repeated 21 times | |
| 03:40:19+643 [APIC] APIC read icr0 | |
| 03:40:19+643 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:19+643 [APIC] APIC read icr0 | |
| 03:40:19+652 [RTC ] cmos reg C read | |
| Previous message repeated 49 times | |
| 03:40:20+039 [APIC] APIC read icr0 | |
| 03:40:20+039 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+039 [APIC] APIC read icr0 | |
| 03:40:20+044 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:20+117 [APIC] APIC read icr0 | |
| 03:40:20+117 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+117 [APIC] APIC read icr0 | |
| 03:40:20+122 [RTC ] cmos reg C read | |
| Previous message repeated 37 times | |
| 03:40:20+403 [APIC] APIC read icr0 | |
| 03:40:20+403 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+403 [APIC] APIC read icr0 | |
| 03:40:20+419 [RTC ] cmos reg C read | |
| Previous message repeated 19 times | |
| 03:40:20+559 [APIC] APIC read icr0 | |
| 03:40:20+559 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+559 [APIC] APIC read icr0 | |
| 03:40:20+575 [RTC ] cmos reg C read | |
| Previous message repeated 13 times | |
| 03:40:20+681 [APIC] APIC read icr0 | |
| 03:40:20+681 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+681 [APIC] APIC read icr0 | |
| 03:40:20+683 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:20+761 [APIC] APIC read icr0 | |
| 03:40:20+761 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+761 [APIC] APIC read icr0 | |
| 03:40:20+763 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:20+837 [APIC] APIC read icr0 | |
| 03:40:20+837 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+837 [APIC] APIC read icr0 | |
| 03:40:20+840 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:20+887 [APIC] APIC read icr0 | |
| 03:40:20+887 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+887 [APIC] APIC read icr0 | |
| 03:40:20+902 [RTC ] cmos reg C read | |
| 03:40:20+912 [RTC ] cmos reg C read | |
| 03:40:20+912 [APIC] APIC read icr0 | |
| 03:40:20+912 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:20+912 [APIC] APIC read icr0 | |
| 03:40:20+919 [RTC ] cmos reg C read | |
| Previous message repeated 25 times | |
| 03:40:21+111 [APIC] APIC read icr0 | |
| 03:40:21+111 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+111 [APIC] APIC read icr0 | |
| 03:40:21+122 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:21+180 [APIC] APIC read icr0 | |
| 03:40:21+180 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+180 [APIC] APIC read icr0 | |
| 03:40:21+183 [RTC ] cmos reg C read | |
| Previous message repeated 39 times | |
| 03:40:21+482 [APIC] APIC read icr0 | |
| 03:40:21+482 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+482 [APIC] APIC read icr0 | |
| 03:40:21+496 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:21+564 [APIC] APIC read icr0 | |
| 03:40:21+564 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+564 [APIC] APIC read icr0 | |
| 03:40:21+574 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:21+642 [APIC] APIC read icr0 | |
| 03:40:21+642 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+642 [APIC] APIC read icr0 | |
| 03:40:21+652 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:21+719 [APIC] APIC read icr0 | |
| 03:40:21+719 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+719 [APIC] APIC read icr0 | |
| 03:40:21+730 [RTC ] cmos reg C read | |
| Previous message repeated 13 times | |
| 03:40:21+833 [APIC] APIC read icr0 | |
| 03:40:21+833 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:21+833 [APIC] APIC read icr0 | |
| 03:40:21+840 [RTC ] cmos reg C read | |
| Previous message repeated 27 times | |
| 03:40:22+050 [APIC] APIC read icr0 | |
| 03:40:22+050 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:22+050 [APIC] APIC read icr0 | |
| 03:40:22+058 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:22+116 [APIC] APIC read icr0 | |
| 03:40:22+116 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:22+116 [APIC] APIC read icr0 | |
| 03:40:22+121 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:22+183 [APIC] APIC read icr0 | |
| 03:40:22+183 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:22+183 [APIC] APIC read icr0 | |
| 03:40:22+184 [RTC ] cmos reg C read | |
| Previous message repeated 21 times | |
| 03:40:22+341 [APIC] APIC read icr0 | |
| 03:40:22+341 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:22+341 [APIC] APIC read icr0 | |
| 03:40:22+355 [RTC ] cmos reg C read | |
| Previous message repeated 17 times | |
| 03:40:22+494 [APIC] APIC read icr0 | |
| 03:40:22+495 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:22+495 [APIC] APIC read icr0 | |
| 03:40:22+496 [RTC ] cmos reg C read | |
| Previous message repeated 91 times | |
| 03:40:23+206 [APIC] APIC read icr0 | |
| 03:40:23+206 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:23+206 [APIC] APIC read icr0 | |
| 03:40:23+215 [RTC ] cmos reg C read | |
| Previous message repeated 31 times | |
| 03:40:23+454 [APIC] APIC read icr0 | |
| 03:40:23+454 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:23+454 [APIC] APIC read icr0 | |
| 03:40:23+465 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:23+530 [APIC] APIC read icr0 | |
| 03:40:23+530 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:23+530 [APIC] APIC read icr0 | |
| 03:40:23+543 [RTC ] cmos reg C read | |
| Previous message repeated 15 times | |
| 03:40:23+653 [APIC] APIC read icr0 | |
| 03:40:23+653 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:23+653 [APIC] APIC read icr0 | |
| 03:40:23+668 [RTC ] cmos reg C read | |
| Previous message repeated 33 times | |
| 03:40:23+932 [APIC] APIC read icr0 | |
| 03:40:23+932 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:23+932 [APIC] APIC read icr0 | |
| 03:40:23+933 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+008 [APIC] APIC read icr0 | |
| 03:40:24+008 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+008 [APIC] APIC read icr0 | |
| 03:40:24+012 [RTC ] cmos reg C read | |
| 03:40:24+012 [RTC ] cmos reg C read | |
| 03:40:24+012 [APIC] APIC read icr0 | |
| 03:40:24+012 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+012 [APIC] APIC read icr0 | |
| 03:40:24+027 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:24+079 [APIC] APIC read icr0 | |
| 03:40:24+079 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+079 [APIC] APIC read icr0 | |
| 03:40:24+090 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:24+151 [APIC] APIC read icr0 | |
| 03:40:24+151 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+151 [APIC] APIC read icr0 | |
| 03:40:24+153 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+223 [APIC] APIC read icr0 | |
| 03:40:24+223 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+223 [APIC] APIC read icr0 | |
| 03:40:24+230 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+295 [APIC] APIC read icr0 | |
| 03:40:24+295 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+295 [APIC] APIC read icr0 | |
| 03:40:24+308 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:24+367 [APIC] APIC read icr0 | |
| 03:40:24+367 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+367 [APIC] APIC read icr0 | |
| 03:40:24+371 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+448 [APIC] APIC read icr0 | |
| 03:40:24+448 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+448 [APIC] APIC read icr0 | |
| 03:40:24+449 [RTC ] cmos reg C read | |
| Previous message repeated 11 times | |
| 03:40:24+536 [APIC] APIC read icr0 | |
| 03:40:24+536 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+536 [APIC] APIC read icr0 | |
| 03:40:24+543 [RTC ] cmos reg C read | |
| Previous message repeated 11 times | |
| 03:40:24+626 [APIC] APIC read icr0 | |
| 03:40:24+626 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+626 [APIC] APIC read icr0 | |
| 03:40:24+638 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:24+697 [APIC] APIC read icr0 | |
| 03:40:24+697 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+697 [APIC] APIC read icr0 | |
| 03:40:24+699 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+766 [APIC] APIC read icr0 | |
| 03:40:24+766 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+766 [APIC] APIC read icr0 | |
| 03:40:24+777 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+845 [APIC] APIC read icr0 | |
| 03:40:24+845 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+845 [APIC] APIC read icr0 | |
| 03:40:24+855 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:24+923 [APIC] APIC read icr0 | |
| 03:40:24+923 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+923 [APIC] APIC read icr0 | |
| 03:40:24+933 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:24+949 [APIC] APIC read icr0 | |
| 03:40:24+949 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:24+949 [APIC] APIC read icr0 | |
| 03:40:24+965 [RTC ] cmos reg C read | |
| Previous message repeated 5 times | |
| 03:40:25+000 [APIC] APIC read icr0 | |
| 03:40:25+000 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+000 [APIC] APIC read icr0 | |
| 03:40:25+013 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:25+071 [APIC] APIC read icr0 | |
| 03:40:25+071 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+071 [APIC] APIC read icr0 | |
| 03:40:25+074 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:25+142 [APIC] APIC read icr0 | |
| 03:40:25+142 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+142 [APIC] APIC read icr0 | |
| 03:40:25+152 [RTC ] cmos reg C read | |
| Previous message repeated 5 times | |
| 03:40:25+188 [APIC] APIC read icr0 | |
| 03:40:25+188 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+188 [APIC] APIC read icr0 | |
| 03:40:25+200 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:25+262 [APIC] APIC read icr0 | |
| 03:40:25+262 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+262 [APIC] APIC read icr0 | |
| 03:40:25+277 [RTC ] cmos reg C read | |
| Previous message repeated 23 times | |
| 03:40:25+449 [APIC] APIC read icr0 | |
| 03:40:25+449 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:25+449 [APIC] APIC read icr0 | |
| 03:40:25+465 [RTC ] cmos reg C read | |
| Previous message repeated 83 times | |
| 03:40:26+117 [APIC] APIC read icr0 | |
| 03:40:26+117 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+117 [APIC] APIC read icr0 | |
| 03:40:26+118 [APIC] APIC read icr0 | |
| 03:40:26+118 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+118 [APIC] APIC read icr0 | |
| 03:40:26+121 [RTC ] cmos reg C read | |
| 03:40:26+130 [RTC ] cmos reg C read | |
| 03:40:26+130 [APIC] APIC read icr0 | |
| 03:40:26+130 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+130 [APIC] APIC read icr0 | |
| 03:40:26+135 [APIC] APIC read icr0 | |
| 03:40:26+135 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+135 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+136 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+136 [APIC] APIC read icr0 | |
| 03:40:26+137 [APIC] APIC read icr0 | |
| 03:40:26+137 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+137 [APIC] APIC read icr0 | |
| 03:40:26+137 [APIC] APIC read icr0 | |
| 03:40:26+137 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+137 [APIC] APIC read icr0 | |
| 03:40:26+137 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:26+155 [APIC] APIC read icr0 | |
| 03:40:26+155 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+155 [APIC] APIC read icr0 | |
| 03:40:26+155 [APIC] APIC read icr0 | |
| 03:40:26+155 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+155 [APIC] APIC read icr0 | |
| 03:40:26+158 [APIC] APIC read icr0 | |
| 03:40:26+158 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+158 [APIC] APIC read icr0 | |
| 03:40:26+159 [APIC] APIC read icr0 | |
| 03:40:26+159 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+159 [APIC] APIC read icr0 | |
| 03:40:26+168 [RTC ] cmos reg C read | |
| 03:40:26+168 [RTC ] cmos reg C read | |
| 03:40:26+168 [APIC] APIC read icr0 | |
| 03:40:26+169 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+169 [APIC] APIC read icr0 | |
| 03:40:26+170 [APIC] APIC read icr0 | |
| 03:40:26+170 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+170 [APIC] APIC read icr0 | |
| 03:40:26+171 [APIC] APIC read icr0 | |
| 03:40:26+171 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+171 [APIC] APIC read icr0 | |
| 03:40:26+171 [APIC] APIC read icr0 | |
| 03:40:26+171 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+171 [APIC] APIC read icr0 | |
| 03:40:26+183 [RTC ] cmos reg C read | |
| Previous message repeated 71 times | |
| 03:40:26+731 [APIC] APIC read icr0 | |
| 03:40:26+731 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:26+731 [APIC] APIC read icr0 | |
| 03:40:26+746 [RTC ] cmos reg C read | |
| Previous message repeated 199 times | |
| 03:40:28+293 [APIC] APIC read icr0 | |
| 03:40:28+293 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+293 [APIC] APIC read icr0 | |
| 03:40:28+308 [RTC ] cmos reg C read | |
| Previous message repeated 33 times | |
| 03:40:28+565 [APIC] APIC read icr0 | |
| 03:40:28+565 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+565 [APIC] APIC read icr0 | |
| 03:40:28+565 [APIC] APIC read icr0 | |
| 03:40:28+565 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+565 [APIC] APIC read icr0 | |
| 03:40:28+574 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+603 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+603 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+604 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+604 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+605 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+605 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [RTC ] cmos reg C read | |
| 03:40:28+606 [RTC ] cmos reg C read | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+606 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+606 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+607 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:28+607 [APIC] APIC read icr0 | |
| 03:40:28+621 [RTC ] cmos reg C read | |
| Previous message repeated 65 times | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x00 0x80000000 -> 0x12378086 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x04 0x80000004 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x08 0x80000008 -> 0x06000002 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x0C 0x8000000C -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x10 0x80000010 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x14 0x80000014 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x18 0x80000018 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x1C 0x8000001C -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x20 0x80000020 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x24 0x80000024 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x28 0x80000028 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x2C 0x8000002C -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x30 0x80000030 -> 0xFEBF9000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x34 0x80000034 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x38 0x80000038 -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=1 bdf=0x0000 dev=0x00 addr=0x3C 0x8000003C -> 0x00000000 | |
| 03:40:29+125 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x10 0x80000810 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x14 0x80000814 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x18 0x80000818 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x1C 0x8000081C -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x20 0x80000820 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x24 0x80000824 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x28 0x80000828 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x2C 0x8000082C -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x30 0x80000830 -> 0xFEBFA000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x34 0x80000834 -> 0x00000000 | |
| 03:40:29+133 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x38 0x80000838 -> 0x00000000 | |
| 03:40:29+134 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x3C 0x8000083C -> 0x00000000 | |
| 03:40:29+134 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+137 [RTC ] cmos reg C read | |
| 03:40:29+138 [RTC ] cmos reg C read | |
| 03:40:29+138 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+138 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+138 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+138 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+138 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+139 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+139 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+140 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+140 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x00 0x80000800 -> 0x70008086 | |
| 03:40:29+140 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x04 0x80000804 -> 0x02000007 | |
| 03:40:29+140 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x08 0x80000808 -> 0x06010000 | |
| 03:40:29+140 [PCI ] enabled=1 bdf=0x0008 dev=0x01 addr=0x0C 0x8000080C -> 0x00800000 | |
| 03:40:29+140 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 25 times | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x00 0x80002800 -> 0x802910EC | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x04 0x80002804 -> 0x00000103 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x08 0x80002808 -> 0x02000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x0C 0x8000280C -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x10 0x80002810 -> 0x0000C101 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x14 0x80002814 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x18 0x80002818 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x1C 0x8000281C -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x20 0x80002820 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x24 0x80002824 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x28 0x80002828 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x2C 0x8000282C -> 0x11001AF4 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x30 0x80002830 -> 0xFEBFB000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x34 0x80002834 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x38 0x80002838 -> 0x00000000 | |
| 03:40:29+143 [PCI ] enabled=1 bdf=0x0028 dev=0x05 addr=0x3C 0x8000283C -> 0x0000010B | |
| 03:40:29+143 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x00 0x80003000 -> 0x10091AF4 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x04 0x80003004 -> 0x00100507 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x08 0x80003008 -> 0x00020000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x0C 0x8000300C -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x10 0x80003010 -> 0x0000C001 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x14 0x80003014 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x18 0x80003018 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x1C 0x8000301C -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x20 0x80003020 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x24 0x80003024 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x28 0x80003028 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x2C 0x8000302C -> 0x00091AF4 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x30 0x80003030 -> 0xFEBFC000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x34 0x80003034 -> 0x00000040 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x38 0x80003038 -> 0x00000000 | |
| 03:40:29+147 [PCI ] enabled=1 bdf=0x0030 dev=0x06 addr=0x3C 0x8000303C -> 0x0000010C | |
| 03:40:29+147 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x10 0x80003810 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x14 0x80003814 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x18 0x80003818 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x1C 0x8000381C -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x20 0x80003820 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x24 0x80003824 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x28 0x80003828 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x2C 0x8000382C -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x30 0x80003830 -> 0xFEBFD000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x34 0x80003834 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x38 0x80003838 -> 0x00000000 | |
| 03:40:29+151 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x3C 0x8000383C -> 0x00000109 | |
| 03:40:29+151 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+152 [RTC ] cmos reg C read | |
| 03:40:29+156 [RTC ] cmos reg C read | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+156 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+156 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+157 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+157 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+157 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x00 0x80003800 -> 0x71138086 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x04 0x80003804 -> 0x02800007 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x08 0x80003808 -> 0x06800008 | |
| 03:40:29+157 [PCI ] enabled=1 bdf=0x0038 dev=0x07 addr=0x0C 0x8000380C -> 0x00800000 | |
| 03:40:29+157 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 81 times | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x10 0x80009010 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x14 0x80009014 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x18 0x80009018 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x1C 0x8000901C -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x20 0x80009020 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x24 0x80009024 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x28 0x80009028 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x2C 0x8000902C -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x30 0x80009030 -> 0xFEBFE000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x34 0x80009034 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x38 0x80009038 -> 0x00000000 | |
| 03:40:29+164 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x3C 0x8000903C -> 0x0000010A | |
| 03:40:29+164 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+168 [RTC ] cmos reg C read | |
| 03:40:29+168 [RTC ] cmos reg C read | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+168 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+168 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+168 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x00 0x80009000 -> 0x0A2010DE | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x04 0x80009004 -> 0x00000007 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x08 0x80009008 -> 0x030000A2 | |
| 03:40:29+169 [PCI ] enabled=1 bdf=0x0090 dev=0x12 addr=0x0C 0x8000900C -> 0x00800000 | |
| 03:40:29+170 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 89 times | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x00 0x8000F000 -> 0x3A208086 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x04 0x8000F004 -> 0x02A00005 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x08 0x8000F008 -> 0x01018F00 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x0C 0x8000F00C -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x10 0x8000F010 -> 0x000001F1 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x14 0x8000F014 -> 0x000003F5 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x18 0x8000F018 -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x1C 0x8000F01C -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x20 0x8000F020 -> 0x0000C121 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x24 0x8000F024 -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x28 0x8000F028 -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x2C 0x8000F02C -> 0x82D41043 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x30 0x8000F030 -> 0xFEBFF000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x34 0x8000F034 -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x38 0x8000F038 -> 0x00000000 | |
| 03:40:29+178 [PCI ] enabled=1 bdf=0x00F0 dev=0x1E addr=0x3C 0x8000F03C -> 0x0000010E | |
| 03:40:29+178 [PCI ] enabled=0 bdf=0x0000 dev=0x00 addr=0x00 0x00000000 -> 0x12378086 | |
| Previous message repeated 8 times | |
| 03:40:29+184 [RTC ] cmos reg C read | |
| Previous message repeated 9 times | |
| 03:40:29+259 [APIC] APIC read icr0 | |
| 03:40:29+259 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+259 [APIC] APIC read icr0 | |
| 03:40:29+259 [APIC] APIC read icr0 | |
| 03:40:29+259 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+259 [APIC] APIC read icr0 | |
| 03:40:29+261 [APIC] APIC read icr0 | |
| 03:40:29+261 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+261 [APIC] APIC read icr0 | |
| 03:40:29+263 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:29+281 [APIC] APIC read icr0 | |
| 03:40:29+281 [APIC] APIC write icr0: 0x0004003D vector=0x3D destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+281 [APIC] APIC read icr0 | |
| 03:40:29+293 [RTC ] cmos reg C read | |
| Previous message repeated 5 times | |
| 03:40:29+337 [IO ] read8 port #0xAFE0 | |
| 03:40:29+337 [IO ] write8 port #0xAFE0 <- 0x00 | |
| 03:40:29+337 [IO ] read8 port #0xAFE1 | |
| 03:40:29+337 [IO ] write8 port #0xAFE1 <- 0x00 | |
| 03:40:29+337 [IO ] write8 port #0xAFE2 <- 0x00 | |
| 03:40:29+337 [IO ] write8 port #0xAFE3 <- 0x00 | |
| 03:40:29+340 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:29+391 [ACPI] ACPI status read | |
| 03:40:29+391 [IO ] read16 port #0xB000 (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] write16 port #0xB000 <- 0xFFFF (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] read16 port #0xB000 (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] read16 port #0xB000 (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] write16 port #0xB000 <- 0xFFFF (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] read16 port #0xB000 (PORT_ACPI_PM_BASE) | |
| 03:40:29+392 [IO ] write16 port #0xB002 <- 0x0121 | |
| 03:40:29+392 [ACPI] ACPI status read | |
| 03:40:29+392 [IO ] write16 port #0xB004 <- 0x0001 | |
| 03:40:29+395 [IO ] write8 port #0xAFE2 <- 0x00 | |
| 03:40:29+395 [IO ] write8 port #0xAFE3 <- 0x00 | |
| 03:40:29+395 [IO ] read8 port #0xAFE0 | |
| 03:40:29+395 [IO ] write8 port #0xAFE0 <- 0x00 | |
| 03:40:29+395 [IO ] read8 port #0xAFE1 | |
| 03:40:29+395 [IO ] write8 port #0xAFE1 <- 0x00 | |
| 03:40:29+403 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:29+419 [APIC] APIC read icr0 | |
| 03:40:29+419 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+419 [APIC] APIC read icr0 | |
| 03:40:29+434 [RTC ] cmos reg C read | |
| Previous message repeated 7 times | |
| 03:40:29+482 [IO ] write8 port #0xAFE2 <- 0xFF | |
| 03:40:29+482 [IO ] write8 port #0xAFE3 <- 0xFF | |
| 03:40:29+483 [APIC] APIC read icr0 | |
| 03:40:29+483 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+483 [APIC] APIC read icr0 | |
| 03:40:29+496 [RTC ] cmos reg C read | |
| 03:40:29+498 [RTC ] cmos reg C read | |
| 03:40:29+498 [IO ] write8 port #0xAFE2 <- 0x00 | |
| 03:40:29+498 [IO ] write8 port #0xAFE3 <- 0x00 | |
| 03:40:29+498 [IO ] read8 port #0xAFE0 | |
| 03:40:29+498 [IO ] write8 port #0xAFE0 <- 0xFF | |
| 03:40:29+498 [IO ] read8 port #0xAFE1 | |
| 03:40:29+498 [IO ] write8 port #0xAFE1 <- 0xFF | |
| 03:40:29+512 [RTC ] cmos reg C read | |
| 03:40:29+512 [RTC ] cmos reg C read | |
| 03:40:29+512 [APIC] APIC read icr0 | |
| 03:40:29+512 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+512 [APIC] APIC read icr0 | |
| 03:40:29+527 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:29+543 [APIC] APIC read icr0 | |
| 03:40:29+543 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+543 [APIC] APIC read icr0 | |
| 03:40:29+547 [IO ] write8 port #0xAFE2 <- 0xFF | |
| 03:40:29+547 [IO ] write8 port #0xAFE3 <- 0xFF | |
| 03:40:29+548 [APIC] APIC read icr0 | |
| 03:40:29+548 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+548 [APIC] APIC read icr0 | |
| 03:40:29+558 [RTC ] cmos reg C read | |
| Previous message repeated 3 times | |
| 03:40:29+574 [APIC] APIC read icr0 | |
| 03:40:29+574 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:29+574 [APIC] APIC read icr0 | |
| 03:40:29+579 [APIC] IOAPIC write 0x23 <- 0x01000000 | |
| 03:40:29+579 [APIC] Write destination 0x01000000 irq=0x9 dest=0x01 | |
| 03:40:29+579 [APIC] IOAPIC write 0x22 <- 0x000089B1 | |
| 03:40:29+579 [APIC] Write config 0x000089B1 irq=0x9 vector=0xB1 delivery=0x1 destmode=1 is_level=1 disabled=0 | |
| 03:40:29+590 [RTC ] cmos reg C read | |
| Previous message repeated 67 times | |
| 03:40:30+105 [APIC] APIC read icr0 | |
| 03:40:30+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:30+105 [APIC] APIC read icr0 | |
| 03:40:30+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:31+105 [APIC] APIC read icr0 | |
| 03:40:31+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:31+105 [APIC] APIC read icr0 | |
| 03:40:31+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:32+105 [APIC] APIC read icr0 | |
| 03:40:32+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:32+105 [APIC] APIC read icr0 | |
| 03:40:32+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:33+105 [APIC] APIC read icr0 | |
| 03:40:33+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:33+105 [APIC] APIC read icr0 | |
| 03:40:33+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:34+105 [APIC] APIC read icr0 | |
| 03:40:34+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:34+105 [APIC] APIC read icr0 | |
| 03:40:34+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:35+105 [APIC] APIC read icr0 | |
| 03:40:35+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:35+105 [APIC] APIC read icr0 | |
| 03:40:35+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:36+105 [APIC] APIC read icr0 | |
| 03:40:36+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:36+105 [APIC] APIC read icr0 | |
| 03:40:36+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:37+105 [APIC] APIC read icr0 | |
| 03:40:37+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:37+105 [APIC] APIC read icr0 | |
| 03:40:37+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:38+105 [APIC] APIC read icr0 | |
| 03:40:38+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:38+105 [APIC] APIC read icr0 | |
| 03:40:38+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:39+105 [APIC] APIC read icr0 | |
| 03:40:39+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:39+105 [APIC] APIC read icr0 | |
| 03:40:39+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:40+105 [APIC] APIC read icr0 | |
| 03:40:40+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:40+105 [APIC] APIC read icr0 | |
| 03:40:40+121 [RTC ] cmos reg C read | |
| Previous message repeated 127 times | |
| 03:40:41+105 [APIC] APIC read icr0 | |
| 03:40:41+105 [APIC] APIC write icr0: 0x00040041 vector=0x41 destination_mode=0 delivery_mode=0 destination_shorthand=self | |
| 03:40:41+105 [APIC] APIC read icr0 | |
| 03:40:41+121 [RTC ] cmos reg C read |
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