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Make is intelligent enough to generate compile rules on its own!!!
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| CFLAGS := -Wall -m32 -march=i386 -g -Iinclude1 -Iinclude2 | |
| LDFLAGS := -Llibrary-dir1 -Llibrary-dir2 | |
| FIRST_BINARY_SRC := FirstBinary.c | |
| FIRST_BINARY_OBJ := $(FIRST_BINARY_SRC:.c=.o) | |
| FIRST_BINARY := FirstBinary | |
| SECOND_BINARY_SRC := SecondBinary.c | |
| SECOND_BINARY_OBJS := $(SECOND_BINARY_SRC:.c=.o) | |
| SECOND_BINARY := SecondBinary | |
| THIRD_BINARY_SRC := ThirdBinary | |
| THIRD_BINARY_OBJS := $(THIRD_BINARY_SRC:.c=.o) | |
| THIRD_BINARY := ThirdBinary | |
| VPATH = include1 include2 src | |
| all: $(FIRST_BINARY) $(SECOND_BINARY) \ | |
| $(THIRD_BINARY) | |
| clean: | |
| rm -rf $(FIRST_BINARY) $(SECOND_BINARY) $(THIRD_BINARY) *.o |
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I was trying the above Makefile to compile some small C programs into binaries. Of course this is dummy make file not exact one which I was using for reasons. If you can see I've not written any rule to comppile the binaries, I only have decalred source objects and binary files. To my surprise when I ran make all binaries got compiled make generated following command
cc$(CFLAGS) $ (LDFLAGS) -o $@ $ <
And I'm dumb founded! how did this happen?