gistfile1.diff

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 9f493b9..48551db 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -821,11 +821,11 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   OpIdx = 0;

   // BX_RET has only two predicate operands, do an early return.
-  if (Opcode == ARM::BX_RET)
+  if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
     return true;

   // BLXr9 and BRIND take one GPR reg.
-  if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
+  if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND || Opcode == ARM::MOVPCRX) {
     assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
            "Reg operand expected");
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,