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cstrahan/gist:219a93abafc4c1abc96f599643daa4cc

Created October 9, 2022 16:25
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probe-rs with teensy
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gistfile1.txt
$ RUST_LOG=debug,probe_rs::probe=info ../target/release/probe-rs-cli download --disable-progressbars --chip MIMXRT1060 --protocol jtag ~/src/hello-teensy/target/thumbv7em-none-eabihf/debug/hello-teensy
DEBUG probe_rs::config::registry > Searching registry for chip with name MIMXRT1060
DEBUG probe_rs::config::registry > Exact match for chip name: MIMXRT1060
WARN probe_rs::config::target > Using custom sequence for MIMXRT10xx
DEBUG jaylink > libusb 1.0.25.11696
DEBUG jaylink > libusb has capability API: true
DEBUG jaylink > libusb has HID access: true
DEBUG jaylink > libusb has hotplug support: true
DEBUG jaylink > libusb can detach kernel driver: true
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0x0,
bDeviceSubClass: 0x0,
bDeviceProtocol: 0x0,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x101,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 1 interfaces
DEBUG jaylink > J-Link interface is #0
DEBUG jaylink > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0x0,
bDeviceSubClass: 0x0,
bDeviceProtocol: 0x0,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x101,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 1 interfaces
DEBUG jaylink > J-Link interface is #0
DEBUG jaylink > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
INFO probe_rs::probe::jlink > J-Link: S/N: 50122644
INFO probe_rs::probe::jlink > J-Link: Firmware version: J-Link V10 compiled Sep 22 2022 14:59:36
INFO probe_rs::probe::jlink > J-Link: Hardware version: J-Link 10.10.0
INFO probe_rs::probe::jlink > J-Link: Target voltage: 3.32 V
INFO probe_rs::probe::jlink > JTAG IDCODE: 0x0ba02477
DEBUG probe_rs::architecture::arm::communication_interface > Selecting DP Default
DEBUG probe_rs::architecture::arm::dp > Writing DP register ABORT, value=0x0000001e
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0x00000000
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0x50000000
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf0000000
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0x50000f00
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf0000000
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf0000000
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0xf0000001
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x4770041
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x4770041
DEBUG probe_rs::architecture::arm::ap > Reading register BASE
DEBUG probe_rs::architecture::arm::ap > Read register BASE, value=0xe00fd003
DEBUG probe_rs::architecture::arm::ap > Reading register BASE2
DEBUG probe_rs::architecture::arm::ap > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x3000042
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x3000050
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 0, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Off, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: false
DEBUG probe_rs::architecture::arm::ap > Reading register CFG
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::architecture::arm::ap > Read register CFG, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > AP GenericAp { address: ApAddress { dp: Default, ap: 0 } }: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 0 }, only_32bit_data_size: false, debug_base_address: 3759132672, supports_hnonsec: false, has_large_address_extension: false, has_large_data_extension: false })
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x1010000
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: a05f0001 }
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10001
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 1f }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ef40 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10110221
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002008 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000200c }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002010 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002014 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002018 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000201c }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002020 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002024 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x60000000, virtual address: 0x60000000, flags: 0x5
INFO probe_rs::flashing::download > Matching section: ".boot"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x60001400, virtual address: 0x60001400, flags: 0x4
INFO probe_rs::flashing::download > Matching section: ".vector_table"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x600016b8, virtual address: 0x00000000, flags: 0x5
INFO probe_rs::flashing::download > Matching section: ".text"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x6000a400, virtual address: 0x20000000, flags: 0x6
INFO probe_rs::flashing::download > Matching section: ".data"
INFO probe_rs::flashing::loader > Found 4 loadable sections:
INFO probe_rs::flashing::loader > .boot at 60000000 (4246 bytes)
INFO probe_rs::flashing::loader > .vector_table at 60001400 (696 bytes)
INFO probe_rs::flashing::loader > .text at 600016B8 (36084 bytes)
INFO probe_rs::flashing::loader > .data at 6000A400 (5816 bytes)
DEBUG probe_rs::flashing::loader > committing FlashLoader!
DEBUG probe_rs::flashing::loader > Contents of builder:
DEBUG probe_rs::flashing::loader > data: 60000000-60001096 (4246 bytes)
DEBUG probe_rs::flashing::loader > data: 60001400-6000a3ac (36780 bytes)
DEBUG probe_rs::flashing::loader > data: 6000a400-6000bab8 (5816 bytes)
DEBUG probe_rs::flashing::loader > Flash algorithms:
DEBUG probe_rs::flashing::loader > algo mimxrt106x_qspi_4kb_sec: 60000000-60800000 (8388608 bytes)
DEBUG probe_rs::flashing::loader > Regions:
DEBUG probe_rs::flashing::loader > region: 60000000-60800000 (8388608 bytes)
DEBUG probe_rs::flashing::loader > -- using algorithm: mimxrt106x_qspi_4kb_sec
DEBUG probe_rs::flashing::loader > Flashing ranges for algo: mimxrt106x_qspi_4kb_sec
INFO probe_rs::flashing::flasher > chosen RAM to run the algo: RamRegion { name: Some("OCRAM2"), range: 20200000..202c0000, is_boot_memory: false, cores: ["main"] }
DEBUG probe_rs::flashing::flasher > Initializing the flash algorithm.
DEBUG probe_rs::flashing::flasher > Halting core 0
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: a05f0003 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x30003
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x30003
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x1
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 1f }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x30003
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 1f }
DEBUG probe_rs::architecture::arm::core::armv7m > Cached halt reason: Halted(Request)
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf4 }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: f }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x30003
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf8 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x130
DEBUG probe_rs::flashing::flasher > PC = 0x00000130
DEBUG probe_rs::flashing::flasher > Reset and halt
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edfc }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edfc }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 1 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x30003
WARN probe_rs::architecture::arm::sequences::nxp > MIMXRT10xx core type supplied as Armv7m, but the actual core is a Armv7em
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000ed0c }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 5fa0004 }
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
ERROR probe_rs::probe::jlink::arm > Unexpected DAP response: 0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002008 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000200c }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002010 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002014 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002018 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000201c }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002020 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x10000080
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e0002024 }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edfc }
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x1
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edfc }
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: 1 }
Error: The flashing procedure failed for '/home/cstrahan/src/hello-teensy/target/thumbv7em-none-eabihf/debug/hello-teensy'.
Caused by:
0: Something during the interaction with the core went wrong
1: A core architecture specific error occurred
2: Failed to write register TAR at address 0x00000004
3: An error specific to the selected architecture occurred
4: Target device responded with a FAULT response to the request.
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