Reset with default debug sequence

gistfile1.txt

 DEBUG probe_rs::config::registry > Searching registry for chip with name MIMXRT1060
 DEBUG probe_rs::config::registry > Exact match for chip name: MIMXRT1060
 WARN  probe_rs::config::target   > Using custom sequence for MIMXRT10xx
 DEBUG jaylink                    > libusb 1.0.25.11696
 DEBUG jaylink                    > libusb has capability API: true
 DEBUG jaylink                    > libusb has HID access: true
 DEBUG jaylink                    > libusb has hotplug support: true
 DEBUG jaylink                    > libusb can detach kernel driver: true
 DEBUG jaylink                    > open_usb: device descriptor: DeviceDescriptor {
    bLength: 0x12,
    bDescriptorType: 0x1,
    bcdUSB: 0x200,
    bDeviceClass: 0x0,
    bDeviceSubClass: 0x0,
    bDeviceProtocol: 0x0,
    bMaxPacketSize: 0x40,
    idVendor: 0x1366,
    idProduct: 0x101,
    bcdDevice: 0x100,
    iManufacturer: 0x1,
    iProduct: 0x2,
    iSerialNumber: 0x3,
    bNumConfigurations: 0x1,
}
 DEBUG jaylink                    > scanning 1 interfaces
 DEBUG jaylink                    > J-Link interface is #0
 DEBUG jaylink                    > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
 DEBUG jaylink::capabilities      > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
 DEBUG jaylink                    > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
 DEBUG jaylink                    > open_usb: device descriptor: DeviceDescriptor {
    bLength: 0x12,
    bDescriptorType: 0x1,
    bcdUSB: 0x200,
    bDeviceClass: 0x0,
    bDeviceSubClass: 0x0,
    bDeviceProtocol: 0x0,
    bMaxPacketSize: 0x40,
    idVendor: 0x1366,
    idProduct: 0x101,
    bcdDevice: 0x100,
    iManufacturer: 0x1,
    iProduct: 0x2,
    iSerialNumber: 0x3,
    bNumConfigurations: 0x1,
}
 DEBUG jaylink                    > scanning 1 interfaces
 DEBUG jaylink                    > J-Link interface is #0
 DEBUG jaylink                    > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
 DEBUG jaylink::capabilities      > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
 DEBUG jaylink                    > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
 INFO  probe_rs::probe::jlink     > J-Link: S/N: 50122644
 INFO  probe_rs::probe::jlink     > J-Link: Firmware version: J-Link V10 compiled Sep 22 2022 14:59:36
 INFO  probe_rs::probe::jlink     > J-Link: Hardware version: J-Link 10.10.0
 INFO  probe_rs::probe::jlink     > J-Link: Target voltage: 3.31 V
 INFO  probe_rs::probe::jlink     > JTAG IDCODE: 0x0ba02477
 DEBUG probe_rs::architecture::arm::communication_interface > Selecting DP Default
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register ABORT, value=0x0000001e
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x00000000
 DEBUG probe_rs::architecture::arm::dp                      > Reading DP register CTRL/STAT
 DEBUG probe_rs::architecture::arm::dp                      > Read    DP register CTRL/STAT, value=0xf0000001
 DEBUG probe_rs::architecture::arm::dp                      > Reading DP register CTRL/STAT
 DEBUG probe_rs::architecture::arm::dp                      > Read    DP register CTRL/STAT, value=0xf0000001
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register CTRL/STAT, value=0xf0000001
 DEBUG probe_rs::architecture::arm::ap                      > Reading register IDR
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x000000f0
 DEBUG probe_rs::architecture::arm::ap                      > Read register    IDR, value=0x4770041
 DEBUG probe_rs::architecture::arm::ap                      > Reading register IDR
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x010000f0
 DEBUG probe_rs::architecture::arm::ap                      > Read register    IDR, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Reading register IDR
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x000000f0
 DEBUG probe_rs::architecture::arm::ap                      > Read register    IDR, value=0x4770041
 DEBUG probe_rs::architecture::arm::ap                      > Reading register BASE
 DEBUG probe_rs::architecture::arm::ap                      > Read register    BASE, value=0xe00fd003
 DEBUG probe_rs::architecture::arm::ap                      > Reading register BASE2
 DEBUG probe_rs::architecture::arm::ap                      > Read register    BASE2, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Reading register CSW
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x00000000
 DEBUG probe_rs::architecture::arm::ap                      > Read register    CSW, value=0x3000052
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register CSW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    CSW, value=0x3000050
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 0, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Single, _RES1: 0, SIZE: U32 }
 DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: false
 DEBUG probe_rs::architecture::arm::ap                      > Reading register CFG
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x000000f0
 DEBUG probe_rs::architecture::arm::ap                      > Read register    CFG, value=0x0
 DEBUG probe_rs::architecture::arm::communication_interface > AP GenericAp { address: ApAddress { dp: Default, ap: 0 } }: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 0 }, only_32bit_data_size: false, debug_base_address: 3759132672, supports_hnonsec: false, has_large_address_extension: false, has_large_data_extension: false })
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
 DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
 DEBUG probe_rs::architecture::arm::dp                      > Writing DP register SELECT, value=0x00000000
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000edf0 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x2030003
 DEBUG probe_rs::architecture::arm::sequences               > Core is already in debug mode, no need to enable it again
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000edf0 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x30003
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000ed30 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x8
 DEBUG probe_rs::architecture::arm::core::armv7m            > Core was halted when connecting, reason: Exception
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000ed30 }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register DRW, value=DRW { data: 1f }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000ef40 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10110221
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002008 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000200c }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002010 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002014 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002018 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000201c }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002020 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002000 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x10000080
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e0002024 }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000ed0c }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register DRW, value=DRW { data: 5fa0004 }
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 ERROR probe_rs::probe::jlink::arm                          > Unexpected DAP response: 0
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
 WARN  probe_rs::session                                    > Could not clear all hardware breakpoints: ArchitectureSpecific(RegisterWrite { address: 0, name: "CSW", source: ArchitectureSpecific(FaultResponse) })
 DEBUG probe_rs::architecture::arm::ap                      > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000edfc }
 DEBUG probe_rs::architecture::arm::ap                      > Reading register DRW
 DEBUG probe_rs::architecture::arm::ap                      > Read register    DRW, value=0x1
 DEBUG probe_rs::architecture::arm::ap                      > Writing register TAR, value=TAR { address: e000edfc }
 DEBUG probe_rs::architecture::arm::ap                      > Writing register DRW, value=DRW { data: 1 }
Error: A core architecture specific error occurred

Caused by:
    0: Failed to write register DRW at address 0x0000000c
    1: An error specific to the selected architecture occurred
    2: Target device did not respond to request.