ARM PMU

gistfile1.txt

Orange Pi 5+ (DTS)

• arch/arm64/mm/proc.S

Comment on the disablement of PMU and AMU

#ifdef CONFIG_CPU_PM

SYM_FUNC_START(cpu_do_resume)

/*	reset_pmuserenr_el0 x0			** Disable PMU access from EL0 */
/*	reset_amuserenr_el0 x0			** Disable AMU access from EL0 */

	isb
	ret
SYM_FUNC_END(cpu_do_resume)
#endif

• arch/arm64/include/asm/assembler.h

	.macro	reset_pmuserenr_el0, tmpreg
	mrs	\tmpreg, id_aa64dfr0_el1
	sbfx	\tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
	cmp	\tmpreg, #1			// Skip if no PMU present
	b.lt	9000f
	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
9000:
	.endm

	.macro	reset_amuserenr_el0, tmpreg
	mrs	\tmpreg, id_aa64pfr0_el1	// Check ID_AA64PFR0_EL1
	ubfx	\tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
	cbz	\tmpreg, .Lskip_\@		// Skip if no AMU present
	msr_s	SYS_AMUSERENR_EL0, xzr		// Disable AMU access from EL0
.Lskip_\@:
	.endm

• Disable CONFIG_ARM_PMUV3 w/ kernel 6
• Disable CONFIG_ARM_PMU w/ kernel 5
• Disable CONFIG_PERF_EVENTS
• Disable CONFIG_KVM
• drivers/perf/arm_pmuv3.c

static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
{
	armv8pmu_stop(cpu_pmu);

	armv8pmu_start(cpu_pmu);

	return IRQ_HANDLED;
}

armv8pmu_stop() -> armv8pmu_pmcr_write() -> write_pmcr() -> write_sysreg() -> __write_sysreg() -> pmcr_el0