Xeon W3690 [Gulftown]

gistfile1.txt

CoreFreq updated to version 1.93.0

Performance

Turbo Single Core

Turbo all Cores

Overclocking

Energy Policy

Clock Modulation

Performance Target

Uncore

Memory Controller

System

Tasks

Tracking

Big Screen

System Information

Processor                                 [Intel(R) Xeon(R) CPU W3690 @ 3.47GHz]
|- Architecture                                              [Westmere/Gulftown]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000001f]
|- Signature                                                           [  06_2C]
|- Stepping                                                            [      2]
|- Online CPU                                                          [ 12/ 12]
|- Base Clock                                                          [133.505]
|- Frequency            (MHz)                      Ratio                        
                 Min   1602.07                    <  12 >                       
                 Max   3471.14                    <  26 >                       
|- Factory                                                             [133.333]
                       3470                       [  26 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   3604.65                    <  27 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   4005.16                    <  30 >                       
                  2C   3738.15                    <  28 >                       
                  3C   3604.65                    <  27 >                       
                  4C   3604.65                    <  27 >                       
                  5C   3604.65                    <  27 >                       
                  6C   3604.65                    <  27 >                       
|- Uncore                                                              [   LOCK]
                 Min   2670.11                    [  20 ]                       
                 Max   2670.11                    [  20 ]                       
|- TDP                                                           Level [  0:0  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [   LOCK]
               Turbo      AUTO                    [   0 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [N]          AES [Y]  AVX/AVX2 [N/N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]      MOVDIRI [N]   MOVDIR64B [N] 
|- BMI1/BMI2  [N/N]         CLWB [N]      CLFLUSH [Y] CLFLUSH-OPT [N] 
|- CLAC-STAC    [N]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [N]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [N]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [N]       RDSEED [N]      RDTSCP [Y] 
|- SEP          [Y]          SHA [N]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [N]         SGX [N] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Capable]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast Short REP STOSB                                         FSRS   [Missing]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Missing]
|- Fused Multiply Add                                     FMA | FMA4   [Missing]
|- Hardware Feedback Interface                                   HFI   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Missing]
|- Hybrid part processor                                      HYBRID   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Missing]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Missing]
|- Supervisor-Mode Execution Prevention                         SMEP   [Missing]
|- Thread Director                                                TD   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [Missing]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Missing]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [Missing]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Missing]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [Missing]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [Missing]
|- Arch - Return Stack Buffer Alternate                         RSBA   [Missing]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Missing]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [Missing]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [Missing]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [Missing]
|- Arch - STLB QoS                                              STLB   [Missing]
|- Arch - Functional Safety Island                              FuSa   [Missing]
|- Arch - RSM in CPL0 only                                       RSM   [Missing]
|- Arch - Split Locked Access Exception                         SPLA   [Missing]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [Missing]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Missing]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [Missing]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [Missing]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [Missing]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [Missing]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Missing]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [Missing]
   |- RDRAND and RDSEED mitigation                             RNGDS   [Missing]
   |- Restricted Transactional Memory                            RTM   [Missing]
   |- Verify Segment for Writing instruction                    VERW   [Missing]
|- Arch - Restricted RSB Alternate                             RRSBA   [Missing]
|- Arch - No Branch Target Injection                          BHI_NO   [Missing]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [Missing]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Missing]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [Missing]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [Missing]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [Missing]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [Missing]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [Missing]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   < ON>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         1.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  3]
|- Counters:          General                   Fixed                           
|           {  4,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       < ON>
|- C1 UnDemotion                                                 C1U       <OFF>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       [OFF]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   < Enable>
   |- Max C-State Inclusion                                    RANGE   <     C7>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x814 ]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     1     1     0     0     0     0              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:101 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [ UNLOCK]
   |- Energy Policy                                        Bias Hint   <      3>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   <Disable>
   |- Power Limit                                                PL1   <  130 W>
   |- Time Window                                                TW1   < 976 us>
   |- Power Limit                                                PL2   <    0 W>
   |- Time Window                                                TW2   < 976 us>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [ 976 us]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   <  110 A>
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [      Missing]
   |- Window                                            second   [  0.000976562]

Processor Events

Idle States CoreFreq sub-drivers

echo "corefreq" > /sys/bus/clocksource/devices/clocksource0/current_clocksource; \
insmod corefreqk.ko RDPMC_Enable=1 Register_ClockSource=1 Register_Governor=1 Register_CPU_Freq=1 Register_CPU_Idle=1 Idle_Route=3 NMI_Disable=1; \
./corefreqd -d

MWAIT

I/O Wait

HALT