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Signal Description Backplane Used in Variants known
AF20 Console selector → L3 D18·13 msl-states → AF20,AF21
AF30 Console selector → V3 C22·02 msl-states + defined → AF30,AF31,AF32
AF40 Console selector → R1/L2 C22·04 msl-states + defined → AF40,AF41,AF42,AF43
AF50 Console selector → V2 C22·09 msl-states + defined → AF50,AF51,AF52,AF53
CI451 UA logic-operation select (CI45) signals.h → CI451,CI45D
CI461 UA decimal/AND select (CI46) signals.h → CI461,CI46B
CI471 UA subtract/XOR select (CI47) signals.h → CI471,CI47B
CM011 CU01 partial command (any class claims) A9·15 signals.h + defined → CM011,CM01A,CM01A0
DA25A State+function DA25 inverted F21·07 signals.h + defined → DA25A,DA25A0
DE001 Function+state AND: jumps+JRT active A22·14 signals.h + defined → DE001,DE00A,DE00A0
DE07A Function+state AND: decode07+beta inverted A2·06 signals.h + defined → DE07A,DE07A0
DE231 State decode 23 active B15·04 signals.h → DE231,DE23A
DI011 State decode 01 active signals.h → DI011,DI01A
DI021 State decode 02 active signals.h → DI021,DI02A
DI031 State decode 03 active signals.h → DI031,DI03A
DI061 State decode 06 active (fan-out) signals.h → DI061,DI062,DI06A
DI101 State decode 10 active signals.h → DI101,DI10A
DI111 State decode 11 active signals.h + defined → DI111,DI11A,DI11A0
DI121 State decode 12 active signals.h + defined → DI121,DI12A,DI12A0
DI13A State decode ED/EC/EF/EE (indexing) signals.h + defined → DI13A,DI13A0
DI141 State decode 14 active signals.h → DI141,DI14A
DI151 State decode 15 active signals.h → DI151,DI15A
DI17A State decode 17 inverted signals.h + defined → DI17A,DI17A0
DI181 State decode E5 active signals.h + defined → DI181,DI18A,DI18A0,DI18B,DI18B0
DI19A State decode inverted (from DI121) signals.h + defined → DI19A,DI19A0
DI201 State decode E6/E7 active signals.h + defined → DI201,DI20A,DI20A0
DI211 State decode 21 active signals.h + defined → DI211,DI21A,DI21A0
DI22A State decode 22 inverted signals.h + defined → DI22A,DI22A0
DI231 State decode 23 active signals.h → DI231,DI23A
DI24A State decode 24 inverted (from DI231) signals.h + defined → DI24A,DI24A0
DI25A State decode 25 inverted (F0/F1) signals.h + defined → DI25A,DI25A0
DI271 State decode 27 active signals.h → DI271,DI27A
DI281 State decode 28 active signals.h + defined → DI281,DI28A,DI28A0,DI28B,DI28B0
DI291 State decode 29 active signals.h + defined → DI291,DI29A,DI29A0
DI481 State decode 48 active signals.h → DI481,DI48A
DI572 State decode 57 active signals.h + defined → DI572,DI57A,DI57A0,DI57B,DI57B0
DI581 State decode 58 active signals.h → DI581,DI58A
DI60A State decode E4-E7 band inverted signals.h + defined → DI60A,DI60A0
DI64A State decode E7-only inverted signals.h + defined → DI64A,DI64A0
DI65A State decode ED/EC-only inverted signals.h + defined → DI65A,DI65A0
DI66A State decode EF/EE inverted signals.h + defined → DI66A,DI66A0
DI67A State decode EF/EE 1st-op inverted signals.h + defined → DI67A,DI67A0
DI691 State decode 69 active signals.h → DI691,DI69A
DI79A State decode 79 inverted (A7/AE) signals.h + defined → DI79A,DI79A0
DI82A State decode E9/EB inverted signals.h + defined → DI82A,DI82A0
DI83A State decode EA stub (ch.239 missing) signals.h + defined → DI83A,DI83A0
DI84A State decode 84 inverted signals.h + defined → DI84A,DI84A0
DI85A State decode 85 inverted signals.h + defined → DI85A,DI85A0
DI86A State decode 86 inverted signals.h + defined → DI86A,DI86A0
DI87A State decode 87 inverted signals.h + defined → DI87A,DI87A0
DI91A State decode 91 inverted signals.h + defined → DI91A,DI91A0
DI931 State decode C0 active signals.h + defined → DI931,DI93A,DI93A0
DI94A State decode C1 inverted signals.h + defined → DI94A,DI94A0
DI95A State decode C2 inverted signals.h + defined → DI95A,DI95A0
DI971 State decode B0 active signals.h + defined → DI971,DI97A,DI97A0
DO001 Function class 00 (console/control codes) signals.h → DO001,DO00A
DO011 Function class: jump (JC/JU/JCC/JRT) msl-states + signals.h → DO011,DO01A
DO021 Function class: LA (load-address) signals.h → DO021,DO02A
DO041 Function decode 04 active signals.h → DO041,DO04A
DO061 Function class 06 (LPSR only) B19·06 signals.h → DO061,DO06A
DO071 Function decode 07 active signals.h → DO071,DO07A
DU92 Selected channel busy D24·11 msl-states → DU92,DU93,DU95,DU96,DU97,DU98
EC56A DI201+L207 inverted (modified-addr) A37·15 signals.h + defined → EC56A,EC56A0
EC69A AF41+DI572 (SCR select) D9·01 signals.h + defined → EC69A,EC69A0
EC70A AF51+DI572 (LETT select) D21·15 signals.h + defined → EC70A,EC70A0
ED70A not-AINI+DI971 (B0 state entry) E24·09 signals.h + defined → ED70A,ED70A0
ED75A AINI+DI011+DI291 (F0/F1 load entry) D33·06 signals.h + defined → ED75A,ED75A0
ED79A DI291+DU161+SA00 decode F37·02 signals.h + defined → ED79A,ED79A0
ED91A DE231+DU201 decode B12·12 signals.h + defined → ED91A,ED91A0
FUL2 FUL26 alias D8·14 ge → FUL2,FUL26
FUL3 FUL36 alias D8·15 ge → FUL3,FUL36
FUL4 FUL4F alias B8·16 ge + defined → FUL4,FUL4F,FUL4G
PB061 Connector-name storage L106 (ch 1) signals.h → PB061,PB06A
PB071 Connector-name storage L107 (ch 1) signals.h → PB071,PB07A
PB261 Connector-name storage L106 (ch 2) signals.h → PB261,PB26A
PB361 Connector-name storage L106 (ch 3) signals.h → PB361,PB36A
PB371 Connector-name storage L107 (ch 3) signals.h → PB371,PB37A
PC011 Channel-1 selected msl-commands,msl-states + signals.h → PC011,PC01A
PC031 Channel-3 selected msl-commands,msl-states + signals.h → PC031,PC03A
PC111 Connector-1 selected (channel 1) G8·14 msl-states + signals.h → PC111,PC11A
PC121 Connector-2 selected (reader, ch 1) G9·05 msl-commands,msl-states,printer + signals.h → PC121,PC12A
PC131 Connector-3 selected (channel 1) G8·09 connector34,msl-commands + signals.h → PC131,PC13A
PC141 Connector-4 selected (channel 1) I9·13 connector34,msl-commands + signals.h → PC141,PC14A
PC211 Connector-1 selected (printer, ch 2) G9·14 msl-states + signals.h → PC211,PC21A
PC221 Connector-2 selected (reader, ch 2) H9·09 signals.h → PC221,PC22A
PC321 Connector-2 selected (channel 3) H8·12 signals.h → PC321,PC32A
PC331 Connector-3 selected (channel 3) G10·04 signals.h → PC331,PC33A
PC341 Connector-4 selected (channel 3) I9·16 signals.h → PC341,PC34A
PIB11 Printer photodisc input into NE signals.h → PIB11,PIB1A
PIM11 Selection reset enable active signals.h + defined → PIM11,PIM1A
PTA31 Connector-3 transmit request active signals.h → PTA31,PTA3A
PTA41 Connector-4 transmit request active signals.h → PTA41,PTA4A
PU002 Connector-2 selected (all channels) L12·02 signals.h → PU002,PU003,PU004
PUB01_d1 Busy condition group 1 inverted signals.h → PUB01_d1,PUB01_d2,PUB01_d3,PUB01_d4
PUC1 Channel-1 selection (PIC1+PIM1) H13·01 console,msl-commands + signals.h → PUC1,PUC11
PUC21 PUC2 alias signals.h + defined → PUC21,PUC26,PUC2A
PUC31 PUC3 alias signals.h + defined → PUC31,PUC36,PUC3A
RB121 RB121 alias (UNIV delay) signals.h → RB121,RB12A
RES0 CPU or channel-1 cycle assigned C5·10 pulse → RES0,RES01
RES3 Channel-3 cycle assigned C5·02 msl-commands,pulse + signals.h → RES3,RES31
RUF11 Channel-1 transfer end (RUF1) signals.h → RUF11,RUF1A
TE103 Connector-3 trigger TE10 G11·15 signals.h → TE103,TE104
TE203 Connector-3 trigger TE20 G11·14 signals.h → TE203,TE204
TE303 Connector-3 trigger TE30 (transmit) H7·13 signals.h → TE303,TE304
UCO01 UA function code bit 0 (decimal-ADD) signals.h + defined → UCO01,UCO0A
UCO11 UA function code bit 1 decoded signals.h + defined → UCO11,UCO1A
UCO21 UA function code bit 2 decoded signals.h + defined → UCO21,UCO2A
UCO41 UA function code bit 4 decoded signals.h + defined → UCO41,UCO4A
VAMA1 VAMA2 with DIAG override O15·01 ge → VAMA1,VAMA2
AEBEC AEBE selection trigger inverted G1·01 defined
AECO3 Connector-3 select (PUOO3) G6·10 defined
AF10 Console selector → V4 D18·16 defined
AITE Console SITE (stop/insert) switch msl-states + signals.h
AITEA SITE switch inverted signals.h
BI201 Reader binary 2nd-nibble clock defined
CI50B CI50 inverted (inhibits inter-zone) signals.h
DE06A Function+state AND: LA inverted A17·16 signals.h
DE08A0 Function+state AND: decode08+beta defined
DE11A Function+state AND: console group inverted A9·06 signals.h
DE13A Function+state AND: LPSR inverted A9·05 signals.h
DU161 State/signal decode SA+PC11/PC21 B31·15 signals.h
DU18A RIG3+L207 decode inverted G37·04 signals.h
DU19A RIG1+PC011+not-RACI inverted G37·03 signals.h
DU201 Combined RIG1/RIG3 decode C23·14 signals.h
DU871 Rejected/not-in-transfer decode F37·04 signals.h
DU881 Channel-2 transfer exit gate G29·01 signals.h
DU89A Channel-2 exit condition inverted E26·02 signals.h
DU90A Selected channel RO-decode inverted F26·05 signals.h
DU91A Selected channel RO-decode ch3 inverted E40·13 signals.h
DU93A LPER external op inverted D24·07 signals.h
DU95A RO status decode inverted B40·09 signals.h
DU96A L2 status decode inverted C15·13 signals.h
DU97A Channel-2 overlap XOR inverted E11·10 signals.h
FEL06 CPU version 466 (6μs) strap D8·04 ge
FEL16 CPU version 467/468 strap D8·13 ge
FIDE1 Reader end-of-sequence (FIDEN) defined
FINA1 Connector-1 end condition signals.h
FINE3 Connector-3 end condition signals.h
FINE4 Connector-4 end condition signals.h
FINI1 Reader end-of-read (FININ) signals.h
FINUC Connector-3 FINU command signals.h
FU091 Connector-1 photodisc strobe (stubbed) G7·12 signals.h
FUSE1 Connector-1 out-of-service signals.h
INES3 Connector-3 interrupt enabled (strap F03) ge
INES4 Connector-4 interrupt enabled (strap F03) ge
LENO1 Reader not operable (LENON) defined
LESA Loader Enable Select A (reader selection) H9·10 reader / cardreader → LESA,LESA2,LESAA,LESAB
LU081 Reader char-ready strobe (LU08N) signals.h
LUPO1 Reader ready/free (LUPOR) signals.h
LURE1 Reader error/jam (LUREN) defined
LUSE1 Reader out-of-service (LUSEN) defined
MARE3 Connector-3 out-of-service signals.h
MARE4 Connector-4 out-of-service signals.h
PA11A Connector-1 request path inverted G8·15 signals.h
PA12A Connector-2 request path inverted H8·11 signals.h
PA13A Connector-3 request path inverted H11·02 signals.h
PA14A Connector-4 request path inverted H12·13 signals.h
PAM1A PAM1 (RASI1+RM101) signals.h
PAM4A PAM4 (RELO1+RASI1+PC121) H8·04 signals.h
PB11A FINA1+PC111 decode (printer) G9·12 signals.h
PB12A Reader input enable ch1 inverted signals.h
PB13A TE303+PC131 (conn-3 output) G11·03 signals.h
PB14A TE304+PC141 (conn-4 output) G8·03 signals.h
PB22A Reader input enable ch2 inverted P12·02 signals.h
PB32A Reader input enable ch3 inverted P11·04 signals.h
PC31A Connector-1 selection inverted (ch 3) F15·09 signals.h
PELEA PELE condition (LU08+LUPO1) N14·05 signals.h
PF12A Connector-2 end (ch1) inverted H9·01 signals.h
PF13A Connector-3 end (ch1) inverted H12·03 signals.h
PF14A Connector-4 end (ch1) inverted H12·02 signals.h
PIB21 Reader input into NE (OR all ch) signals.h
PIB31 Connector-3 input into NE signals.h
PIB41 Connector-4 input into NE signals.h
PIC1A PIC1 inverted signals.h
PICO1 Reader first-column flag (PICON) defined
PM11A Connector-1 MARE inverted G10·12 signals.h
PM13A Connector-3 MARE inverted G9·16 signals.h
PM14A Connector-4 MARE inverted L8·11 signals.h
POM01 Reader binary-mode indicator defined
PUB01 Selected connector busy (NAND all) msl-states
PUOO3 Connector-3 selection alias signals.h
PV13A Connector-3 VICU path inverted H11·06 signals.h
RA101 Channel-1 char-exchange request (OR) H12·14 ge
RASI1 Channel-1 in-transfer (RASI) signals.h
RATE1 Connector-3 AEBE emission (stubbed) G11·01 signals.h
RAVI1 VICU emission signal (stubbed) signals.h
RB01A RT121+RB101 inverted signals.h
RB101 Channel-1 trigger end (OR) signals.h
RB111 RB111 end-condition G12·06 msl-commands,reader + signals.h
RB13A Connector-3 input enable ch1 inverted signals.h
RB14A Connector-4 input enable ch1 inverted signals.h
RB33A Connector-3 input enable ch3 inverted signals.h
RB34A Connector-4 input enable ch3 inverted signals.h
RELO1 Reader load condition (PELEA+RUF1A) signals.h
RES2 Channel-2 cycle assigned C5·06 msl-commands,pulse + signals.h
RESI Channel-1 cycle request (sync) msl-commands + signals.h
RESI1 RESI alias signals.h
RESIA RESI inverted signals.h
RET21 Channel-2 cycle-assignment stored (T010) signals.h
RF101 Channel-1 OR of peripheral end conditions H12·15 defined
RIA01 CPU cycle request (sync) / RIA0 signals.h
RIA2A Channel-2 request inverted signals.h
RIA3A Channel-3 request inverted signals.h
RIUC CPU cycle assigned (exec. micro-cycle) msl-commands,pulse + signals.h
RIUCA No-attribution inverted signals.h
RL1U1 L1 all-ones decode (terminal-count) I10·10 msl-states
RM101 Out-of-service (OR of PM1x) H12·11 signals.h
RS011 Selection reset (PAM4A+PAM1A) signals.h
RT111 Connector-3 timing (stubbed) G11·06 signals.h
RT121 Timing pulse RT121 (UNIV 1.2μs) G10·02 signals.h
RT131 Timing pulse RT131 (UNIV 1.2μs) G11·12 signals.h
RT311 Connector-3 timing 1 (stubbed) G11·07 signals.h
RT321 Connector-3 timing 2 (stubbed) G10·18 signals.h
RT331 Connector-3 timing 3 (stubbed) G11·11 signals.h
RUF31 Channel-3 transfer end (stubbed) signals.h
SEPEI Connector-1 selected (NAND all ch) signals.h
TO501 Clock TO50 active signals.h
TU00A RI read-strobe inverted (TU00N) msl-commands
TU10C Connector-3 TU10 inverted defined
TU20C Connector-3 TU20 inverted defined
TU30C Connector-3 TU30 inverted defined
UCOA1 UA function code bit A decoded signals.h
UZE71_enabled UA high-zone enable (UZE71) defined
UZE81_enabled UA bit-8 zone enable (UZE81) defined
VAMB1 VEMB6 with DIAG override D19·15 ge + signals.h
VAMC1 VAMC2 with DIAG override C19·16 ge + signals.h
VAMC2 Memory capacity select C (strap E05) D19·01 ge + signals.h
VEMB6 Memory capacity select B (strap F05) D19·14 ge + signals.h
verified_condition (combinatorial decode) msl-commands
VICU3 Connector-3 VICU output defined
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