RISC-V uArch vs. instructions

uarchvsinst.md

uArch Components

TLB, PTW, I-Cache, D-Cache, Shared Cache, BP, RAS, Load-Store Queue (LSQ)

Load/Store

lb(u), lh(u), lw
sb(u), sh(u), sw

Arithmetic

sll(i), srl(i), sra(i)
add(i), sub, lui, auipc
xor(i), or(i), and(i)
slt(i)(u)

Branch

beq, bne, bge(u), blt(u)

Jump

jal, jalr

Sync

fence, fence.i

MMU Sync

sfence.vma

Instructions	TLB	PTW	IC	DC	SC	BP	LSQ	RAS
Load/Store	O	O	O	O	O		O
Arithmetic			O		O
Branch			O		O	O
Jump						O		O
Sync			O	O	O		O
MMU Sync	O