target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
target triple = "i386-pc-linux-gnu-elf"
%struct.Memory = type opaque
%struct.State = type { %struct.ArchState, [32 x %union.VectorReg], %struct.ArithFlags, %union.anon, %struct.Segments, %struct.AddressSpace, %struct.GPR, %struct.X87Stack, %struct.MMX, %struct.FPUStatusFlags, %union.anon, %union.FPU, %struct.SegmentCaches }
%struct.ArchState = type { i32, i32, %union.anon }
%union.VectorReg = type { %union.vec512_t }
%union.vec512_t = type { %struct.uint64v8_t }
%struct.uint64v8_t = type { [8 x i64] }
%struct.ArithFlags = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
%struct.Segments = type { i16, %union.SegmentSelector, i16, %union.SegmentSelector, i16, %union.SegmentSelector, i16, %union.SegmentSelector, i16, %union.SegmentSelector, i16, %union.SegmentSelector }
%union.SegmentSelector = type { i16 }
%struct.AddressSpace = type { i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg }
%struct.Reg = type { %union.anon.1, i32 }
%union.anon.1 = type { i32 }
%struct.GPR = type { i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg, i64, %struct.Reg }
%struct.X87Stack = type { [8 x %struct.anon.3] }
%struct.anon.3 = type { i64, double }
%struct.MMX = type { [8 x %struct.anon.4] }
%struct.anon.4 = type { i64, %union.vec64_t }
%union.vec64_t = type { %struct.uint64v1_t }
%struct.uint64v1_t = type { [1 x i64] }
%struct.FPUStatusFlags = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [4 x i8] }
%union.anon = type { i64 }
%union.FPU = type { %struct.anon.13 }
%struct.anon.13 = type { %struct.FpuFXSAVE, [96 x i8] }
%struct.FpuFXSAVE = type { %union.SegmentSelector, %union.SegmentSelector, %union.FPUAbridgedTagWord, i8, i16, i32, %union.SegmentSelector, i16, i32, %union.SegmentSelector, i16, %union.anon.1, %union.anon.1, [8 x %struct.FPUStackElem], [16 x %union.vec128_t] }
%union.FPUAbridgedTagWord = type { i8 }
%struct.FPUStackElem = type { %union.anon.11, [6 x i8] }
%union.anon.11 = type { %struct.float80_t }
%struct.float80_t = type { [10 x i8] }
%union.vec128_t = type { %struct.uint128v1_t }
%struct.uint128v1_t = type { [1 x i128] }
%struct.SegmentCaches = type { %struct.SegmentShadow, %struct.SegmentShadow, %struct.SegmentShadow, %struct.SegmentShadow, %struct.SegmentShadow, %struct.SegmentShadow }
%struct.SegmentShadow = type { %union.anon, i32, i32 }
; Function Attrs: noinline nounwind
define <{ i32, i32 }> @"BigMul(double, long double)"(double %x, x86_fp80 %y) local_unnamed_addr #0 {
%1 = tail call i8* @llvm.returnaddress(i32 0)
%2 = ptrtoint i8* %1 to i32
%3 = fptrunc x86_fp80 %y to double
%4 = bitcast double %3 to i64
%5 = and i64 %4, 9221120237041090560
%6 = icmp eq i64 %5, 9218868437227405312
br i1 %6, label %7, label %.thread
7: ; preds = %0
%8 = and i64 %4, 2251799813685247
%9 = icmp eq i64 %8, 0
%10 = or i64 %4, 2251799813685248
%11 = bitcast i64 %10 to double
br i1 %9, label %.thread, label %12
.thread: ; preds = %0, %7
br label %12
12: ; preds = %7, %.thread
%13 = phi i8 [ 0, %.thread ], [ 1, %7 ]
%14 = phi double [ %3, %.thread ], [ %11, %7 ]
%15 = tail call i32 @__remill_fpu_exception_test_and_clear(i32 0, i32 61) #8
%16 = fmul double %14, %x
%17 = tail call i32 @__remill_fpu_exception_test_and_clear(i32 61, i32 %15) #8
%18 = trunc i32 %17 to i8
%19 = and i8 %18, 1
%20 = or i8 %19, %13
%21 = tail call double @round(double %16) #9, !noalias !0
%22 = bitcast double %21 to i64
%23 = and i64 %22, 9221120237041090560
%24 = icmp eq i64 %23, 9218868437227405312
br i1 %24, label %25, label %29
25: ; preds = %12
%26 = and i64 %22, 2251799813685247
%27 = icmp ne i64 %26, 0
%28 = zext i1 %27 to i8
br label %29
29: ; preds = %25, %12
%30 = phi i8 [ 0, %12 ], [ %28, %25 ]
%31 = or i8 %20, %30
%32 = icmp eq i8 %31, 0
%33 = or i64 %22, 2251799813685248
%34 = bitcast i64 %33 to double
%35 = select i1 %32, double %21, double %34
%36 = tail call i32 @fegetround() #10
%37 = lshr i32 %36, 10
%38 = shl i32 %36, 22
%39 = or i32 %37, %38
switch i32 %39, label %43 [
i32 3, label %42
i32 1, label %40
i32 2, label %41
]
40: ; preds = %29
br label %43
41: ; preds = %29
br label %43
42: ; preds = %29
br label %43
43: ; preds = %29, %42, %41, %40
%44 = phi i32 [ 1024, %40 ], [ 2048, %41 ], [ 3072, %42 ], [ 0, %29 ]
%45 = tail call i32 @fesetround(i32 3072) #11
%46 = tail call double @llvm.nearbyint.f64(double %35) #9
%47 = fcmp ueq double %46, 0.000000e+00
br i1 %47, label %48, label %50
48: ; preds = %43
%49 = tail call double @llvm.fabs.f64(double %46) #9
br label %54
50: ; preds = %43
%51 = tail call double @llvm.fabs.f64(double %46) #1
%52 = fcmp oeq double %51, 0x7FF0000000000000
br i1 %52, label %54, label %53
53: ; preds = %50
br label %54
54: ; preds = %53, %50, %48
%55 = phi double [ %49, %48 ], [ 0x7FF0000000000000, %50 ], [ %51, %53 ]
tail call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() #9, !srcloc !3
%56 = fptosi double %46 to i64
tail call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() #9, !srcloc !4
%57 = fcmp ogt double %55, 0x43E0000000000000
%58 = select i1 %57, i64 -9223372036854775808, i64 %56
%59 = tail call i32 @fesetround(i32 %44) #11
%.sroa.5.20.extract.trunc = trunc i64 %58 to i32
%.sroa.5.24.extract.shift = lshr i64 %58, 32
%.sroa.5.24.extract.trunc = trunc i64 %.sroa.5.24.extract.shift to i32
%60 = tail call %struct.Memory* @__remill_function_return(%struct.State* nonnull undef, i32 %2, %struct.Memory* null) #9
%61 = insertvalue <{ i32, i32 }> undef, i32 %.sroa.5.20.extract.trunc, 0
%62 = insertvalue <{ i32, i32 }> %61, i32 %.sroa.5.24.extract.trunc, 1
ret <{ i32, i32 }> %62
}
; Function Attrs: nounwind readnone
declare i8* @llvm.returnaddress(i32 immarg) #1
; Function Attrs: nounwind readnone speculatable
declare double @llvm.fabs.f64(double) #2
; Function Attrs: nounwind readnone
declare dso_local i32 @__remill_fpu_exception_test_and_clear(i32, i32) local_unnamed_addr #3
; Function Attrs: nounwind readonly
declare dso_local i32 @fegetround() local_unnamed_addr #4
; Function Attrs: nounwind
declare dso_local i32 @fesetround(i32) local_unnamed_addr #5
; Function Attrs: nounwind readnone speculatable
declare double @llvm.nearbyint.f64(double) #2
; Function Attrs: noduplicate noinline nounwind optnone
declare dso_local %struct.Memory* @__remill_function_return(%struct.State* dereferenceable(3376), i32, %struct.Memory*) local_unnamed_addr #6
; Function Attrs: noinline
declare double @round(double) local_unnamed_addr #7
attributes #0 = { noinline nounwind }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readnone speculatable }
attributes #3 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #4 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #5 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #6 = { noduplicate noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #7 = { noinline }
attributes #8 = { nobuiltin nounwind readnone }
attributes #9 = { nounwind }
attributes #10 = { alwaysinline nobuiltin nounwind readonly }
attributes #11 = { alwaysinline nobuiltin nounwind }
!0 = !{!1}
!1 = distinct !{!1, !2, !"round.anvill.lifted_to_native: argument 0"}
!2 = distinct !{!2, !"round.anvill.lifted_to_native"}
!3 = !{i32 -2144213175}
!4 = !{i32 -2144213100}
