Amaranth blinker Verilog output

blinker.py

from amaranth import Module, Signal, Elaboratable
from amaranth.back import verilog


class Blinker(Elaboratable):
    def __init__(self, half_freq) -> None:
        self.half_freq = half_freq
        self.led = Signal()

    def elaborate(self, platform):
        m = Module()

        self.timer = Signal(range(self.half_freq + 1))
        with m.If(self.timer == self.half_freq):
            m.d.sync += self.led.eq(~(self.led))
            m.d.sync += self.timer.eq(0)
        with m.Else():
            m.d.sync += self.timer.eq(self.timer + 1)

        return m


if __name__ == "__main__":
    blinker = Blinker(10)
    ports = [blinker.led]
    print(verilog.convert(blinker, ports=ports))

blinker.v

/* Generated by Yosys 0.48 (git sha1 aaa5347494801e9e3870b31387da59da24233f76, clang++ 16.0.0 -fPIC -O3) */

(* top =  1  *)
(* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:11" *)
(* generator = "Amaranth" *)
module top(rst, led, clk);
  reg \$auto$verilog_backend.cc:2348:dump_module$1  = 0;
  wire \$1 ;
  wire \$2 ;
  wire [4:0] \$3 ;
  reg \$4 ;
  reg [3:0] \$5 ;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/.direnv/python-3.12/lib/python3.12/site-packages/amaranth/hdl/_ir.py:283" *)
  input clk;
  wire clk;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:8" *)
  output led;
  reg led = 1'h0;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/.direnv/python-3.12/lib/python3.12/site-packages/amaranth/hdl/_ir.py:283" *)
  input rst;
  wire rst;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:13" *)
  reg [3:0] timer = 4'h0;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:8" *)
  always @(posedge clk)
    led <= \$4 ;
  (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:13" *)
  always @(posedge clk)
    timer <= \$5 ;
  assign \$1  = timer == (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:14" *) 4'ha;
  assign \$2  = ~ (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:15" *) led;
  assign \$3  = timer + (* src = "/Users/dave/work/verilog/icebreaker/icebreaker-amaranth-examples/icebreaker/blink/blinker.py:18" *) 1'h1;
  always @* begin
    if (\$auto$verilog_backend.cc:2348:dump_module$1 ) begin end
    (* full_case = 32'd1 *)
    if (\$1 ) begin
      \$5  = 4'h0;
    end else begin
      \$5  = \$3 [3:0];
    end
    if (rst) begin
      \$5  = 4'h0;
    end
  end
  always @* begin
    if (\$auto$verilog_backend.cc:2348:dump_module$1 ) begin end
    \$4  = led;
    if (\$1 ) begin
      \$4  = \$2 ;
    end
    if (rst) begin
      \$4  = 1'h0;
    end
  end
endmodule