Created
June 26, 2021 20:06
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servant Go Board
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| Info: constrained 'i_clk' to bel 'X0/Y8/io1' | |
| Info: constrained 'q' to bel 'X13/Y6/io1' | |
| Info: Packing constants.. | |
| Info: Packing IOs.. | |
| Info: Packing LUT-FFs.. | |
| Info: 277 LCs used as LUT4 only | |
| Info: 124 LCs used as LUT4 and DFF | |
| Info: Packing non-LUT FFs.. | |
| Info: 131 LCs used as DFF only | |
| Info: Packing carries.. | |
| Info: 37 LCs used as CARRY only | |
| Info: Packing RAMs.. | |
| Info: Placing PLLs.. | |
| Info: Packing special functions.. | |
| Info: Packing PLLs.. | |
| Info: Promoting globals.. | |
| Info: promoting i_clk$SB_IO_IN (fanout 261) | |
| Info: promoting wb_rst [reset] (fanout 110) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$2577 [cen] (fanout 32) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$3342 [cen] (fanout 32) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$3540 [cen] (fanout 31) | |
| Info: promoting servant.cpu.cpu.bufreg_en [cen] (fanout 30) | |
| Info: Constraining chains... | |
| Info: 4 LCs used to legalise carry chains. | |
| Info: Checksum: 0x728f8cdb | |
| Info: Annotating ports with timing budgets for target frequency 20.00 MHz | |
| Info: Checksum: 0x628109ce | |
| Info: Device utilisation: | |
| Info: ICESTORM_LC: 575/ 1280 44% | |
| Info: ICESTORM_RAM: 3/ 16 18% | |
| Info: SB_IO: 2/ 112 1% | |
| Info: SB_GB: 6/ 8 75% | |
| Info: ICESTORM_PLL: 0/ 1 0% | |
| Info: SB_WARMBOOT: 0/ 1 0% | |
| Info: Placed 2 cells based on constraints. | |
| Info: Creating initial analytic placement for 505 cells, random placement wirelen = 7577. | |
| Info: at initial placer iter 0, wirelen = 302 | |
| Info: at initial placer iter 1, wirelen = 338 | |
| Info: at initial placer iter 2, wirelen = 332 | |
| Info: at initial placer iter 3, wirelen = 365 | |
| Info: Running main analytical placer. | |
| Info: at iteration #1, type ALL: wirelen solved = 360, spread = 3245, legal = 3527; time = 0.01s | |
| Info: at iteration #2, type ALL: wirelen solved = 117, spread = 2382, legal = 2948; time = 0.01s | |
| Info: at iteration #3, type ALL: wirelen solved = 168, spread = 2443, legal = 2987; time = 0.01s | |
| Info: at iteration #4, type ALL: wirelen solved = 269, spread = 2324, legal = 3039; time = 0.01s | |
| Info: at iteration #5, type ALL: wirelen solved = 343, spread = 2288, legal = 2874; time = 0.01s | |
| Info: at iteration #6, type ALL: wirelen solved = 377, spread = 2414, legal = 3005; time = 0.01s | |
| Info: at iteration #7, type ALL: wirelen solved = 409, spread = 2257, legal = 2833; time = 0.01s | |
| Info: at iteration #8, type ALL: wirelen solved = 407, spread = 2220, legal = 2971; time = 0.01s | |
| Info: at iteration #9, type ALL: wirelen solved = 426, spread = 2245, legal = 2842; time = 0.01s | |
| Info: at iteration #10, type ALL: wirelen solved = 595, spread = 2227, legal = 2891; time = 0.01s | |
| Info: at iteration #11, type ALL: wirelen solved = 588, spread = 1983, legal = 2862; time = 0.01s | |
| Info: at iteration #12, type ALL: wirelen solved = 613, spread = 1919, legal = 2684; time = 0.01s | |
| Info: at iteration #13, type ALL: wirelen solved = 647, spread = 1819, legal = 2495; time = 0.01s | |
| Info: at iteration #14, type ALL: wirelen solved = 686, spread = 2120, legal = 3039; time = 0.01s | |
| Info: at iteration #15, type ALL: wirelen solved = 822, spread = 2248, legal = 2885; time = 0.01s | |
| Info: at iteration #16, type ALL: wirelen solved = 893, spread = 1809, legal = 2375; time = 0.01s | |
| Info: at iteration #17, type ALL: wirelen solved = 792, spread = 1787, legal = 2544; time = 0.01s | |
| Info: at iteration #18, type ALL: wirelen solved = 764, spread = 1719, legal = 2382; time = 0.01s | |
| Info: at iteration #19, type ALL: wirelen solved = 814, spread = 1994, legal = 2467; time = 0.01s | |
| Info: at iteration #20, type ALL: wirelen solved = 969, spread = 2027, legal = 2699; time = 0.01s | |
| Info: at iteration #21, type ALL: wirelen solved = 1020, spread = 2004, legal = 2450; time = 0.01s | |
| Info: HeAP Placer Time: 0.29s | |
| Info: of which solving equations: 0.16s | |
| Info: of which spreading cells: 0.02s | |
| Info: of which strict legalisation: 0.06s | |
| Info: Running simulated annealing placer for refinement. | |
| Info: at iteration #1: temp = 0.000000, timing cost = 50, wirelen = 2375 | |
| Info: at iteration #5: temp = 0.000000, timing cost = 85, wirelen = 1994 | |
| Info: at iteration #10: temp = 0.000000, timing cost = 78, wirelen = 1871 | |
| Info: at iteration #15: temp = 0.000000, timing cost = 77, wirelen = 1812 | |
| Info: at iteration #20: temp = 0.000000, timing cost = 66, wirelen = 1775 | |
| Info: at iteration #21: temp = 0.000000, timing cost = 66, wirelen = 1769 | |
| Info: SA placement time 0.28s | |
| Info: Max frequency for clock 'i_clk$SB_IO_IN_$glb_clk': 93.82 MHz (PASS at 20.00 MHz) | |
| Info: Max delay posedge i_clk$SB_IO_IN_$glb_clk -> <async>: 1.89 ns | |
| Info: Slack histogram: | |
| Info: legend: * represents 2 endpoint(s) | |
| Info: + represents [1,2) endpoint(s) | |
| Info: [ 39341, 39813) |+ | |
| Info: [ 39813, 40285) |*******+ | |
| Info: [ 40285, 40757) |*****+ | |
| Info: [ 40757, 41229) |******+ | |
| Info: [ 41229, 41701) |****************+ | |
| Info: [ 41701, 42173) |************+ | |
| Info: [ 42173, 42645) |******+ | |
| Info: [ 42645, 43117) |*******+ | |
| Info: [ 43117, 43589) |*******************+ | |
| Info: [ 43589, 44061) |*****+ | |
| Info: [ 44061, 44533) |********************+ | |
| Info: [ 44533, 45005) |**********************************************+ | |
| Info: [ 45005, 45477) |********************+ | |
| Info: [ 45477, 45949) |************+ | |
| Info: [ 45949, 46421) |***************+ | |
| Info: [ 46421, 46893) |*******+ | |
| Info: [ 46893, 47365) |**+ | |
| Info: [ 47365, 47837) |***************************+ | |
| Info: [ 47837, 48309) |******************+ | |
| Info: [ 48309, 48781) |************************************************************ | |
| Info: Checksum: 0x598a83f1 | |
| Info: Routing.. | |
| Info: Setting up routing queue. | |
| Info: Routing 1786 arcs. | |
| Info: | (re-)routed arcs | delta | remaining| time spent | | |
| Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| | |
| Info: 1000 | 64 869 | 64 869 | 861| 0.08 0.08| | |
| Info: 2000 | 247 1686 | 183 817 | 118| 0.12 0.20| | |
| Info: 2137 | 262 1809 | 15 123 | 0| 0.02 0.22| | |
| Info: Routing complete. | |
| Info: Router1 time 0.22s | |
| Info: Checksum: 0x8f9e4037 | |
| Info: Critical path report for clock 'i_clk$SB_IO_IN_$glb_clk' (posedge -> posedge): | |
| Info: curr total | |
| Info: 2.1 2.1 Source servant.cpu.rf_ram.memory.0.0.0_RAM.RDATA_3 | |
| Info: 0.6 2.7 Net servant.cpu.rdata[0] budget 7.457000 ns (3,7) -> (4,6) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4230_LC.I1 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:82 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v:30 | |
| Info: 0.4 3.1 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4230_LC.O | |
| Info: 1.0 4.1 Net $abc$4115$servant.cpu.cpu.ctrl.i_csr_pc_new_inv_ budget 7.456000 ns (4,6) -> (4,5) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4229_LC.I2 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:305 | |
| Info: ../src/serv_1.0.2/rtl/serv_ctrl.v:23 | |
| Info: 0.4 4.5 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4229_LC.O | |
| Info: 1.3 5.7 Net $abc$4115$servant.cpu.cpu.alu.i_op_b_new_inv_ budget 4.971000 ns (4,5) -> (2,3) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4228_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:17 | |
| Info: 0.4 6.2 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4228_LC.O | |
| Info: 0.6 6.8 Net $abc$4115$techmap\servant.cpu.cpu.alu.$logic_not$../src/serv_1.0.2/rtl/serv_alu.v:38$247_Y_new_inv_ budget 4.971000 ns (2,3) -> (2,4) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4227_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:38 | |
| Info: 0.4 7.2 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4227_LC.O | |
| Info: 0.6 7.8 Net $abc$4115$techmap\servant.cpu.cpu.alu.$and$../src/serv_1.0.2/rtl/serv_alu.v:57$257_Y_new_ budget 4.971000 ns (2,4) -> (2,4) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4226_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:57 | |
| Info: 0.4 8.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4226_LC.O | |
| Info: 0.6 8.9 Net $abc$4115$techmap\servant.cpu.cpu.rf_if.$and$../src/serv_1.0.2/rtl/serv_rf_if.v:57$214_Y_new_ budget 4.971000 ns (2,4) -> (2,5) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4224_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:352 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_if.v:57 | |
| Info: 0.4 9.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4224_LC.O | |
| Info: 0.6 9.9 Net $abc$4115$new_n548_ budget 4.970000 ns (2,5) -> (2,6) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4248_LC.I0 | |
| Info: 0.4 10.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4248_LC.O | |
| Info: 1.0 11.3 Net servant.cpu.wdata[1] budget 4.970000 ns (2,6) -> (3,7) | |
| Info: Sink servant.cpu.rf_ram.memory.0.0.0_RAM.WDATA_11 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:77 | |
| Info: 0.1 11.4 Setup servant.cpu.rf_ram.memory.0.0.0_RAM.WDATA_11 | |
| Info: 5.3 ns logic, 6.1 ns routing | |
| Info: Critical path report for cross-domain path 'posedge i_clk$SB_IO_IN_$glb_clk' -> '<async>': | |
| Info: curr total | |
| Info: 0.5 0.5 Source $auto$simplemap.cc:420:simplemap_dff$888_DFFLC.O | |
| Info: 1.3 1.8 Net q$SB_IO_OUT budget 49.459999 ns (11,3) -> (13,6) | |
| Info: Sink q$sb_io.D_OUT_0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:6 | |
| Info: 0.5 ns logic, 1.3 ns routing | |
| Info: Max frequency for clock 'i_clk$SB_IO_IN_$glb_clk': 87.76 MHz (PASS at 20.00 MHz) | |
| Info: Max delay posedge i_clk$SB_IO_IN_$glb_clk -> <async>: 1.81 ns | |
| Info: Slack histogram: | |
| Info: legend: * represents 2 endpoint(s) | |
| Info: + represents [1,2) endpoint(s) | |
| Info: [ 38605, 39114) |+ | |
| Info: [ 39114, 39623) |+ | |
| Info: [ 39623, 40132) |*+ | |
| Info: [ 40132, 40641) |**+ | |
| Info: [ 40641, 41150) |***********+ | |
| Info: [ 41150, 41659) |***+ | |
| Info: [ 41659, 42168) |********+ | |
| Info: [ 42168, 42677) |**************+ | |
| Info: [ 42677, 43186) |****************************** | |
| Info: [ 43186, 43695) |****************+ | |
| Info: [ 43695, 44204) |****+ | |
| Info: [ 44204, 44713) |*************************+ | |
| Info: [ 44713, 45222) |************ | |
| Info: [ 45222, 45731) |**********+ | |
| Info: [ 45731, 46240) |*********************+ | |
| Info: [ 46240, 46749) |********************************************+ | |
| Info: [ 46749, 47258) |*****+ | |
| Info: [ 47258, 47767) |*********************+ | |
| Info: [ 47767, 48276) |********************+ | |
| Info: [ 48276, 48785) |************************************************************ | |
| Info: Program finished normally. |
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| DEBUG: Setup logging at level 10. | |
| DEBUG: Verbose output | |
| DEBUG: Monochrome output | |
| DEBUG: Looking for config files from /etc/fusesoc/fusesoc.conf:/home/dave/.config/fusesoc/fusesoc.conf:fusesoc.conf | |
| DEBUG: Found config files in fusesoc.conf | |
| DEBUG: cache_root=/home/dave/.cache/fusesoc | |
| DEBUG: library_root=/home/dave/.local/share/fusesoc | |
| DEBUG: Initializing core manager | |
| DEBUG: Checking for cores in fusesoc_libraries/serv | |
| DEBUG: Adding core ::serving:1.0.2 | |
| DEBUG: Adding core ::servant:1.0.2 | |
| DEBUG: Adding core ::serv:1.0.2 | |
| DEBUG: Checking for cores in fusesoc_libraries/fusesoc-generators | |
| DEBUG: Adding core fusesoc:utils:generators:0.1.6 | |
| DEBUG: Adding core fusesoc:utils:generators_template_package:0.1 | |
| DEBUG: Adding core fusesoc:utils:generators_template_local:0.1 | |
| DEBUG: Adding core test:demo:chiselblinky:0 | |
| DEBUG: Adding core fusesoc:utils:generators_template_constraints:0.1 | |
| DEBUG: ::servant:1.0.2 : Getting tool for flags {'tool': None, 'target': 'go_board'} | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': None, 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched tool icestorm | |
| DEBUG: Setting build_root to /home/dave/Shared/verilog/serv/build/servant_1.0.2 | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Getting tool for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Matched tool icestorm | |
| DEBUG: Building EDA API | |
| DEBUG: Calculating dependencies for ==::servant:1.0.2 with flags {'tool': 'icestorm', 'target': 'go_board'} | |
| DEBUG: ::serving:1.0.2 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: ::serving:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serving:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serving:1.0.2 : Matched target default | |
| DEBUG: ::serving:1.0.2 : Matched filesets ['rtl'] | |
| DEBUG: ::servant:1.0.2 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched filesets ['mem_files', 'soc', 'service_no_pll', 'go_board'] | |
| DEBUG: ::serv:1.0.2 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: ::serv:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Matched filesets ['core'] | |
| DEBUG: fusesoc:utils:generators:0.1.6 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: fusesoc:utils:generators:0.1.6 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators:0.1.6 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators:0.1.6 : Matched no target | |
| DEBUG: fusesoc:utils:generators_template_package:0.1 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: fusesoc:utils:generators_template_package:0.1 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_package:0.1 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_package:0.1 : Matched target default | |
| DEBUG: fusesoc:utils:generators_template_package:0.1 : Matched filesets [] | |
| DEBUG: fusesoc:utils:generators_template_local:0.1 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: fusesoc:utils:generators_template_local:0.1 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_local:0.1 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_local:0.1 : Matched target default | |
| DEBUG: fusesoc:utils:generators_template_local:0.1 : Matched filesets ['tb'] | |
| DEBUG: test:demo:chiselblinky:0 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: test:demo:chiselblinky:0 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: test:demo:chiselblinky:0 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: test:demo:chiselblinky:0 : Matched no target | |
| DEBUG: fusesoc:utils:generators_template_constraints:0.1 : Getting dependencies for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: fusesoc:utils:generators_template_constraints:0.1 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_constraints:0.1 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: fusesoc:utils:generators_template_constraints:0.1 : Matched target default | |
| DEBUG: fusesoc:utils:generators_template_constraints:0.1 : Matched filesets ['hdl'] | |
| DEBUG: Resolved core to ::servant:1.0.2 | |
| DEBUG: with dependencies ::serv:1.0.2, ::servant:1.0.2 | |
| INFO: Preparing ::serv:1.0.2 | |
| INFO: Preparing ::servant:1.0.2 | |
| DEBUG: Calculating dependencies for ==::servant:1.0.2 with flags {'tool': 'icestorm', 'target': 'go_board'} | |
| DEBUG: Resolved core to ::servant:1.0.2 | |
| DEBUG: with dependencies ::serv:1.0.2, ::servant:1.0.2 | |
| DEBUG: Searching for generators in ::serv:1.0.2 | |
| DEBUG: ::serv:1.0.2 : Getting generators for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: Found generators: {} | |
| DEBUG: Searching for generators in ::servant:1.0.2 | |
| DEBUG: ::servant:1.0.2 : Getting generators for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: Found generators: {} | |
| DEBUG: Calculating dependencies for ==::servant:1.0.2 with flags {'tool': 'icestorm', 'target': 'go_board'} | |
| DEBUG: Resolved core to ::servant:1.0.2 | |
| DEBUG: with dependencies ::serv:1.0.2, ::servant:1.0.2 | |
| DEBUG: Running generators in ::serv:1.0.2 | |
| DEBUG: ::serv:1.0.2 : Getting ttptttg for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: Running generators in ::servant:1.0.2 | |
| DEBUG: ::servant:1.0.2 : Getting ttptttg for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: Collecting EDA API parameters from ::serv:1.0.2 | |
| DEBUG: ::serv:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Matched filesets ['core'] | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Exporting ['rtl/serv_bufreg.v', 'rtl/serv_alu.v', 'rtl/serv_csr.v', 'rtl/serv_ctrl.v', 'rtl/serv_decode.v', 'rtl/serv_immdec.v', 'rtl/serv_mem_if.v', 'rtl/serv_rf_if.v', 'rtl/serv_rf_ram_if.v', 'rtl/serv_rf_ram.v', 'rtl/serv_state.v', 'rtl/serv_top.v', 'rtl/serv_rf_top.v'] | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Getting parameters for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Found parameters {'RISCV_FORMAL': {'datatype': 'bool', 'paramtype': 'vlogdefine'}, 'SERV_CLEAR_RAM': {'datatype': 'bool', 'paramtype': 'vlogdefine'}} | |
| DEBUG: ::serv:1.0.2 : Getting tool options for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Found tool options {} | |
| DEBUG: ::serv:1.0.2 : Getting hooks for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Matched filesets ['core'] | |
| DEBUG: ::serv:1.0.2 : Getting VPI libraries for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False} | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': False}' | |
| DEBUG: ::serv:1.0.2 : Matched target default | |
| DEBUG: ::serv:1.0.2 : Matched VPI libraries [] | |
| DEBUG: Collecting EDA API parameters from ::servant:1.0.2 | |
| DEBUG: ::servant:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched filesets ['mem_files', 'soc', 'service_no_pll', 'go_board'] | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Exporting ['sw/blinky.hex', 'sw/zephyr_hello.hex', 'servant/servant_clock_gen.v', 'servant/servant_timer.v', 'servant/servant_gpio.v', 'servant/servant_arbiter.v', 'servant/servant_mux.v', 'servant/servant_ram.v', 'servant/servant.v', 'servant/service.v', 'data/go_board.pcf'] | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Getting parameters for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Found parameters {'memfile': {'datatype': 'file', 'paramtype': 'vlogparam', 'description': 'Preload RAM with a hex file at compile-time', 'default': 'blinky.hex'}, 'memsize': {'datatype': 'int', 'paramtype': 'vlogparam', 'description': 'Memory size in bytes for RAM (default 8kiB)', 'default': 512}} | |
| DEBUG: ::servant:1.0.2 : Getting tool options for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Found tool options {'pnr': 'next', 'nextpnr_options': ['--hx1k', '--package', 'vq100', '--freq', '20']} | |
| DEBUG: ::servant:1.0.2 : Getting hooks for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Getting filesets for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched filesets ['mem_files', 'soc', 'service_no_pll', 'go_board'] | |
| DEBUG: ::servant:1.0.2 : Getting VPI libraries for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched VPI libraries [] | |
| DEBUG: Calculating dependencies for ==::servant:1.0.2 with flags {'tool': 'icestorm', 'target': 'go_board'} | |
| DEBUG: Resolved core to ::servant:1.0.2 | |
| DEBUG: with dependencies ::serv:1.0.2, ::servant:1.0.2 | |
| DEBUG: ::servant:1.0.2 : Getting toplevel for flags {'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True} | |
| DEBUG: ::servant:1.0.2 : Resolving target for flags '{'tool': 'icestorm', 'target': 'go_board', 'is_toplevel': True}' | |
| DEBUG: ::servant:1.0.2 : Matched target go_board | |
| DEBUG: ::servant:1.0.2 : Matched toplevel ['service'] | |
| INFO: Setting up project | |
| INFO: Setting up project | |
| INFO: Building | |
| DEBUG: Running make | |
| DEBUG: args : | |
| make -f servant_1.0.2.mk | |
| make[1]: Entering directory '/home/dave/Shared/verilog/serv/build/servant_1.0.2/go_board-icestorm' | |
| yosys -l yosys.log -p "tcl edalize_yosys_template.tcl" | |
| /----------------------------------------------------------------------------\ | |
| | | | |
| | yosys -- Yosys Open SYnthesis Suite | | |
| | | | |
| | Copyright (C) 2012 - 2019 Clifford Wolf <[email protected]> | | |
| | | | |
| | Permission to use, copy, modify, and/or distribute this software for any | | |
| | purpose with or without fee is hereby granted, provided that the above | | |
| | copyright notice and this permission notice appear in all copies. | | |
| | | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | |
| | | | |
| \----------------------------------------------------------------------------/ | |
| Yosys 0.9 (git sha1 1979e0b) | |
| -- Running command `tcl edalize_yosys_template.tcl' -- | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. | |
| 1. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_bufreg.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_bufreg.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_bufreg'. | |
| Successfully finished Verilog frontend. | |
| 2. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_alu.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_alu.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_alu'. | |
| Successfully finished Verilog frontend. | |
| 3. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_csr.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_csr.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_csr'. | |
| Successfully finished Verilog frontend. | |
| 4. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_ctrl.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_ctrl.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_ctrl'. | |
| Successfully finished Verilog frontend. | |
| 5. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_decode.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_decode.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_decode'. | |
| Successfully finished Verilog frontend. | |
| 6. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_immdec.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_immdec.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_immdec'. | |
| Successfully finished Verilog frontend. | |
| 7. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_mem_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_mem_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_mem_if'. | |
| Successfully finished Verilog frontend. | |
| 8. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_if'. | |
| Successfully finished Verilog frontend. | |
| 9. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_ram_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_ram_if'. | |
| Successfully finished Verilog frontend. | |
| 10. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_ram.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_ram.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_ram'. | |
| Successfully finished Verilog frontend. | |
| 11. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_state.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_state.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_state'. | |
| Successfully finished Verilog frontend. | |
| 12. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_top.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_top.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_top'. | |
| Successfully finished Verilog frontend. | |
| 13. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_top.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_top.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_top'. | |
| Successfully finished Verilog frontend. | |
| 14. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_clock_gen.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_clock_gen.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_clock_gen'. | |
| Successfully finished Verilog frontend. | |
| 15. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_timer.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_timer.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_timer'. | |
| Successfully finished Verilog frontend. | |
| 16. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_gpio.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_gpio.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_gpio'. | |
| Successfully finished Verilog frontend. | |
| 17. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_arbiter.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_arbiter.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_arbiter'. | |
| Successfully finished Verilog frontend. | |
| 18. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_mux.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_mux.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_mux'. | |
| Successfully finished Verilog frontend. | |
| 19. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_ram.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_ram.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_ram'. | |
| Successfully finished Verilog frontend. | |
| 20. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant'. | |
| Successfully finished Verilog frontend. | |
| 21. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/service.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/service.v' to AST representation. | |
| Storing AST representation for module `$abstract\service'. | |
| Successfully finished Verilog frontend. | |
| 22. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Generating RTLIL representation for module `$paramod$2a32106e1ec3373ac1e5a9aebce3a711b7475215\service'. | |
| 23. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Parameter \memsize = 512 | |
| Generating RTLIL representation for module `$paramod\service\memsize=512'. | |
| 24. Executing SYNTH_ICE40 pass. | |
| 24.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. | |
| Generating RTLIL representation for module `\SB_IO'. | |
| Generating RTLIL representation for module `\SB_GB_IO'. | |
| Generating RTLIL representation for module `\SB_GB'. | |
| Generating RTLIL representation for module `\SB_LUT4'. | |
| Generating RTLIL representation for module `\SB_CARRY'. | |
| Generating RTLIL representation for module `\SB_DFF'. | |
| Generating RTLIL representation for module `\SB_DFFE'. | |
| Generating RTLIL representation for module `\SB_DFFSR'. | |
| Generating RTLIL representation for module `\SB_DFFR'. | |
| Generating RTLIL representation for module `\SB_DFFSS'. | |
| Generating RTLIL representation for module `\SB_DFFS'. | |
| Generating RTLIL representation for module `\SB_DFFESR'. | |
| Generating RTLIL representation for module `\SB_DFFER'. | |
| Generating RTLIL representation for module `\SB_DFFESS'. | |
| Generating RTLIL representation for module `\SB_DFFES'. | |
| Generating RTLIL representation for module `\SB_DFFN'. | |
| Generating RTLIL representation for module `\SB_DFFNE'. | |
| Generating RTLIL representation for module `\SB_DFFNSR'. | |
| Generating RTLIL representation for module `\SB_DFFNR'. | |
| Generating RTLIL representation for module `\SB_DFFNSS'. | |
| Generating RTLIL representation for module `\SB_DFFNS'. | |
| Generating RTLIL representation for module `\SB_DFFNESR'. | |
| Generating RTLIL representation for module `\SB_DFFNER'. | |
| Generating RTLIL representation for module `\SB_DFFNESS'. | |
| Generating RTLIL representation for module `\SB_DFFNES'. | |
| Generating RTLIL representation for module `\SB_RAM40_4K'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNR'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNW'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. | |
| Generating RTLIL representation for module `\ICESTORM_LC'. | |
| Generating RTLIL representation for module `\SB_PLL40_CORE'. | |
| Generating RTLIL representation for module `\SB_PLL40_PAD'. | |
| Generating RTLIL representation for module `\SB_PLL40_2_PAD'. | |
| Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. | |
| Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. | |
| Generating RTLIL representation for module `\SB_WARMBOOT'. | |
| Generating RTLIL representation for module `\SB_SPRAM256KA'. | |
| Generating RTLIL representation for module `\SB_HFOSC'. | |
| Generating RTLIL representation for module `\SB_LFOSC'. | |
| Generating RTLIL representation for module `\SB_RGBA_DRV'. | |
| Generating RTLIL representation for module `\SB_LED_DRV_CUR'. | |
| Generating RTLIL representation for module `\SB_RGB_DRV'. | |
| Generating RTLIL representation for module `\SB_I2C'. | |
| Generating RTLIL representation for module `\SB_SPI'. | |
| Generating RTLIL representation for module `\SB_LEDDA_IP'. | |
| Generating RTLIL representation for module `\SB_FILTER_50NS'. | |
| Generating RTLIL representation for module `\SB_IO_I3C'. | |
| Generating RTLIL representation for module `\SB_IO_OD'. | |
| Generating RTLIL representation for module `\SB_MAC16'. | |
| Successfully finished Verilog frontend. | |
| 24.2. Executing HIERARCHY pass (managing design hierarchy). | |
| 24.3. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Generating RTLIL representation for module `\service'. | |
| 24.3.1. Analyzing design hierarchy.. | |
| Top module: \service | |
| 24.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\servant'. | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Parameter \memsize = 512 | |
| Generating RTLIL representation for module `$paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant'. | |
| 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_clock_gen'. | |
| Parameter \PLL = 1313820229 | |
| Generating RTLIL representation for module `$paramod\servant_clock_gen\PLL=1313820229'. | |
| 24.3.4. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_timer'. | |
| Parameter \WIDTH = 32 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Generating RTLIL representation for module `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801'. | |
| Note: Assuming pure combinatorial block at ../src/servant_1.0.2/servant/servant_timer.v:21 in | |
| compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending | |
| use of @* instead of @(...) for better match of synthesis and simulation. | |
| 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_top'. | |
| Parameter \RESET_PC = 0 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1'. | |
| 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_gpio'. | |
| Generating RTLIL representation for module `\servant_gpio'. | |
| 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_ram'. | |
| Parameter \depth = 512 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Generating RTLIL representation for module `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram'. | |
| Preloading $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram from blinky.hex | |
| 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_mux'. | |
| Parameter 1 (\sim) = 0 | |
| Generating RTLIL representation for module `$paramod\servant_mux\sim=0'. | |
| 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_arbiter'. | |
| Generating RTLIL representation for module `\servant_arbiter'. | |
| 24.3.11. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_top'. | |
| Parameter \WITH_CSR = 1 | |
| Parameter \PRE_REGISTER = 1 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \RESET_PC = 0 | |
| Generating RTLIL representation for module `$paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top'. | |
| 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_ram'. | |
| Parameter \width = 2 | |
| Parameter \csr_regs = 4 | |
| Generating RTLIL representation for module `$paramod\serv_rf_ram\width=2\csr_regs=4'. | |
| 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_ram_if'. | |
| Parameter \width = 2 | |
| Parameter \reset_strategy = 1296649801 | |
| Parameter \csr_regs = 4 | |
| Generating RTLIL representation for module `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4'. | |
| 24.3.15. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_csr'. | |
| Generating RTLIL representation for module `\serv_csr'. | |
| 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_mem_if'. | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_mem_if\WITH_CSR=1'. | |
| 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_if'. | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_rf_if\WITH_CSR=1'. | |
| 24.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_alu'. | |
| Generating RTLIL representation for module `\serv_alu'. | |
| 24.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_ctrl'. | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \RESET_PC = 0 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1'. | |
| 24.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_bufreg'. | |
| Generating RTLIL representation for module `\serv_bufreg'. | |
| 24.3.22. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_immdec'. | |
| Generating RTLIL representation for module `\serv_immdec'. | |
| 24.3.23. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_decode'. | |
| Parameter \PRE_REGISTER = 1 | |
| Generating RTLIL representation for module `$paramod\serv_decode\PRE_REGISTER=1'. | |
| 24.3.24. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_state'. | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1'. | |
| 24.3.25. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: \serv_csr | |
| Used module: $paramod\serv_mem_if\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_if\WITH_CSR=1 | |
| Used module: \serv_alu | |
| Used module: $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 | |
| Used module: \serv_bufreg | |
| Used module: \serv_immdec | |
| Used module: $paramod\serv_decode\PRE_REGISTER=1 | |
| Used module: $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.26. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: \serv_csr | |
| Used module: $paramod\serv_mem_if\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_if\WITH_CSR=1 | |
| Used module: \serv_alu | |
| Used module: $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 | |
| Used module: \serv_bufreg | |
| Used module: \serv_immdec | |
| Used module: $paramod\serv_decode\PRE_REGISTER=1 | |
| Used module: $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| Removing unused module `$abstract\service'. | |
| Removing unused module `$abstract\servant'. | |
| Removing unused module `$abstract\servant_ram'. | |
| Removing unused module `$abstract\servant_mux'. | |
| Removing unused module `$abstract\servant_arbiter'. | |
| Removing unused module `$abstract\servant_gpio'. | |
| Removing unused module `$abstract\servant_timer'. | |
| Removing unused module `$abstract\servant_clock_gen'. | |
| Removing unused module `$abstract\serv_rf_top'. | |
| Removing unused module `$abstract\serv_top'. | |
| Removing unused module `$abstract\serv_state'. | |
| Removing unused module `$abstract\serv_rf_ram'. | |
| Removing unused module `$abstract\serv_rf_ram_if'. | |
| Removing unused module `$abstract\serv_rf_if'. | |
| Removing unused module `$abstract\serv_mem_if'. | |
| Removing unused module `$abstract\serv_immdec'. | |
| Removing unused module `$abstract\serv_decode'. | |
| Removing unused module `$abstract\serv_ctrl'. | |
| Removing unused module `$abstract\serv_csr'. | |
| Removing unused module `$abstract\serv_alu'. | |
| Removing unused module `$abstract\serv_bufreg'. | |
| Removed 21 unused modules. | |
| 24.4. Executing PROC pass (convert processes to netlists). | |
| 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Found and cleaned up 1 empty switch in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:65$287'. | |
| Removing empty process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:65$287'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Found and cleaned up 1 empty switch in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:38$40'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:38$40'. | |
| Cleaned up 6 empty switches. | |
| 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). | |
| Marked 1 switch rules as full_case in process $proc$../src/servant_1.0.2/servant/servant_ram.v:24$17 in module $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Marked 1 switch rules as full_case in process $proc$../src/servant_1.0.2/servant/servant_timer.v:26$5 in module $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Removed a total of 0 dead cases. | |
| 24.4.3. Executing PROC_INIT pass (extract init attributes). | |
| Found init rule in `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| Set init value: \rst_reg = 5'11111 | |
| 24.4.4. Executing PROC_ARST pass (detect async resets in processes). | |
| 24.4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). | |
| Creating decoders for process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| 1/1: $0\misalign_trap_sync_r[0:0] | |
| Creating decoders for process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| 1/7: $0\o_cnt_r[3:0] | |
| 2/7: $0\o_cnt[2:0] | |
| 3/7: $0\stage_two_req[0:0] | |
| 4/7: $0\o_cnt_done[0:0] | |
| 5/7: $0\ibus_cyc[0:0] | |
| 6/7: $0\init_done[0:0] | |
| 7/7: $0\o_ctrl_jump[0:0] | |
| Creating decoders for process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| 1/40: $0\o_rd_alu_en[0:0] | |
| 2/40: $0\o_rd_csr_en[0:0] | |
| 3/40: $0\o_op_b_source[0:0] | |
| 4/40: $0\o_immdec_en[3:0] | |
| 5/40: $0\o_immdec_ctrl[3:0] | |
| 6/40: $0\o_csr_imm_en[0:0] | |
| 7/40: $0\o_csr_d_sel[0:0] | |
| 8/40: $0\o_csr_source[1:0] | |
| 9/40: $0\o_csr_mcause_en[0:0] | |
| 10/40: $0\o_csr_mie_en[0:0] | |
| 11/40: $0\o_csr_mstatus_en[0:0] | |
| 12/40: $0\o_csr_addr[1:0] | |
| 13/40: $0\o_csr_en[0:0] | |
| 14/40: $0\o_mem_cmd[0:0] | |
| 15/40: $0\o_mem_half[0:0] | |
| 16/40: $0\o_mem_word[0:0] | |
| 17/40: $0\o_mem_signed[0:0] | |
| 18/40: $0\o_alu_rd_sel[2:0] | |
| 19/40: $0\o_alu_cmp_sig[0:0] | |
| 20/40: $0\o_alu_cmp_eq[0:0] | |
| 21/40: $0\o_alu_bool_op[1:0] | |
| 22/40: $0\o_alu_sub[0:0] | |
| 23/40: $0\o_ctrl_mret[0:0] | |
| 24/40: $0\o_ctrl_pc_rel[0:0] | |
| 25/40: $0\o_ctrl_utype[0:0] | |
| 26/40: $0\o_ctrl_jal_or_jalr[0:0] | |
| 27/40: $0\o_bufreg_sh_signed[0:0] | |
| 28/40: $0\o_bufreg_clr_lsb[0:0] | |
| 29/40: $0\o_bufreg_imm_en[0:0] | |
| 30/40: $0\o_bufreg_rs1_en[0:0] | |
| 31/40: $0\o_rd_op[0:0] | |
| 32/40: $0\o_slt_op[0:0] | |
| 33/40: $0\o_shift_op[0:0] | |
| 34/40: $0\o_mem_op[0:0] | |
| 35/40: $0\o_branch_op[0:0] | |
| 36/40: $0\o_ebreak[0:0] | |
| 37/40: $0\o_e_op[0:0] | |
| 38/40: $0\o_cond_branch[0:0] | |
| 39/40: $0\o_bne_or_bge[0:0] | |
| 40/40: $0\o_sh_right[0:0] | |
| Creating decoders for process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| 1/7: $0\op22[0:0] | |
| 2/7: $0\op20[0:0] | |
| 3/7: $0\funct3[2:0] | |
| 4/7: $0\imm30[0:0] | |
| 5/7: $0\op26[0:0] | |
| 6/7: $0\op21[0:0] | |
| 7/7: $0\opcode[4:0] | |
| Creating decoders for process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| 1/6: $0\imm30_25[5:0] | |
| 2/6: $0\imm7[0:0] | |
| 3/6: $0\imm19_12_20[8:0] | |
| 4/6: $0\imm11_7[4:0] | |
| 5/6: $0\imm24_20[4:0] | |
| 6/6: $0\signbit[0:0] | |
| Creating decoders for process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| 1/3: $0\c_r[0:0] | |
| 2/3: $0\data[29:0] | |
| 3/3: $0\o_lsb[1:0] | |
| Creating decoders for process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| 1/3: $0\pc_plus_offset_cy_r[0:0] | |
| 2/3: $0\pc_plus_4_cy_r[0:0] | |
| 3/3: $0\o_ibus_adr[31:0] | |
| Creating decoders for process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| 1/2: $0\add_cy_r[0:0] | |
| 2/2: $0\cmp_r[0:0] | |
| Creating decoders for process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| 1/2: $0\signbit[0:0] | |
| 2/2: $0\dat[31:0] | |
| Creating decoders for process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| 1/10: $0\mcause3_0[3:0] [1] | |
| 2/10: $0\mcause3_0[3:0] [0] | |
| 3/10: $0\mcause3_0[3:0] [2] | |
| 4/10: $0\mcause3_0[3:0] [3] | |
| 5/10: $0\mie_mtie[0:0] | |
| 6/10: $0\mcause31[0:0] | |
| 7/10: $0\mstatus_mpie[0:0] | |
| 8/10: $0\mstatus_mie[0:0] | |
| 9/10: $0\timer_irq_r[0:0] | |
| 10/10: $0\o_new_irq[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| 1/1: $0\rdata1[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| 1/1: $0\wdata0_r[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| 1/5: $0\rdata0[1:0] | |
| 2/5: $0\rgnt[0:0] | |
| 3/5: $0\rreq_r[0:0] | |
| 4/5: $0\rcnt[4:0] | |
| 5/5: $0\rtrig1[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| 1/3: $0\wdata1_r[1:0] | |
| 2/3: $0\wen1_r[0:0] | |
| 3/3: $0\wen0_r[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| 1/4: $0\o_rdata[1:0] | |
| 2/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 | |
| 3/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_DATA[1:0]$62 | |
| 4/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_ADDR[9:0]$63 | |
| Creating decoders for process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| 1/1: $0\o_wb_cpu_ack[0:0] | |
| Creating decoders for process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| 1/13: $0\o_wb_rdt[31:0] | |
| 2/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 | |
| 3/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA[31:0]$24 | |
| 4/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_ADDR[6:0]$27 | |
| 5/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 | |
| 6/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA[31:0]$25 | |
| 7/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_ADDR[6:0]$23 | |
| 8/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 | |
| 9/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA[31:0]$29 | |
| 10/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_ADDR[6:0]$28 | |
| 11/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 | |
| 12/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_DATA[31:0]$32 | |
| 13/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_ADDR[6:0]$31 | |
| Creating decoders for process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| 1/1: $0\o_wb_ack[0:0] | |
| Creating decoders for process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| 1/2: $0\o_wb_rdt[0:0] | |
| 2/2: $0\o_gpio[0:0] | |
| Creating decoders for process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| 1/3: $0\o_irq[0:0] | |
| 2/3: $0\mtime[31:0] | |
| 3/3: $0\mtimecmp[31:0] | |
| Creating decoders for process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| 1/1: $0\o_wb_dat[31:0] | |
| Creating decoders for process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| 1/1: $1\rst_reg[4:0] | |
| Creating decoders for process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| 1/1: $0\rst_reg[4:0] | |
| 24.4.6. Executing PROC_DLATCH pass (convert process syncs to latches). | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bne_or_bge' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_cond_branch' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_e_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ebreak' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_branch_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_shift_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_slt_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_sh_right' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_rs1_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_imm_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_clr_lsb' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_sh_signed' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_jal_or_jalr' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_utype' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_pc_rel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_mret' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_op_b_source' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_sub' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_bool_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_cmp_eq' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_cmp_sig' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_rd_sel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_cmd' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_signed' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_word' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_half' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_addr' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mstatus_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mie_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mcause_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_source' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_d_sel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_imm_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_immdec_ctrl' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_immdec_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_csr_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_alu_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\o_wb_dat' from process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| 24.4.7. Executing PROC_DFF pass (convert process syncs to FFs). | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\misalign_trap_sync_r' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| created $dff cell `$procdff$660' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt_done' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$661' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_ctrl_jump' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$662' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\init_done' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$663' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$664' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\ibus_cyc' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$665' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\stage_two_req' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$666' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt_r' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$667' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\opcode' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$668' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op21' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$669' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op26' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$670' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\imm30' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$671' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\funct3' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$672' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op20' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$673' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op22' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$674' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\signbit' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$675' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm24_20' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$676' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm11_7' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$677' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm19_12_20' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$678' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm7' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$679' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm30_25' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$680' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\o_lsb' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$681' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\c_r' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$682' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\data' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$683' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\o_ibus_adr' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$684' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\pc_plus_4_cy_r' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$685' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\pc_plus_offset_cy_r' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$686' with positive edge clock. | |
| Creating register for signal `\serv_alu.\cmp_r' using process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| created $dff cell `$procdff$687' with positive edge clock. | |
| Creating register for signal `\serv_alu.\add_cy_r' using process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| created $dff cell `$procdff$688' with positive edge clock. | |
| Creating register for signal `$paramod\serv_mem_if\WITH_CSR=1.\dat' using process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| created $dff cell `$procdff$689' with positive edge clock. | |
| Creating register for signal `$paramod\serv_mem_if\WITH_CSR=1.\signbit' using process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| created $dff cell `$procdff$690' with positive edge clock. | |
| Creating register for signal `\serv_csr.\o_new_irq' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$691' with positive edge clock. | |
| Creating register for signal `\serv_csr.\timer_irq_r' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$692' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mstatus_mie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$693' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mstatus_mpie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$694' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mcause3_0' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$695' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mie_mtie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$696' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mcause31' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$697' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rdata1' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| created $dff cell `$procdff$698' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wdata0_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| created $dff cell `$procdff$699' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rdata0' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$700' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rcnt' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$701' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rgnt' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$702' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rtrig1' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$703' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rreq_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$704' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wen1_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$705' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wen0_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$706' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wdata1_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$707' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.\o_rdata' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$708' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_DATA' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$709' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_ADDR' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$710' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$711' with positive edge clock. | |
| Creating register for signal `$paramod\servant_mux\sim=0.\o_wb_cpu_ack' using process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| created $dff cell `$procdff$712' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.\o_wb_rdt' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$713' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$714' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$715' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$716' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$717' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$718' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$719' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$720' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$721' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$722' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$723' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$724' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$725' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.\o_wb_ack' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| created $dff cell `$procdff$726' with positive edge clock. | |
| Creating register for signal `\servant_gpio.\o_wb_rdt' using process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| created $dff cell `$procdff$727' with positive edge clock. | |
| Creating register for signal `\servant_gpio.\o_gpio' using process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| created $dff cell `$procdff$728' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\o_irq' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$729' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\mtimecmp' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$730' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\mtime' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$731' with positive edge clock. | |
| Creating register for signal `$paramod\servant_clock_gen\PLL=1313820229.\rst_reg' using process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| created $dff cell `$procdff$732' with positive edge clock. | |
| 24.4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Found and cleaned up 2 empty switches in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Removing empty process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Found and cleaned up 3 empty switches in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Removing empty process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Removing empty process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| Removing empty process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| Found and cleaned up 6 empty switches in `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| Removing empty process `serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| Found and cleaned up 2 empty switches in `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| Removing empty process `serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Removing empty process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Found and cleaned up 1 empty switch in `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| Removing empty process `serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| Found and cleaned up 2 empty switches in `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| Removing empty process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| Found and cleaned up 6 empty switches in `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| Removing empty process `serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| Found and cleaned up 4 empty switches in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| Removing empty process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| Found and cleaned up 2 empty switches in `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| Removing empty process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| Found and cleaned up 4 empty switches in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| Found and cleaned up 1 empty switch in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| Found and cleaned up 1 empty switch in `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| Removing empty process `servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| Found and cleaned up 3 empty switches in `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| Removing empty process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| Removing empty process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| Removing empty process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| Removing empty process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| Cleaned up 41 empty switches. | |
| 24.5. Executing FLATTEN pass (flatten design). | |
| Using template $paramod\servant_clock_gen\PLL=1313820229 for cells of type $paramod\servant_clock_gen\PLL=1313820229. | |
| Using template $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant for cells of type $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant. | |
| Using template servant_gpio for cells of type servant_gpio. | |
| Using template $paramod\servant_mux\sim=0 for cells of type $paramod\servant_mux\sim=0. | |
| Using template $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 for cells of type $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Using template $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 for cells of type $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Using template $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram for cells of type $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Using template servant_arbiter for cells of type servant_arbiter. | |
| Using template $paramod\serv_rf_ram\width=2\csr_regs=4 for cells of type $paramod\serv_rf_ram\width=2\csr_regs=4. | |
| Using template $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 for cells of type $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4. | |
| Using template $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top for cells of type $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top. | |
| Using template $paramod\serv_decode\PRE_REGISTER=1 for cells of type $paramod\serv_decode\PRE_REGISTER=1. | |
| Using template serv_alu for cells of type serv_alu. | |
| Using template $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 for cells of type $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Using template serv_immdec for cells of type serv_immdec. | |
| Using template serv_bufreg for cells of type serv_bufreg. | |
| Using template $paramod\serv_mem_if\WITH_CSR=1 for cells of type $paramod\serv_mem_if\WITH_CSR=1. | |
| Using template $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 for cells of type $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1. | |
| Using template $paramod\serv_rf_if\WITH_CSR=1 for cells of type $paramod\serv_rf_if\WITH_CSR=1. | |
| Using template serv_csr for cells of type serv_csr. | |
| <suppressed ~20 debug messages> | |
| No more expansions possible. | |
| Deleting now unused module $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Deleting now unused module $paramod\serv_decode\PRE_REGISTER=1. | |
| Deleting now unused module serv_immdec. | |
| Deleting now unused module serv_bufreg. | |
| Deleting now unused module $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1. | |
| Deleting now unused module serv_alu. | |
| Deleting now unused module $paramod\serv_rf_if\WITH_CSR=1. | |
| Deleting now unused module $paramod\serv_mem_if\WITH_CSR=1. | |
| Deleting now unused module serv_csr. | |
| Deleting now unused module $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4. | |
| Deleting now unused module $paramod\serv_rf_ram\width=2\csr_regs=4. | |
| Deleting now unused module $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top. | |
| Deleting now unused module servant_arbiter. | |
| Deleting now unused module $paramod\servant_mux\sim=0. | |
| Deleting now unused module $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Deleting now unused module servant_gpio. | |
| Deleting now unused module $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Deleting now unused module $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Deleting now unused module $paramod\servant_clock_gen\PLL=1313820229. | |
| Deleting now unused module $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant. | |
| 24.6. Executing TRIBUF pass. | |
| 24.7. Executing DEMINOUT pass (demote inout ports to input or output). | |
| 24.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~24 debug messages> | |
| 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 3 unused cells and 319 unused wires. | |
| <suppressed ~6 debug messages> | |
| 24.10. Executing CHECK pass (checking for obvious problems). | |
| checking module service.. | |
| found and reported 0 problems. | |
| 24.11. Executing OPT pass (performing simple optimizations). | |
| 24.11.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~201 debug messages> | |
| Removed a total of 67 cells. | |
| 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~77 debug messages> | |
| 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.state.$reduce_or$../src/serv_1.0.2/rtl/serv_state.v:57$443: { \servant.cpu.cpu.state.o_cnt_r [0] \servant.cpu.cpu.state.o_cnt_r [1] \servant.cpu.cpu.state.o_cnt_r [2] \servant.cpu.cpu.state.o_cnt_r [3] } | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.rf_if.$reduce_or$../src/serv_1.0.2/rtl/serv_rf_if.v:52$212: { \servant.cpu.cpu.immdec.imm11_7 [0] \servant.cpu.cpu.immdec.imm11_7 [1] \servant.cpu.cpu.immdec.imm11_7 [2] \servant.cpu.cpu.immdec.imm11_7 [3] \servant.cpu.cpu.immdec.imm11_7 [4] } | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.decode.$reduce_or$../src/serv_1.0.2/rtl/serv_decode.v:120$370: { \servant.cpu.cpu.decode.funct3 [0] \servant.cpu.cpu.decode.funct3 [1] \servant.cpu.cpu.decode.funct3 [2] } | |
| Consolidated identical input bits for $mux cell $techmap\servant.cpu.rf_ram.$procmux$613: | |
| Old ports: A=2'00, B=2'11, Y=$techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [0] | |
| New connections: $techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [1] = $techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [0] | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$623: | |
| Old ports: A=0, B=255, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] | |
| New connections: $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [31:1] = { 24'000000000000000000000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$629: | |
| Old ports: A=0, B=65280, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [31:9] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [7:0] } = { 16'0000000000000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] 8'00000000 } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$635: | |
| Old ports: A=0, B=16711680, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [31:17] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [15:0] } = { 8'00000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] 16'0000000000000000 } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$641: | |
| Old ports: A=0, B=32'11111111000000000000000000000000, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [31:25] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [23:0] } = { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] 24'000000000000000000000000 } | |
| Optimizing cells in module \service. | |
| Performed a total of 8 changes. | |
| 24.11.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.11.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 71 unused wires. | |
| <suppressed ~5 debug messages> | |
| 24.11.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~77 debug messages> | |
| 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.11.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.11.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.11.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.12. Executing WREDUCE pass (reducing word size of cells). | |
| Removed top 25 address bits (of 32) from memory init port service.$techmap\servant.ram.$meminit$\mem$../src/servant_1.0.2/servant/servant_ram.v:43$35 (servant.ram.mem). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.servant_mux.$eq$../src/servant_1.0.2/servant/servant_mux.v:58$48 ($eq). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7 ($add). | |
| Removed top 8 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$722 ($dff). | |
| Removed top 7 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$725 ($dff). | |
| Removed top 16 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$718 ($dff). | |
| Removed top 24 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$714 ($dff). | |
| Removed cell service.$techmap\servant.ram.$procmux$645 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$643 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$639 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$637 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$633 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$631 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$627 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$625 ($mux). | |
| Removed top 23 bits (of 32) from mux cell service.$techmap\servant.arbiter.$ternary$../src/servant_1.0.2/servant/servant_arbiter.v:33$54 ($mux). | |
| Removed top 1 bits (of 2) from FF cell service.$techmap\servant.cpu.rf_ram.$procdff$711 ($dff). | |
| Removed cell service.$techmap\servant.cpu.rf_ram.$procmux$617 ($mux). | |
| Removed cell service.$techmap\servant.cpu.rf_ram.$procmux$615 ($mux). | |
| Removed top 4 bits (of 5) from port B of cell service.$techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79 ($add). | |
| Removed top 30 bits (of 32) from port B of cell service.$techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| Removed top 27 bits (of 32) from port Y of cell service.$techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.decode.$eq$../src/serv_1.0.2/rtl/serv_decode.v:211$428 ($eq). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.decode.$eq$../src/serv_1.0.2/rtl/serv_decode.v:117$367 ($eq). | |
| Removed top 2 bits (of 3) from port B of cell service.$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510 ($add). | |
| Removed top 2 bits (of 3) from port B of cell service.$techmap\servant.cpu.cpu.state.$eq$../src/serv_1.0.2/rtl/serv_state.v:67$455 ($eq). | |
| Removed top 1 bits (of 2) from port A of cell service.$techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| Removed top 31 bits (of 32) from port A of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port A of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$209 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208 ($and). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$207 ($or). | |
| Removed top 26 bits (of 32) from mux cell service.$techmap\servant.cpu.cpu.mem_if.$ternary$../src/serv_1.0.2/rtl/serv_mem_if.v:86$203 ($mux). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| Removed top 26 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$eq$../src/serv_1.0.2/rtl/serv_mem_if.v:53$171 ($eq). | |
| Removed top 1 bits (of 2) from port A of cell service.$techmap\servant.cpu.cpu.rf_if.$or$../src/serv_1.0.2/rtl/serv_rf_if.v:114$231 ($or). | |
| Removed top 4 bits (of 6) from mux cell service.$techmap\servant.cpu.cpu.rf_if.$ternary$../src/serv_1.0.2/rtl/serv_rf_if.v:78$223 ($mux). | |
| Removed cell service.$techmap\servant.cpu.cpu.csr.$ternary$../src/serv_1.0.2/rtl/serv_csr.v:58$91 ($mux). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.csr.$eq$../src/serv_1.0.2/rtl/serv_csr.v:54$84 ($eq). | |
| Removed top 7 bits (of 24) from FF cell service.$techmap\servant.ram.$procdff$722 ($dff). | |
| Removed top 7 bits (of 16) from FF cell service.$techmap\servant.ram.$procdff$718 ($dff). | |
| Removed top 7 bits (of 8) from FF cell service.$techmap\servant.ram.$procdff$714 ($dff). | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208_Y. | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$209_Y. | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$207_Y. | |
| Removed top 26 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199_Y. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA[31:0]$24. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA[31:0]$25. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA[31:0]$29. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN. | |
| Removed top 23 bits (of 32) from wire service.servant.arbiter.o_wb_cpu_adr. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.cpu.o_wreg1. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.cpu.rf_if.o_wreg1. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.rf_ram_if.i_wreg1. | |
| 24.13. Executing PEEPOPT pass (run peephole optimizers). | |
| 24.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 1 unused cells and 32 unused wires. | |
| <suppressed ~2 debug messages> | |
| 24.15. Executing SHARE pass (SAT-based resource sharing). | |
| 24.16. Executing TECHMAP pass (map to technology primitives). | |
| 24.16.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_lut_cmp_'. | |
| Successfully finished Verilog frontend. | |
| 24.16.2. Continuing TECHMAP pass. | |
| Using template $paramod$6816abac91a51b405c3de5bceb2855c03dd44485\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$df71d3c5c306636e78c1ede81ccfd95a4d222f85\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$0760830c1e6c196382cd2cb153e9fff2d84c061d\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$77ad031fce233083715243f95e3cd2547d931e42\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$d87a48a4cd82717ae6bd57e6fe5ce90d87c44016\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$99e5b0ecd4c7f9fb6cd3a733593eba894c42613f\_90_lut_cmp_ for cells of type $eq. | |
| No more expansions possible. | |
| <suppressed ~148 debug messages> | |
| 24.17. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~1 debug messages> | |
| 24.18. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 43 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.19. Executing ALUMACC pass (create $alu and $macc cells). | |
| Extracting $alu and $macc cells in module service: | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$242 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$245 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$266 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$274 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| creating $macc model for $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510 ($add). | |
| creating $macc model for $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79 ($add). | |
| creating $macc model for $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| creating $macc model for $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7 ($add). | |
| merging $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$274 into $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275. | |
| merging $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$266 into $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267. | |
| merging $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 into $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294. | |
| merging $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$245 into $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246. | |
| merging $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$242 into $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294. | |
| creating $alu model for $macc $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246. | |
| creating $alu model for $macc $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243. | |
| creating $alu model for $macc $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7. | |
| creating $alu model for $techmap\servant.timer.$ge$../src/servant_1.0.2/servant/servant_timer.v:30$8 ($ge): new $alu | |
| creating $alu cell for $techmap\servant.timer.$ge$../src/servant_1.0.2/servant/servant_timer.v:30$8: $auto$alumacc.cc:474:replace_alu$771 | |
| creating $alu cell for $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7: $auto$alumacc.cc:474:replace_alu$780 | |
| creating $alu cell for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243: $auto$alumacc.cc:474:replace_alu$783 | |
| creating $alu cell for $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73: $auto$alumacc.cc:474:replace_alu$786 | |
| creating $alu cell for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246: $auto$alumacc.cc:474:replace_alu$789 | |
| creating $alu cell for $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79: $auto$alumacc.cc:474:replace_alu$792 | |
| creating $alu cell for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294: $auto$alumacc.cc:474:replace_alu$795 | |
| creating $alu cell for $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510: $auto$alumacc.cc:474:replace_alu$798 | |
| creating $alu cell for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267: $auto$alumacc.cc:474:replace_alu$801 | |
| creating $alu cell for $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199: $auto$alumacc.cc:474:replace_alu$804 | |
| creating $alu cell for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275: $auto$alumacc.cc:474:replace_alu$807 | |
| created 11 $alu and 0 $macc cells. | |
| 24.20. Executing OPT pass (performing simple optimizations). | |
| 24.20.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~12 debug messages> | |
| Removed a total of 4 cells. | |
| 24.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~69 debug messages> | |
| 24.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$778: { $auto$rtlil.cc:1832:Not$775 $auto$rtlil.cc:1835:ReduceAnd$777 } | |
| New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$776: { $auto$alumacc.cc:490:replace_alu$772 [0] $auto$alumacc.cc:490:replace_alu$772 [1] $auto$alumacc.cc:490:replace_alu$772 [2] $auto$alumacc.cc:490:replace_alu$772 [3] $auto$alumacc.cc:490:replace_alu$772 [4] $auto$alumacc.cc:490:replace_alu$772 [5] $auto$alumacc.cc:490:replace_alu$772 [6] $auto$alumacc.cc:490:replace_alu$772 [7] $auto$alumacc.cc:490:replace_alu$772 [8] $auto$alumacc.cc:490:replace_alu$772 [9] $auto$alumacc.cc:490:replace_alu$772 [10] $auto$alumacc.cc:490:replace_alu$772 [11] $auto$alumacc.cc:490:replace_alu$772 [12] $auto$alumacc.cc:490:replace_alu$772 [13] $auto$alumacc.cc:490:replace_alu$772 [14] $auto$alumacc.cc:490:replace_alu$772 [15] $auto$alumacc.cc:490:replace_alu$772 [16] $auto$alumacc.cc:490:replace_alu$772 [17] $auto$alumacc.cc:490:replace_alu$772 [18] $auto$alumacc.cc:490:replace_alu$772 [19] $auto$alumacc.cc:490:replace_alu$772 [20] $auto$alumacc.cc:490:replace_alu$772 [21] $auto$alumacc.cc:490:replace_alu$772 [22] $auto$alumacc.cc:490:replace_alu$772 [23] $auto$alumacc.cc:490:replace_alu$772 [24] $auto$alumacc.cc:490:replace_alu$772 [25] $auto$alumacc.cc:490:replace_alu$772 [26] $auto$alumacc.cc:490:replace_alu$772 [27] $auto$alumacc.cc:490:replace_alu$772 [28] $auto$alumacc.cc:490:replace_alu$772 [29] $auto$alumacc.cc:490:replace_alu$772 [30] $auto$alumacc.cc:490:replace_alu$772 [31] } | |
| Optimizing cells in module \service. | |
| Performed a total of 2 changes. | |
| 24.20.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.20.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.20.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 5 unused cells and 10 unused wires. | |
| <suppressed ~6 debug messages> | |
| 24.20.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.20.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~69 debug messages> | |
| 24.20.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.20.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.20.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.20.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.20.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.21. Executing FSM pass (extract and optimize FSM). | |
| 24.21.1. Executing FSM_DETECT pass (finding FSMs in design). | |
| 24.21.2. Executing FSM_EXTRACT pass (extracting FSM from design). | |
| 24.21.3. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 24.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.21.5. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 24.21.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). | |
| 24.21.7. Executing FSM_INFO pass (dumping all available information on FSM cells). | |
| 24.21.8. Executing FSM_MAP pass (mapping FSMs to basic logic). | |
| 24.22. Executing OPT pass (performing simple optimizations). | |
| 24.22.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.22.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.22.3. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.22.5. Finished fast OPT passes. | |
| 24.23. Executing MEMORY pass. | |
| 24.23.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). | |
| Checking cell `$techmap\servant.cpu.rf_ram.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$66' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$36' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$37' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$38' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.cpu.rf_ram.$memrd$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:17$65' in module `\service': merged data $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memrd$\mem$../src/servant_1.0.2/servant/servant_ram.v:35$34' in module `\service': merged data $dff to cell. | |
| 24.23.2. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 14 unused cells and 16 unused wires. | |
| <suppressed ~15 debug messages> | |
| 24.23.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). | |
| Consolidating write ports of memory service.servant.ram.mem by address: | |
| New clock domain: posedge \i_clk | |
| Port 0 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$36) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000000000000000000011111111 | |
| Port 1 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$37) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000000000001111111100000000 | |
| Merging port 0 into this one. | |
| Active bits: 00000000000000001111111111111111 | |
| Port 2 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$38) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000111111110000000000000000 | |
| Merging port 1 into this one. | |
| Active bits: 00000000111111111111111111111111 | |
| Port 3 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 11111111000000000000000000000000 | |
| Merging port 2 into this one. | |
| Active bits: 11111111111111111111111111111111 | |
| 24.23.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.23.5. Executing MEMORY_COLLECT pass (generating $mem cells). | |
| Collecting $memrd, $memwr and $meminit for memory `\servant.cpu.rf_ram.memory' in module `\service': | |
| $techmap\servant.cpu.rf_ram.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$66 ($memwr) | |
| $techmap\servant.cpu.rf_ram.$memrd$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:17$65 ($memrd) | |
| Collecting $memrd, $memwr and $meminit for memory `\servant.ram.mem' in module `\service': | |
| $techmap\servant.ram.$meminit$\mem$../src/servant_1.0.2/servant/servant_ram.v:43$35 ($meminit) | |
| $techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39 ($memwr) | |
| $techmap\servant.ram.$memrd$\mem$../src/servant_1.0.2/servant/servant_ram.v:35$34 ($memrd) | |
| 24.24. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). | |
| Processing service.servant.cpu.rf_ram.memory: | |
| Properties: ports=2 bits=1152 rports=1 wports=1 dbits=2 abits=10 words=576 | |
| Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Bram geometry: abits=8 dbits=16 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M0: awaste=192 dwaste=14 bwaste=3968 waste=3968 efficiency=9 | |
| Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3968 efficiency=9 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Bram geometry: abits=9 dbits=8 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=448 dwaste=6 bwaste=3968 waste=3968 efficiency=14 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3968 efficiency=14 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Bram geometry: abits=10 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=448 dwaste=2 bwaste=2944 waste=2944 efficiency=28 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2944 efficiency=28 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Bram geometry: abits=11 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=1472 dwaste=0 bwaste=2944 waste=2944 efficiency=28 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2944 efficiency=28 | |
| Storing for later selection. | |
| Selecting best of 4 rules: | |
| Efficiency for rule 2.3: efficiency=28, cells=1, acells=1 | |
| Efficiency for rule 2.2: efficiency=28, cells=1, acells=1 | |
| Efficiency for rule 2.1: efficiency=14, cells=2, acells=2 | |
| Efficiency for rule 1.1: efficiency=9, cells=3, acells=3 | |
| Selected rule 2.3 with efficiency 28. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: servant.cpu.rf_ram.memory.0.0.0 | |
| Processing service.servant.ram.mem: | |
| Properties: ports=2 bits=4096 rports=1 wports=1 dbits=32 abits=7 words=128 | |
| Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Bram geometry: abits=8 dbits=16 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M0: awaste=128 dwaste=0 bwaste=2048 waste=2048 efficiency=50 | |
| Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2048 efficiency=50 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Bram geometry: abits=9 dbits=8 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=384 dwaste=0 bwaste=3072 waste=3072 efficiency=25 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3072 efficiency=25 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Bram geometry: abits=10 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=896 dwaste=0 bwaste=3584 waste=3584 efficiency=12 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3584 efficiency=12 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Bram geometry: abits=11 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=1920 dwaste=0 bwaste=3840 waste=3840 efficiency=6 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3840 efficiency=6 | |
| Storing for later selection. | |
| Selecting best of 4 rules: | |
| Efficiency for rule 2.3: efficiency=6, cells=16, acells=1 | |
| Efficiency for rule 2.2: efficiency=12, cells=8, acells=1 | |
| Efficiency for rule 2.1: efficiency=25, cells=4, acells=1 | |
| Efficiency for rule 1.1: efficiency=50, cells=2, acells=1 | |
| Selected rule 1.1 with efficiency 50. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: servant.ram.mem.0.0.0 | |
| Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: servant.ram.mem.1.0.0 | |
| 24.26. Executing TECHMAP pass (map to technology primitives). | |
| 24.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K'. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. | |
| Successfully finished Verilog frontend. | |
| 24.26.2. Continuing TECHMAP pass. | |
| Using template $paramod$1cf52d6bf97abd8ac242c98f430558b534970d65\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. | |
| Using template $paramod$f99e76b470b5c9ef85019a34bf48912c9da143c7\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. | |
| Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=11\CFG_DBITS=2\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. | |
| Using template $paramod$302e632eba0ef6d8cd68a4764c637a5431c6a98c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| Using template $paramod$e0a1b09a23541879bdb850ec7d5e406ac4498a7d\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| Using template $paramod$c580e88c60026da015257f05680f05599f0d3ee1\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| No more expansions possible. | |
| <suppressed ~130 debug messages> | |
| 24.27. Executing ICE40_BRAMINIT pass. | |
| 24.28. Executing OPT pass (performing simple optimizations). | |
| 24.28.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~17 debug messages> | |
| 24.28.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.28.3. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 76 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.28.5. Finished fast OPT passes. | |
| 24.29. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). | |
| 24.30. Executing OPT pass (performing simple optimizations). | |
| 24.30.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~64 debug messages> | |
| 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $techmap$techmap825\servant.ram.mem.0.0.0.$reduce_or$/usr/bin/../share/yosys/ice40/brams_map.v:222$824: { \servant.ram.we [0] \servant.ram.we [1] } | |
| New input vector for $reduce_or cell $techmap$techmap822\servant.ram.mem.1.0.0.$reduce_or$/usr/bin/../share/yosys/ice40/brams_map.v:222$821: { \servant.ram.we [2] \servant.ram.we [3] } | |
| Optimizing cells in module \service. | |
| Performed a total of 2 changes. | |
| 24.30.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.30.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~64 debug messages> | |
| 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.30.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.30.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.31. Executing TECHMAP pass (map to technology primitives). | |
| 24.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 24.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. | |
| Generating RTLIL representation for module `\_80_ice40_alu'. | |
| Successfully finished Verilog frontend. | |
| 24.31.3. Continuing TECHMAP pass. | |
| Using extmapper simplemap for cells of type $and. | |
| Using extmapper simplemap for cells of type $dff. | |
| Using extmapper simplemap for cells of type $mux. | |
| Using extmapper simplemap for cells of type $logic_not. | |
| Using extmapper simplemap for cells of type $lut. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $not. | |
| Using extmapper simplemap for cells of type $or. | |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $reduce_and. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=2\Y_WIDTH=5 for cells of type $alu. | |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $reduce_or. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $xor. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $pos. | |
| Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. | |
| Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu. | |
| No more expansions possible. | |
| <suppressed ~900 debug messages> | |
| 24.32. Executing ICE40_OPT pass (performing simple optimizations). | |
| 24.32.1. Running ICE40 specific optimizations. | |
| 24.32.2. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~218 debug messages> | |
| 24.32.3. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~129 debug messages> | |
| Removed a total of 43 cells. | |
| 24.32.4. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.5. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 65 unused cells and 277 unused wires. | |
| <suppressed ~70 debug messages> | |
| 24.32.6. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.32.7. Running ICE40 specific optimizations. | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$780.slice[0].carry: CO=\servant.timer.mtime [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$786.slice[0].carry: CO=\servant.cpu.rf_ram_if.rcnt [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$792.slice[0].carry: CO=\servant.cpu.rf_ram_if.rcnt [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$804.slice[0].carry: CO=\servant.cpu.cpu.mem_if.dat [0] | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$780.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$786.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$792.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$804.slice[1].adder back to logic. | |
| 24.32.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~52 debug messages> | |
| 24.32.9. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~15 debug messages> | |
| Removed a total of 5 cells. | |
| 24.32.10. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.11. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 12 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.32.12. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.32.13. Running ICE40 specific optimizations. | |
| 24.32.14. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.32.15. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.32.16. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.17. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.32.18. Finished OPT passes. (There is nothing left to do.) | |
| 24.33. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). | |
| 24.34. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). | |
| Selected cell types for direct conversion: | |
| $_DFF_PP1_ -> $__DFFE_PP1 | |
| $_DFF_PP0_ -> $__DFFE_PP0 | |
| $_DFF_PN1_ -> $__DFFE_PN1 | |
| $_DFF_PN0_ -> $__DFFE_PN0 | |
| $_DFF_NP1_ -> $__DFFE_NP1 | |
| $_DFF_NP0_ -> $__DFFE_NP0 | |
| $_DFF_NN1_ -> $__DFFE_NN1 | |
| $_DFF_NN0_ -> $__DFFE_NN0 | |
| $_DFF_N_ -> $_DFFE_NP_ | |
| $_DFF_P_ -> $_DFFE_PP_ | |
| Transforming FF to FF+Enable cells in module service: | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1029 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [0] -> \servant.timer.mtimecmp [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1030 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [1] -> \servant.timer.mtimecmp [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1031 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [2] -> \servant.timer.mtimecmp [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1032 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [3] -> \servant.timer.mtimecmp [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1033 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [4] -> \servant.timer.mtimecmp [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1034 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [5] -> \servant.timer.mtimecmp [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1035 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [6] -> \servant.timer.mtimecmp [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1036 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [7] -> \servant.timer.mtimecmp [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1037 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [8] -> \servant.timer.mtimecmp [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1038 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [9] -> \servant.timer.mtimecmp [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1039 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [10] -> \servant.timer.mtimecmp [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1040 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [11] -> \servant.timer.mtimecmp [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1041 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [12] -> \servant.timer.mtimecmp [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1042 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [13] -> \servant.timer.mtimecmp [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1043 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [14] -> \servant.timer.mtimecmp [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1044 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [15] -> \servant.timer.mtimecmp [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1045 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [16] -> \servant.timer.mtimecmp [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1046 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [17] -> \servant.timer.mtimecmp [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1047 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [18] -> \servant.timer.mtimecmp [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1048 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [19] -> \servant.timer.mtimecmp [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1049 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [20] -> \servant.timer.mtimecmp [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1050 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [21] -> \servant.timer.mtimecmp [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1051 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [22] -> \servant.timer.mtimecmp [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1052 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [23] -> \servant.timer.mtimecmp [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1053 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [24] -> \servant.timer.mtimecmp [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1054 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [25] -> \servant.timer.mtimecmp [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1055 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [26] -> \servant.timer.mtimecmp [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1056 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [27] -> \servant.timer.mtimecmp [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1057 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [28] -> \servant.timer.mtimecmp [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1058 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [29] -> \servant.timer.mtimecmp [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1059 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [30] -> \servant.timer.mtimecmp [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1060 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [31] -> \servant.timer.mtimecmp [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1194 to $_DFFE_PP_ for $techmap\servant.cpu.rf_ram_if.$0\rdata1[0:0] -> \servant.cpu.rf_ram_if.rdata1. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1231 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [0] -> \servant.cpu.cpu.decode.funct3 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1232 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [1] -> \servant.cpu.cpu.decode.funct3 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1233 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [2] -> \servant.cpu.cpu.decode.funct3 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1315 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op22[0:0] -> \servant.cpu.cpu.decode.op22. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1316 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op20[0:0] -> \servant.cpu.cpu.decode.op20. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1317 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\imm30[0:0] -> \servant.cpu.cpu.decode.imm30. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1318 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op26[0:0] -> \servant.cpu.cpu.decode.op26. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1319 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op21[0:0] -> \servant.cpu.cpu.decode.op21. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1320 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [0] -> \servant.cpu.cpu.decode.opcode [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1321 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [1] -> \servant.cpu.cpu.decode.opcode [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1322 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [2] -> \servant.cpu.cpu.decode.opcode [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1323 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [3] -> \servant.cpu.cpu.decode.opcode [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1324 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [4] -> \servant.cpu.cpu.decode.opcode [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1453 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.alu.$0\cmp_r[0:0] -> \servant.cpu.cpu.alu.cmp_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1476 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\init_done[0:0] -> \servant.cpu.cpu.state.init_done. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1477 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [0] -> \servant.cpu.cpu.immdec.imm19_12_20 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1478 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [1] -> \servant.cpu.cpu.immdec.imm19_12_20 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1479 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [2] -> \servant.cpu.cpu.immdec.imm19_12_20 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1480 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [3] -> \servant.cpu.cpu.immdec.imm19_12_20 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1481 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [4] -> \servant.cpu.cpu.immdec.imm19_12_20 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1482 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [5] -> \servant.cpu.cpu.immdec.imm19_12_20 [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1483 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [6] -> \servant.cpu.cpu.immdec.imm19_12_20 [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1484 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [7] -> \servant.cpu.cpu.immdec.imm19_12_20 [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1485 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [8] -> \servant.cpu.cpu.immdec.imm19_12_20 [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1491 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\ibus_cyc[0:0] -> \servant.cpu.cpu.state.ibus_cyc. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1495 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\o_ctrl_jump[0:0] -> \servant.cpu.cpu.state.o_ctrl_jump. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1497 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\misalign_trap_sync_r[0:0] -> \servant.cpu.cpu.state.misalign_trap_sync_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1591 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [0] -> \servant.cpu.cpu.immdec.imm30_25 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1592 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [1] -> \servant.cpu.cpu.immdec.imm30_25 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1593 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [2] -> \servant.cpu.cpu.immdec.imm30_25 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1594 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [3] -> \servant.cpu.cpu.immdec.imm30_25 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1595 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [4] -> \servant.cpu.cpu.immdec.imm30_25 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1596 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [5] -> \servant.cpu.cpu.immdec.imm30_25 [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1597 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm7[0:0] -> \servant.cpu.cpu.immdec.imm7. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1598 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [0] -> \servant.cpu.cpu.immdec.imm11_7 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1599 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [1] -> \servant.cpu.cpu.immdec.imm11_7 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1600 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [2] -> \servant.cpu.cpu.immdec.imm11_7 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1601 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [3] -> \servant.cpu.cpu.immdec.imm11_7 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1602 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [4] -> \servant.cpu.cpu.immdec.imm11_7 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1603 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [0] -> \servant.cpu.cpu.immdec.imm24_20 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1604 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [1] -> \servant.cpu.cpu.immdec.imm24_20 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1605 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [2] -> \servant.cpu.cpu.immdec.imm24_20 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1606 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [3] -> \servant.cpu.cpu.immdec.imm24_20 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1607 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [4] -> \servant.cpu.cpu.immdec.imm24_20 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1608 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\signbit[0:0] -> \servant.cpu.cpu.immdec.signbit. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1750 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [0] -> \servant.cpu.cpu.bufreg.data [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1751 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [1] -> \servant.cpu.cpu.bufreg.data [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1752 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [2] -> \servant.cpu.cpu.bufreg.data [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1753 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [3] -> \servant.cpu.cpu.bufreg.data [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1754 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [4] -> \servant.cpu.cpu.bufreg.data [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1755 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [5] -> \servant.cpu.cpu.bufreg.data [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1756 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [6] -> \servant.cpu.cpu.bufreg.data [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1757 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [7] -> \servant.cpu.cpu.bufreg.data [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1758 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [8] -> \servant.cpu.cpu.bufreg.data [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1759 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [9] -> \servant.cpu.cpu.bufreg.data [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1760 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [10] -> \servant.cpu.cpu.bufreg.data [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1761 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [11] -> \servant.cpu.cpu.bufreg.data [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1762 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [12] -> \servant.cpu.cpu.bufreg.data [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1763 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [13] -> \servant.cpu.cpu.bufreg.data [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1764 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [14] -> \servant.cpu.cpu.bufreg.data [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1765 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [15] -> \servant.cpu.cpu.bufreg.data [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1766 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [16] -> \servant.cpu.cpu.bufreg.data [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1767 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [17] -> \servant.cpu.cpu.bufreg.data [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1768 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [18] -> \servant.cpu.cpu.bufreg.data [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1769 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [19] -> \servant.cpu.cpu.bufreg.data [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1770 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [20] -> \servant.cpu.cpu.bufreg.data [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1771 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [21] -> \servant.cpu.cpu.bufreg.data [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1772 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [22] -> \servant.cpu.cpu.bufreg.data [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1773 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [23] -> \servant.cpu.cpu.bufreg.data [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1774 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [24] -> \servant.cpu.cpu.bufreg.data [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1775 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [25] -> \servant.cpu.cpu.bufreg.data [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1776 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [26] -> \servant.cpu.cpu.bufreg.data [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1777 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [27] -> \servant.cpu.cpu.bufreg.data [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1778 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [28] -> \servant.cpu.cpu.bufreg.data [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1779 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [29] -> \servant.cpu.cpu.bufreg.data [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1781 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\o_lsb[1:0] [0] -> \servant.cpu.cpu.bufreg.o_lsb [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1782 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\o_lsb[1:0] [1] -> \servant.cpu.cpu.bufreg.o_lsb [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1799 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [0] -> \servant.cpu.cpu.ctrl.o_ibus_adr [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1800 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [1] -> \servant.cpu.cpu.ctrl.o_ibus_adr [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1801 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [2] -> \servant.cpu.cpu.ctrl.o_ibus_adr [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1802 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [3] -> \servant.cpu.cpu.ctrl.o_ibus_adr [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1803 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [4] -> \servant.cpu.cpu.ctrl.o_ibus_adr [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1804 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [5] -> \servant.cpu.cpu.ctrl.o_ibus_adr [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1805 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [6] -> \servant.cpu.cpu.ctrl.o_ibus_adr [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1806 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [7] -> \servant.cpu.cpu.ctrl.o_ibus_adr [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1807 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [8] -> \servant.cpu.cpu.ctrl.o_ibus_adr [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1808 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [9] -> \servant.cpu.cpu.ctrl.o_ibus_adr [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1809 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [10] -> \servant.cpu.cpu.ctrl.o_ibus_adr [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1810 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [11] -> \servant.cpu.cpu.ctrl.o_ibus_adr [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1811 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [12] -> \servant.cpu.cpu.ctrl.o_ibus_adr [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1812 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [13] -> \servant.cpu.cpu.ctrl.o_ibus_adr [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1813 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [14] -> \servant.cpu.cpu.ctrl.o_ibus_adr [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1814 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [15] -> \servant.cpu.cpu.ctrl.o_ibus_adr [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1815 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [16] -> \servant.cpu.cpu.ctrl.o_ibus_adr [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1816 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [17] -> \servant.cpu.cpu.ctrl.o_ibus_adr [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1817 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [18] -> \servant.cpu.cpu.ctrl.o_ibus_adr [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1818 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [19] -> \servant.cpu.cpu.ctrl.o_ibus_adr [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1819 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [20] -> \servant.cpu.cpu.ctrl.o_ibus_adr [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1820 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [21] -> \servant.cpu.cpu.ctrl.o_ibus_adr [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1821 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [22] -> \servant.cpu.cpu.ctrl.o_ibus_adr [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1822 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [23] -> \servant.cpu.cpu.ctrl.o_ibus_adr [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1823 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [24] -> \servant.cpu.cpu.ctrl.o_ibus_adr [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1824 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [25] -> \servant.cpu.cpu.ctrl.o_ibus_adr [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1825 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [26] -> \servant.cpu.cpu.ctrl.o_ibus_adr [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1826 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [27] -> \servant.cpu.cpu.ctrl.o_ibus_adr [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1827 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [28] -> \servant.cpu.cpu.ctrl.o_ibus_adr [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1828 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [29] -> \servant.cpu.cpu.ctrl.o_ibus_adr [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1829 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [30] -> \servant.cpu.cpu.ctrl.o_ibus_adr [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1830 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [31] -> \servant.cpu.cpu.ctrl.o_ibus_adr [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1831 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\signbit[0:0] -> \servant.cpu.cpu.mem_if.signbit. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1832 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [0] -> \servant.cpu.cpu.mem_if.dat [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1833 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [1] -> \servant.cpu.cpu.mem_if.dat [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1834 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [2] -> \servant.cpu.cpu.mem_if.dat [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1835 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [3] -> \servant.cpu.cpu.mem_if.dat [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1836 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [4] -> \servant.cpu.cpu.mem_if.dat [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1837 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [5] -> \servant.cpu.cpu.mem_if.dat [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1838 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [6] -> \servant.cpu.cpu.mem_if.dat [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1839 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [7] -> \servant.cpu.cpu.mem_if.dat [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1840 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [8] -> \servant.cpu.cpu.mem_if.dat [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1841 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [9] -> \servant.cpu.cpu.mem_if.dat [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1842 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [10] -> \servant.cpu.cpu.mem_if.dat [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1843 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [11] -> \servant.cpu.cpu.mem_if.dat [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1844 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [12] -> \servant.cpu.cpu.mem_if.dat [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1845 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [13] -> \servant.cpu.cpu.mem_if.dat [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1846 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [14] -> \servant.cpu.cpu.mem_if.dat [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1847 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [15] -> \servant.cpu.cpu.mem_if.dat [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1848 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [16] -> \servant.cpu.cpu.mem_if.dat [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1849 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [17] -> \servant.cpu.cpu.mem_if.dat [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1850 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [18] -> \servant.cpu.cpu.mem_if.dat [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1851 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [19] -> \servant.cpu.cpu.mem_if.dat [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1852 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [20] -> \servant.cpu.cpu.mem_if.dat [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1853 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [21] -> \servant.cpu.cpu.mem_if.dat [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1854 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [22] -> \servant.cpu.cpu.mem_if.dat [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1855 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [23] -> \servant.cpu.cpu.mem_if.dat [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1856 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [24] -> \servant.cpu.cpu.mem_if.dat [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1857 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [25] -> \servant.cpu.cpu.mem_if.dat [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1858 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [26] -> \servant.cpu.cpu.mem_if.dat [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1859 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [27] -> \servant.cpu.cpu.mem_if.dat [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1860 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [28] -> \servant.cpu.cpu.mem_if.dat [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1861 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [29] -> \servant.cpu.cpu.mem_if.dat [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1862 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [30] -> \servant.cpu.cpu.mem_if.dat [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1863 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [31] -> \servant.cpu.cpu.mem_if.dat [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2044 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mstatus_mie[0:0] -> \servant.cpu.cpu.csr.mstatus_mie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2095 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause31[0:0] -> \servant.cpu.cpu.csr.mcause31. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2096 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mie_mtie[0:0] -> \servant.cpu.cpu.csr.mie_mtie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2097 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [0] -> \servant.cpu.cpu.csr.mcause3_0 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2098 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [1] -> \servant.cpu.cpu.csr.mcause3_0 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2099 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [2] -> \servant.cpu.cpu.csr.mcause3_0 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2100 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [3] -> \servant.cpu.cpu.csr.mcause3_0 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2101 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mstatus_mpie[0:0] -> \servant.cpu.cpu.csr.mstatus_mpie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2102 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\timer_irq_r[0:0] -> \servant.cpu.cpu.csr.timer_irq_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2103 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\o_new_irq[0:0] -> \servant.cpu.cpu.csr.o_new_irq. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$888 to $_DFFE_PP_ for $techmap\servant.gpio.$0\o_gpio[0:0] -> \servant.gpio.o_gpio. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$998 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtime[31:0] [1] -> \servant.timer.mtime [1]. | |
| 24.35. Executing TECHMAP pass (map to technology primitives). | |
| 24.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DFF_N_'. | |
| Generating RTLIL representation for module `\$_DFF_P_'. | |
| Generating RTLIL representation for module `\$_DFFE_NN_'. | |
| Generating RTLIL representation for module `\$_DFFE_PN_'. | |
| Generating RTLIL representation for module `\$_DFFE_NP_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP_'. | |
| Generating RTLIL representation for module `\$_DFF_NN0_'. | |
| Generating RTLIL representation for module `\$_DFF_NN1_'. | |
| Generating RTLIL representation for module `\$_DFF_PN0_'. | |
| Generating RTLIL representation for module `\$_DFF_PN1_'. | |
| Generating RTLIL representation for module `\$_DFF_NP0_'. | |
| Generating RTLIL representation for module `\$_DFF_NP1_'. | |
| Generating RTLIL representation for module `\$_DFF_PP0_'. | |
| Generating RTLIL representation for module `\$_DFF_PP1_'. | |
| Generating RTLIL representation for module `\$__DFFE_NN0'. | |
| Generating RTLIL representation for module `\$__DFFE_NN1'. | |
| Generating RTLIL representation for module `\$__DFFE_PN0'. | |
| Generating RTLIL representation for module `\$__DFFE_PN1'. | |
| Generating RTLIL representation for module `\$__DFFE_NP0'. | |
| Generating RTLIL representation for module `\$__DFFE_NP1'. | |
| Generating RTLIL representation for module `\$__DFFE_PP0'. | |
| Generating RTLIL representation for module `\$__DFFE_PP1'. | |
| Successfully finished Verilog frontend. | |
| 24.35.2. Continuing TECHMAP pass. | |
| Using template \$_DFF_P_ for cells of type $_DFF_P_. | |
| Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. | |
| No more expansions possible. | |
| <suppressed ~255 debug messages> | |
| 24.36. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~412 debug messages> | |
| 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). | |
| 24.38. Executing ICE40_FFINIT pass (implement FF init values). | |
| Handling FF init values in service. | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$883 (SB_DFF): \clock_gen.rst_reg [0] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$884 (SB_DFF): \clock_gen.rst_reg [1] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$885 (SB_DFF): \clock_gen.rst_reg [2] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$886 (SB_DFF): \clock_gen.rst_reg [3] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$887 (SB_DFF): \clock_gen.rst_reg [4] = 1 | |
| 24.39. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). | |
| Merging set/reset $_MUX_ cells into SB_FFs in service. | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1098 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1001 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1099 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1002 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2002 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1799 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1101 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1004 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1103 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1006 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1198 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [3], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1190 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1104 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1007 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1105 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1008 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1106 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1009 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1108 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1011 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1109 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1012 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1110 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1013 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1111 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1014 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1112 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1015 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1114 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1017 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1115 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1018 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1116 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1019 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1117 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1020 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1119 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1022 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1062 (A=\servant.cpu.cpu.mem_if.dat [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1029 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1120 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1023 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1121 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1024 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1122 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1025 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1123 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1026 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1124 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1027 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1505 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1494 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1118 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1021 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1063 (A=\servant.cpu.cpu.mem_if.dat [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1030 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1064 (A=\servant.cpu.cpu.mem_if.dat [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1031 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1065 (A=\servant.cpu.cpu.mem_if.dat [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1032 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1066 (A=\servant.cpu.cpu.mem_if.dat [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1033 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1067 (A=\servant.cpu.cpu.mem_if.dat [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1034 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1068 (A=\servant.cpu.cpu.mem_if.dat [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1035 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1069 (A=\servant.cpu.cpu.mem_if.dat [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1036 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1071 (A=\servant.cpu.cpu.mem_if.dat [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1038 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1102 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1005 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1072 (A=\servant.cpu.cpu.mem_if.dat [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1039 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1073 (A=\servant.cpu.cpu.mem_if.dat [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1040 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1074 (A=\servant.cpu.cpu.mem_if.dat [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1041 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1075 (A=\servant.cpu.cpu.mem_if.dat [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1042 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1076 (A=\servant.cpu.cpu.mem_if.dat [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1043 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1077 (A=\servant.cpu.cpu.mem_if.dat [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1044 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1078 (A=\servant.cpu.cpu.mem_if.dat [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1045 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1079 (A=\servant.cpu.cpu.mem_if.dat [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1046 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1080 (A=\servant.cpu.cpu.mem_if.dat [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1047 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1081 (A=\servant.cpu.cpu.mem_if.dat [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1048 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1082 (A=\servant.cpu.cpu.mem_if.dat [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1049 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1083 (A=\servant.cpu.cpu.mem_if.dat [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1050 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1084 (A=\servant.cpu.cpu.mem_if.dat [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1051 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1085 (A=\servant.cpu.cpu.mem_if.dat [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1052 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1086 (A=\servant.cpu.cpu.mem_if.dat [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1053 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1087 (A=\servant.cpu.cpu.mem_if.dat [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1054 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1088 (A=\servant.cpu.cpu.mem_if.dat [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1055 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1089 (A=\servant.cpu.cpu.mem_if.dat [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1056 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1090 (A=\servant.cpu.cpu.mem_if.dat [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1057 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1091 (A=\servant.cpu.cpu.mem_if.dat [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1058 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1500 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:126$505_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1476 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1205 (A=\servant.cpu.rf_ram_if.i_rreq, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1184 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1146 (A=$techmap\servant.ram.$and$../src/servant_1.0.2/servant/servant_ram.v:28$20_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1145 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1070 (A=\servant.cpu.cpu.mem_if.dat [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1037 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1196 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [1], B=1'1, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1188 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1195 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [0], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1187 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1197 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [2], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1189 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1199 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [4], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1191 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1208 (A=1'0, B=\servant.cpu.rf_ram.o_rdata [1], S=\servant.cpu.rf_ram_if.rcnt [0]) into $auto$simplemap.cc:420:simplemap_dff$1193 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1206 (A=\servant.cpu.rf_ram_if.rreq_r, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1186 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1510 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:181$524_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1497 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1092 (A=\servant.cpu.cpu.mem_if.dat [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1059 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2003 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1800 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1093 (A=\servant.cpu.cpu.mem_if.dat [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1060 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1125 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1028 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1506 (A=$techmap\servant.cpu.cpu.state.$or$../src/serv_1.0.2/rtl/serv_state.v:157$515_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1486 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1508 (A=\servant.cpu.cpu.state.o_cnt_r [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1488 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1509 (A=\servant.cpu.cpu.state.o_cnt_r [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1489 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1504 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1493 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1113 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1016 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1498 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:127$506_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1495 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1503 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1492 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1107 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1010 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2017 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1814 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1100 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1003 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2024 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1821 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2025 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1822 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2026 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1823 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2027 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1824 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2028 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1825 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2029 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1826 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2030 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1827 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2031 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1828 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2032 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1829 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2033 (A=\servant.cpu.cpu.ctrl.new_pc, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1830 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1507 (A=\servant.cpu.cpu.state.o_cnt_r [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1487 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2004 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1801 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2007 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1804 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2006 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1803 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2008 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1805 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2009 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1806 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2010 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1807 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2011 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1808 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2012 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1809 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2013 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1810 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2014 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1811 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2015 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1812 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2016 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1813 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2019 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1816 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2020 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1817 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2018 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1815 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2023 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1820 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2021 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1818 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1094 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$997 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2022 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1819 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$925 (A=$techmap\servant.servant_mux.$and$../src/servant_1.0.2/servant/servant_mux.v:44$45_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$924 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2005 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1802 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1095 (A=$auto$alumacc.cc:474:replace_alu$771.BB [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$998 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1096 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$999 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1097 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1000 (SB_DFF). | |
| 24.40. Executing ICE40_OPT pass (performing simple optimizations). | |
| 24.40.1. Running ICE40 specific optimizations. | |
| 24.40.2. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~242 debug messages> | |
| 24.40.3. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~102 debug messages> | |
| Removed a total of 34 cells. | |
| 24.40.4. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.5. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 120 unused cells and 1419 unused wires. | |
| <suppressed ~121 debug messages> | |
| 24.40.6. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.40.7. Running ICE40 specific optimizations. | |
| 24.40.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~4 debug messages> | |
| 24.40.9. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.40.10. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.11. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.40.12. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.40.13. Running ICE40 specific optimizations. | |
| 24.40.14. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.40.15. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.40.16. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.17. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.40.18. Finished OPT passes. (There is nothing left to do.) | |
| 24.41. Executing TECHMAP pass (map to technology primitives). | |
| 24.41.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DLATCH_N_'. | |
| Generating RTLIL representation for module `\$_DLATCH_P_'. | |
| Successfully finished Verilog frontend. | |
| 24.41.2. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 24.42. Executing ABC pass (technology mapping using ABC). | |
| 24.42.1. Extracting gate netlist of module `\service' to `<abc-temp-dir>/input.blif'.. | |
| Extracted 682 gates and 929 wires to a netlist network with 245 inputs and 185 outputs. | |
| 24.42.1.1. Executing ABC. | |
| Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1 | |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". | |
| ABC: | |
| ABC: + read_blif <abc-temp-dir>/input.blif | |
| ABC: + read_lut <abc-temp-dir>/lutdefs.txt | |
| ABC: + strash | |
| ABC: + ifraig | |
| ABC: + scorr | |
| ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). | |
| ABC: + dc2 | |
| ABC: + dretime | |
| ABC: + retime | |
| ABC: + strash | |
| ABC: + dch -f | |
| ABC: + if | |
| ABC: + mfs2 | |
| ABC: + lutpack -S 1 | |
| ABC: + dress | |
| ABC: Total number of equiv classes = 292. | |
| ABC: Participating nodes from both networks = 607. | |
| ABC: Participating nodes from the first network = 291. ( 81.97 % of nodes) | |
| ABC: Participating nodes from the second network = 316. ( 89.01 % of nodes) | |
| ABC: Node pairs (any polarity) = 291. ( 81.97 % of names can be moved) | |
| ABC: Node pairs (same polarity) = 233. ( 65.63 % of names can be moved) | |
| ABC: Total runtime = 0.01 sec | |
| ABC: + write_blif <abc-temp-dir>/output.blif | |
| 24.42.1.2. Re-integrating ABC results. | |
| ABC RESULTS: $lut cells: 708 | |
| ABC RESULTS: internal signals: 499 | |
| ABC RESULTS: input signals: 245 | |
| ABC RESULTS: output signals: 185 | |
| Removing temp directory. | |
| Removed 0 unused cells and 859 unused wires. | |
| 24.43. Executing TECHMAP pass (map to technology primitives). | |
| 24.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DFF_N_'. | |
| Generating RTLIL representation for module `\$_DFF_P_'. | |
| Generating RTLIL representation for module `\$_DFFE_NN_'. | |
| Generating RTLIL representation for module `\$_DFFE_PN_'. | |
| Generating RTLIL representation for module `\$_DFFE_NP_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP_'. | |
| Generating RTLIL representation for module `\$_DFF_NN0_'. | |
| Generating RTLIL representation for module `\$_DFF_NN1_'. | |
| Generating RTLIL representation for module `\$_DFF_PN0_'. | |
| Generating RTLIL representation for module `\$_DFF_PN1_'. | |
| Generating RTLIL representation for module `\$_DFF_NP0_'. | |
| Generating RTLIL representation for module `\$_DFF_NP1_'. | |
| Generating RTLIL representation for module `\$_DFF_PP0_'. | |
| Generating RTLIL representation for module `\$_DFF_PP1_'. | |
| Generating RTLIL representation for module `\$__DFFE_NN0'. | |
| Generating RTLIL representation for module `\$__DFFE_NN1'. | |
| Generating RTLIL representation for module `\$__DFFE_PN0'. | |
| Generating RTLIL representation for module `\$__DFFE_PN1'. | |
| Generating RTLIL representation for module `\$__DFFE_NP0'. | |
| Generating RTLIL representation for module `\$__DFFE_NP1'. | |
| Generating RTLIL representation for module `\$__DFFE_PP0'. | |
| Generating RTLIL representation for module `\$__DFFE_PP1'. | |
| Generating RTLIL representation for module `\$lut'. | |
| Successfully finished Verilog frontend. | |
| 24.43.2. Continuing TECHMAP pass. | |
| Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111101011000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00011100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101010101100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0101000011001111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110100010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111000100010111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111001000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100001101110101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001011101110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110100000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. | |
| No more expansions possible. | |
| <suppressed ~1498 debug messages> | |
| Removed 0 unused cells and 708 unused wires. | |
| 24.44. Executing HIERARCHY pass (managing design hierarchy). | |
| 24.44.1. Analyzing design hierarchy.. | |
| Top module: \service | |
| 24.44.2. Analyzing design hierarchy.. | |
| Top module: \service | |
| Removed 0 unused modules. | |
| 24.45. Printing statistics. | |
| === service === | |
| Number of wires: 673 | |
| Number of wire bits: 2510 | |
| Number of public wires: 334 | |
| Number of public wire bits: 2046 | |
| Number of memories: 0 | |
| Number of memory bits: 0 | |
| Number of processes: 0 | |
| Number of cells: 733 | |
| SB_CARRY 74 | |
| SB_DFF 20 | |
| SB_DFFE 119 | |
| SB_DFFESR 68 | |
| SB_DFFSR 47 | |
| SB_DFFSS 1 | |
| SB_LUT4 401 | |
| SB_RAM40_4K 3 | |
| 24.46. Executing CHECK pass (checking for obvious problems). | |
| checking module service.. | |
| found and reported 0 problems. | |
| 25. Executing BLIF backend. | |
| 26. Executing JSON backend. | |
| 27. Executing EDIF backend. | |
| Warning: Bit 0 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 1 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 2 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 3 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 4 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 5 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 6 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 7 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 8 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 9 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 10 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 11 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 12 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 13 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 14 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 15 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 0 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 1 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 2 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 4 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 5 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 6 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 7 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 8 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 9 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 10 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 12 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 13 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 14 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 15 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warnings: 30 unique messages, 30 total | |
| End of script. Logfile hash: 90989b5104 | |
| CPU: user 1.99s system 0.05s, MEM: 80.79 MB total, 63.09 MB resident | |
| Yosys 0.9 (git sha1 1979e0b) | |
| Time spent: 25% 23x opt_clean (0 sec), 12% 22x opt_expr (0 sec), ... | |
| make[1]: Leaving directory '/home/dave/Shared/verilog/serv/build/servant_1.0.2/go_board-icestorm' | |
| nextpnr-ice40 -l next.log --hx1k --package vq100 --freq 20 --pcf ../src/servant_1.0.2/data/go_board.pcf --json servant_1.0.2.json --asc servant_1.0.2_next.asc | |
| Info: constrained 'i_clk' to bel 'X0/Y8/io1' | |
| Info: constrained 'q' to bel 'X13/Y6/io1' | |
| Info: Packing constants.. | |
| Info: Packing IOs.. | |
| Info: Packing LUT-FFs.. | |
| Info: 277 LCs used as LUT4 only | |
| Info: 124 LCs used as LUT4 and DFF | |
| Info: Packing non-LUT FFs.. | |
| Info: 131 LCs used as DFF only | |
| Info: Packing carries.. | |
| Info: 37 LCs used as CARRY only | |
| Info: Packing RAMs.. | |
| Info: Placing PLLs.. | |
| Info: Packing special functions.. | |
| Info: Packing PLLs.. | |
| Info: Promoting globals.. | |
| Info: promoting i_clk$SB_IO_IN (fanout 261) | |
| Info: promoting wb_rst [reset] (fanout 110) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$2577 [cen] (fanout 32) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$3342 [cen] (fanout 32) | |
| Info: promoting $abc$4115$auto$dff2dffe.cc:158:make_patterns_logic$3540 [cen] (fanout 31) | |
| Info: promoting servant.cpu.cpu.bufreg_en [cen] (fanout 30) | |
| Info: Constraining chains... | |
| Info: 4 LCs used to legalise carry chains. | |
| Info: Checksum: 0x728f8cdb | |
| Info: Annotating ports with timing budgets for target frequency 20.00 MHz | |
| Info: Checksum: 0x628109ce | |
| Info: Device utilisation: | |
| Info: ICESTORM_LC: 575/ 1280 44% | |
| Info: ICESTORM_RAM: 3/ 16 18% | |
| Info: SB_IO: 2/ 112 1% | |
| Info: SB_GB: 6/ 8 75% | |
| Info: ICESTORM_PLL: 0/ 1 0% | |
| Info: SB_WARMBOOT: 0/ 1 0% | |
| Info: Placed 2 cells based on constraints. | |
| Info: Creating initial analytic placement for 505 cells, random placement wirelen = 7577. | |
| Info: at initial placer iter 0, wirelen = 302 | |
| Info: at initial placer iter 1, wirelen = 338 | |
| Info: at initial placer iter 2, wirelen = 332 | |
| Info: at initial placer iter 3, wirelen = 365 | |
| Info: Running main analytical placer. | |
| Info: at iteration #1, type ALL: wirelen solved = 360, spread = 3245, legal = 3527; time = 0.01s | |
| Info: at iteration #2, type ALL: wirelen solved = 117, spread = 2382, legal = 2948; time = 0.01s | |
| Info: at iteration #3, type ALL: wirelen solved = 168, spread = 2443, legal = 2987; time = 0.01s | |
| Info: at iteration #4, type ALL: wirelen solved = 269, spread = 2324, legal = 3039; time = 0.01s | |
| Info: at iteration #5, type ALL: wirelen solved = 343, spread = 2288, legal = 2874; time = 0.01s | |
| Info: at iteration #6, type ALL: wirelen solved = 377, spread = 2414, legal = 3005; time = 0.01s | |
| Info: at iteration #7, type ALL: wirelen solved = 409, spread = 2257, legal = 2833; time = 0.01s | |
| Info: at iteration #8, type ALL: wirelen solved = 407, spread = 2220, legal = 2971; time = 0.01s | |
| Info: at iteration #9, type ALL: wirelen solved = 426, spread = 2245, legal = 2842; time = 0.01s | |
| Info: at iteration #10, type ALL: wirelen solved = 595, spread = 2227, legal = 2891; time = 0.01s | |
| Info: at iteration #11, type ALL: wirelen solved = 588, spread = 1983, legal = 2862; time = 0.01s | |
| Info: at iteration #12, type ALL: wirelen solved = 613, spread = 1919, legal = 2684; time = 0.01s | |
| Info: at iteration #13, type ALL: wirelen solved = 647, spread = 1819, legal = 2495; time = 0.01s | |
| Info: at iteration #14, type ALL: wirelen solved = 686, spread = 2120, legal = 3039; time = 0.01s | |
| Info: at iteration #15, type ALL: wirelen solved = 822, spread = 2248, legal = 2885; time = 0.01s | |
| Info: at iteration #16, type ALL: wirelen solved = 893, spread = 1809, legal = 2375; time = 0.01s | |
| Info: at iteration #17, type ALL: wirelen solved = 792, spread = 1787, legal = 2544; time = 0.01s | |
| Info: at iteration #18, type ALL: wirelen solved = 764, spread = 1719, legal = 2382; time = 0.01s | |
| Info: at iteration #19, type ALL: wirelen solved = 814, spread = 1994, legal = 2467; time = 0.01s | |
| Info: at iteration #20, type ALL: wirelen solved = 969, spread = 2027, legal = 2699; time = 0.01s | |
| Info: at iteration #21, type ALL: wirelen solved = 1020, spread = 2004, legal = 2450; time = 0.01s | |
| Info: HeAP Placer Time: 0.29s | |
| Info: of which solving equations: 0.16s | |
| Info: of which spreading cells: 0.02s | |
| Info: of which strict legalisation: 0.06s | |
| Info: Running simulated annealing placer for refinement. | |
| Info: at iteration #1: temp = 0.000000, timing cost = 50, wirelen = 2375 | |
| Info: at iteration #5: temp = 0.000000, timing cost = 85, wirelen = 1994 | |
| Info: at iteration #10: temp = 0.000000, timing cost = 78, wirelen = 1871 | |
| Info: at iteration #15: temp = 0.000000, timing cost = 77, wirelen = 1812 | |
| Info: at iteration #20: temp = 0.000000, timing cost = 66, wirelen = 1775 | |
| Info: at iteration #21: temp = 0.000000, timing cost = 66, wirelen = 1769 | |
| Info: SA placement time 0.28s | |
| Info: Max frequency for clock 'i_clk$SB_IO_IN_$glb_clk': 93.82 MHz (PASS at 20.00 MHz) | |
| Info: Max delay posedge i_clk$SB_IO_IN_$glb_clk -> <async>: 1.89 ns | |
| Info: Slack histogram: | |
| Info: legend: * represents 2 endpoint(s) | |
| Info: + represents [1,2) endpoint(s) | |
| Info: [ 39341, 39813) |+ | |
| Info: [ 39813, 40285) |*******+ | |
| Info: [ 40285, 40757) |*****+ | |
| Info: [ 40757, 41229) |******+ | |
| Info: [ 41229, 41701) |****************+ | |
| Info: [ 41701, 42173) |************+ | |
| Info: [ 42173, 42645) |******+ | |
| Info: [ 42645, 43117) |*******+ | |
| Info: [ 43117, 43589) |*******************+ | |
| Info: [ 43589, 44061) |*****+ | |
| Info: [ 44061, 44533) |********************+ | |
| Info: [ 44533, 45005) |**********************************************+ | |
| Info: [ 45005, 45477) |********************+ | |
| Info: [ 45477, 45949) |************+ | |
| Info: [ 45949, 46421) |***************+ | |
| Info: [ 46421, 46893) |*******+ | |
| Info: [ 46893, 47365) |**+ | |
| Info: [ 47365, 47837) |***************************+ | |
| Info: [ 47837, 48309) |******************+ | |
| Info: [ 48309, 48781) |************************************************************ | |
| Info: Checksum: 0x598a83f1 | |
| Info: Routing.. | |
| Info: Setting up routing queue. | |
| Info: Routing 1786 arcs. | |
| Info: | (re-)routed arcs | delta | remaining| time spent | | |
| Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| | |
| Info: 1000 | 64 869 | 64 869 | 861| 0.08 0.08| | |
| Info: 2000 | 247 1686 | 183 817 | 118| 0.12 0.20| | |
| Info: 2137 | 262 1809 | 15 123 | 0| 0.02 0.22| | |
| Info: Routing complete. | |
| Info: Router1 time 0.22s | |
| Info: Checksum: 0x8f9e4037 | |
| Info: Critical path report for clock 'i_clk$SB_IO_IN_$glb_clk' (posedge -> posedge): | |
| Info: curr total | |
| Info: 2.1 2.1 Source servant.cpu.rf_ram.memory.0.0.0_RAM.RDATA_3 | |
| Info: 0.6 2.7 Net servant.cpu.rdata[0] budget 7.457000 ns (3,7) -> (4,6) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4230_LC.I1 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:82 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v:30 | |
| Info: 0.4 3.1 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4230_LC.O | |
| Info: 1.0 4.1 Net $abc$4115$servant.cpu.cpu.ctrl.i_csr_pc_new_inv_ budget 7.456000 ns (4,6) -> (4,5) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4229_LC.I2 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:305 | |
| Info: ../src/serv_1.0.2/rtl/serv_ctrl.v:23 | |
| Info: 0.4 4.5 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4229_LC.O | |
| Info: 1.3 5.7 Net $abc$4115$servant.cpu.cpu.alu.i_op_b_new_inv_ budget 4.971000 ns (4,5) -> (2,3) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4228_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:17 | |
| Info: 0.4 6.2 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4228_LC.O | |
| Info: 0.6 6.8 Net $abc$4115$techmap\servant.cpu.cpu.alu.$logic_not$../src/serv_1.0.2/rtl/serv_alu.v:38$247_Y_new_inv_ budget 4.971000 ns (2,3) -> (2,4) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4227_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:38 | |
| Info: 0.4 7.2 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4227_LC.O | |
| Info: 0.6 7.8 Net $abc$4115$techmap\servant.cpu.cpu.alu.$and$../src/serv_1.0.2/rtl/serv_alu.v:57$257_Y_new_ budget 4.971000 ns (2,4) -> (2,4) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4226_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:333 | |
| Info: ../src/serv_1.0.2/rtl/serv_alu.v:57 | |
| Info: 0.4 8.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4226_LC.O | |
| Info: 0.6 8.9 Net $abc$4115$techmap\servant.cpu.cpu.rf_if.$and$../src/serv_1.0.2/rtl/serv_rf_if.v:57$214_Y_new_ budget 4.971000 ns (2,4) -> (2,5) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4224_LC.I0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:119 | |
| Info: ../src/serv_1.0.2/rtl/serv_top.v:352 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_if.v:57 | |
| Info: 0.4 9.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4224_LC.O | |
| Info: 0.6 9.9 Net $abc$4115$new_n548_ budget 4.970000 ns (2,5) -> (2,6) | |
| Info: Sink $abc$4115$auto$blifparse.cc:492:parse_blif$4248_LC.I0 | |
| Info: 0.4 10.3 Source $abc$4115$auto$blifparse.cc:492:parse_blif$4248_LC.O | |
| Info: 1.0 11.3 Net servant.cpu.wdata[1] budget 4.970000 ns (2,6) -> (3,7) | |
| Info: Sink servant.cpu.rf_ram.memory.0.0.0_RAM.WDATA_11 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:149 | |
| Info: ../src/serv_1.0.2/rtl/serv_rf_top.v:77 | |
| Info: 0.1 11.4 Setup servant.cpu.rf_ram.memory.0.0.0_RAM.WDATA_11 | |
| Info: 5.3 ns logic, 6.1 ns routing | |
| Info: Critical path report for cross-domain path 'posedge i_clk$SB_IO_IN_$glb_clk' -> '<async>': | |
| Info: curr total | |
| Info: 0.5 0.5 Source $auto$simplemap.cc:420:simplemap_dff$888_DFFLC.O | |
| Info: 1.3 1.8 Net q$SB_IO_OUT budget 49.459999 ns (11,3) -> (13,6) | |
| Info: Sink q$sb_io.D_OUT_0 | |
| Info: Defined in: | |
| Info: ../src/servant_1.0.2/servant/service.v:20 | |
| Info: ../src/servant_1.0.2/servant/servant.v:6 | |
| Info: 0.5 ns logic, 1.3 ns routing | |
| Info: Max frequency for clock 'i_clk$SB_IO_IN_$glb_clk': 87.76 MHz (PASS at 20.00 MHz) | |
| Info: Max delay posedge i_clk$SB_IO_IN_$glb_clk -> <async>: 1.81 ns | |
| Info: Slack histogram: | |
| Info: legend: * represents 2 endpoint(s) | |
| Info: + represents [1,2) endpoint(s) | |
| Info: [ 38605, 39114) |+ | |
| Info: [ 39114, 39623) |+ | |
| Info: [ 39623, 40132) |*+ | |
| Info: [ 40132, 40641) |**+ | |
| Info: [ 40641, 41150) |***********+ | |
| Info: [ 41150, 41659) |***+ | |
| Info: [ 41659, 42168) |********+ | |
| Info: [ 42168, 42677) |**************+ | |
| Info: [ 42677, 43186) |****************************** | |
| Info: [ 43186, 43695) |****************+ | |
| Info: [ 43695, 44204) |****+ | |
| Info: [ 44204, 44713) |*************************+ | |
| Info: [ 44713, 45222) |************ | |
| Info: [ 45222, 45731) |**********+ | |
| Info: [ 45731, 46240) |*********************+ | |
| Info: [ 46240, 46749) |********************************************+ | |
| Info: [ 46749, 47258) |*****+ | |
| Info: [ 47258, 47767) |*********************+ | |
| Info: [ 47767, 48276) |********************+ | |
| Info: [ 48276, 48785) |************************************************************ | |
| Info: Program finished normally. | |
| icepack servant_1.0.2_next.asc servant_1.0.2.bin | |
| INFO: Running | |
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| /----------------------------------------------------------------------------\ | |
| | | | |
| | yosys -- Yosys Open SYnthesis Suite | | |
| | | | |
| | Copyright (C) 2012 - 2019 Clifford Wolf <[email protected]> | | |
| | | | |
| | Permission to use, copy, modify, and/or distribute this software for any | | |
| | purpose with or without fee is hereby granted, provided that the above | | |
| | copyright notice and this permission notice appear in all copies. | | |
| | | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | |
| | | | |
| \----------------------------------------------------------------------------/ | |
| Yosys 0.9 (git sha1 1979e0b) | |
| -- Running command `tcl edalize_yosys_template.tcl' -- | |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. | |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. | |
| 1. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_bufreg.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_bufreg.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_bufreg'. | |
| Successfully finished Verilog frontend. | |
| 2. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_alu.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_alu.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_alu'. | |
| Successfully finished Verilog frontend. | |
| 3. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_csr.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_csr.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_csr'. | |
| Successfully finished Verilog frontend. | |
| 4. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_ctrl.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_ctrl.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_ctrl'. | |
| Successfully finished Verilog frontend. | |
| 5. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_decode.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_decode.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_decode'. | |
| Successfully finished Verilog frontend. | |
| 6. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_immdec.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_immdec.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_immdec'. | |
| Successfully finished Verilog frontend. | |
| 7. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_mem_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_mem_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_mem_if'. | |
| Successfully finished Verilog frontend. | |
| 8. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_if'. | |
| Successfully finished Verilog frontend. | |
| 9. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_ram_if.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_ram_if.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_ram_if'. | |
| Successfully finished Verilog frontend. | |
| 10. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_ram.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_ram.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_ram'. | |
| Successfully finished Verilog frontend. | |
| 11. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_state.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_state.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_state'. | |
| Successfully finished Verilog frontend. | |
| 12. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_top.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_top.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_top'. | |
| Successfully finished Verilog frontend. | |
| 13. Executing Verilog-2005 frontend: ../src/serv_1.0.2/rtl/serv_rf_top.v | |
| Parsing Verilog input from `../src/serv_1.0.2/rtl/serv_rf_top.v' to AST representation. | |
| Storing AST representation for module `$abstract\serv_rf_top'. | |
| Successfully finished Verilog frontend. | |
| 14. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_clock_gen.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_clock_gen.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_clock_gen'. | |
| Successfully finished Verilog frontend. | |
| 15. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_timer.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_timer.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_timer'. | |
| Successfully finished Verilog frontend. | |
| 16. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_gpio.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_gpio.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_gpio'. | |
| Successfully finished Verilog frontend. | |
| 17. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_arbiter.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_arbiter.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_arbiter'. | |
| Successfully finished Verilog frontend. | |
| 18. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_mux.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_mux.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_mux'. | |
| Successfully finished Verilog frontend. | |
| 19. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant_ram.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant_ram.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant_ram'. | |
| Successfully finished Verilog frontend. | |
| 20. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/servant.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/servant.v' to AST representation. | |
| Storing AST representation for module `$abstract\servant'. | |
| Successfully finished Verilog frontend. | |
| 21. Executing Verilog-2005 frontend: ../src/servant_1.0.2/servant/service.v | |
| Parsing Verilog input from `../src/servant_1.0.2/servant/service.v' to AST representation. | |
| Storing AST representation for module `$abstract\service'. | |
| Successfully finished Verilog frontend. | |
| 22. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Generating RTLIL representation for module `$paramod$2a32106e1ec3373ac1e5a9aebce3a711b7475215\service'. | |
| 23. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Parameter \memsize = 512 | |
| Generating RTLIL representation for module `$paramod\service\memsize=512'. | |
| 24. Executing SYNTH_ICE40 pass. | |
| 24.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. | |
| Generating RTLIL representation for module `\SB_IO'. | |
| Generating RTLIL representation for module `\SB_GB_IO'. | |
| Generating RTLIL representation for module `\SB_GB'. | |
| Generating RTLIL representation for module `\SB_LUT4'. | |
| Generating RTLIL representation for module `\SB_CARRY'. | |
| Generating RTLIL representation for module `\SB_DFF'. | |
| Generating RTLIL representation for module `\SB_DFFE'. | |
| Generating RTLIL representation for module `\SB_DFFSR'. | |
| Generating RTLIL representation for module `\SB_DFFR'. | |
| Generating RTLIL representation for module `\SB_DFFSS'. | |
| Generating RTLIL representation for module `\SB_DFFS'. | |
| Generating RTLIL representation for module `\SB_DFFESR'. | |
| Generating RTLIL representation for module `\SB_DFFER'. | |
| Generating RTLIL representation for module `\SB_DFFESS'. | |
| Generating RTLIL representation for module `\SB_DFFES'. | |
| Generating RTLIL representation for module `\SB_DFFN'. | |
| Generating RTLIL representation for module `\SB_DFFNE'. | |
| Generating RTLIL representation for module `\SB_DFFNSR'. | |
| Generating RTLIL representation for module `\SB_DFFNR'. | |
| Generating RTLIL representation for module `\SB_DFFNSS'. | |
| Generating RTLIL representation for module `\SB_DFFNS'. | |
| Generating RTLIL representation for module `\SB_DFFNESR'. | |
| Generating RTLIL representation for module `\SB_DFFNER'. | |
| Generating RTLIL representation for module `\SB_DFFNESS'. | |
| Generating RTLIL representation for module `\SB_DFFNES'. | |
| Generating RTLIL representation for module `\SB_RAM40_4K'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNR'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNW'. | |
| Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. | |
| Generating RTLIL representation for module `\ICESTORM_LC'. | |
| Generating RTLIL representation for module `\SB_PLL40_CORE'. | |
| Generating RTLIL representation for module `\SB_PLL40_PAD'. | |
| Generating RTLIL representation for module `\SB_PLL40_2_PAD'. | |
| Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. | |
| Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. | |
| Generating RTLIL representation for module `\SB_WARMBOOT'. | |
| Generating RTLIL representation for module `\SB_SPRAM256KA'. | |
| Generating RTLIL representation for module `\SB_HFOSC'. | |
| Generating RTLIL representation for module `\SB_LFOSC'. | |
| Generating RTLIL representation for module `\SB_RGBA_DRV'. | |
| Generating RTLIL representation for module `\SB_LED_DRV_CUR'. | |
| Generating RTLIL representation for module `\SB_RGB_DRV'. | |
| Generating RTLIL representation for module `\SB_I2C'. | |
| Generating RTLIL representation for module `\SB_SPI'. | |
| Generating RTLIL representation for module `\SB_LEDDA_IP'. | |
| Generating RTLIL representation for module `\SB_FILTER_50NS'. | |
| Generating RTLIL representation for module `\SB_IO_I3C'. | |
| Generating RTLIL representation for module `\SB_IO_OD'. | |
| Generating RTLIL representation for module `\SB_MAC16'. | |
| Successfully finished Verilog frontend. | |
| 24.2. Executing HIERARCHY pass (managing design hierarchy). | |
| 24.3. Executing AST frontend in derive mode using pre-parsed AST for module `\service'. | |
| Generating RTLIL representation for module `\service'. | |
| 24.3.1. Analyzing design hierarchy.. | |
| Top module: \service | |
| 24.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\servant'. | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Parameter \memsize = 512 | |
| Generating RTLIL representation for module `$paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant'. | |
| 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_clock_gen'. | |
| Parameter \PLL = 1313820229 | |
| Generating RTLIL representation for module `$paramod\servant_clock_gen\PLL=1313820229'. | |
| 24.3.4. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_timer'. | |
| Parameter \WIDTH = 32 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Generating RTLIL representation for module `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801'. | |
| Note: Assuming pure combinatorial block at ../src/servant_1.0.2/servant/servant_timer.v:21 in | |
| compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending | |
| use of @* instead of @(...) for better match of synthesis and simulation. | |
| 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_top'. | |
| Parameter \RESET_PC = 0 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1'. | |
| 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_gpio'. | |
| Generating RTLIL representation for module `\servant_gpio'. | |
| 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_ram'. | |
| Parameter \depth = 512 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \memfile = 80'01100010011011000110100101101110011010110111100100101110011010000110010101111000 | |
| Generating RTLIL representation for module `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram'. | |
| Preloading $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram from blinky.hex | |
| 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_mux'. | |
| Parameter 1 (\sim) = 0 | |
| Generating RTLIL representation for module `$paramod\servant_mux\sim=0'. | |
| 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\servant_arbiter'. | |
| Generating RTLIL representation for module `\servant_arbiter'. | |
| 24.3.11. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_top'. | |
| Parameter \WITH_CSR = 1 | |
| Parameter \PRE_REGISTER = 1 | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \RESET_PC = 0 | |
| Generating RTLIL representation for module `$paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top'. | |
| 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_ram'. | |
| Parameter \width = 2 | |
| Parameter \csr_regs = 4 | |
| Generating RTLIL representation for module `$paramod\serv_rf_ram\width=2\csr_regs=4'. | |
| 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_ram_if'. | |
| Parameter \width = 2 | |
| Parameter \reset_strategy = 1296649801 | |
| Parameter \csr_regs = 4 | |
| Generating RTLIL representation for module `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4'. | |
| 24.3.15. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_csr'. | |
| Generating RTLIL representation for module `\serv_csr'. | |
| 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_mem_if'. | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_mem_if\WITH_CSR=1'. | |
| 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_rf_if'. | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_rf_if\WITH_CSR=1'. | |
| 24.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_alu'. | |
| Generating RTLIL representation for module `\serv_alu'. | |
| 24.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_ctrl'. | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \RESET_PC = 0 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1'. | |
| 24.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_bufreg'. | |
| Generating RTLIL representation for module `\serv_bufreg'. | |
| 24.3.22. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_immdec'. | |
| Generating RTLIL representation for module `\serv_immdec'. | |
| 24.3.23. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_decode'. | |
| Parameter \PRE_REGISTER = 1 | |
| Generating RTLIL representation for module `$paramod\serv_decode\PRE_REGISTER=1'. | |
| 24.3.24. Executing AST frontend in derive mode using pre-parsed AST for module `\serv_state'. | |
| Parameter \RESET_STRATEGY = 1296649801 | |
| Parameter \WITH_CSR = 1 | |
| Generating RTLIL representation for module `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1'. | |
| 24.3.25. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: \serv_csr | |
| Used module: $paramod\serv_mem_if\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_if\WITH_CSR=1 | |
| Used module: \serv_alu | |
| Used module: $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 | |
| Used module: \serv_bufreg | |
| Used module: \serv_immdec | |
| Used module: $paramod\serv_decode\PRE_REGISTER=1 | |
| Used module: $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| 24.3.26. Analyzing design hierarchy.. | |
| Top module: \service | |
| Used module: $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant | |
| Used module: $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 | |
| Used module: $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top | |
| Used module: \serv_csr | |
| Used module: $paramod\serv_mem_if\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_if\WITH_CSR=1 | |
| Used module: \serv_alu | |
| Used module: $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 | |
| Used module: \serv_bufreg | |
| Used module: \serv_immdec | |
| Used module: $paramod\serv_decode\PRE_REGISTER=1 | |
| Used module: $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 | |
| Used module: $paramod\serv_rf_ram\width=2\csr_regs=4 | |
| Used module: $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 | |
| Used module: \servant_gpio | |
| Used module: $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram | |
| Used module: $paramod\servant_mux\sim=0 | |
| Used module: \servant_arbiter | |
| Used module: $paramod\servant_clock_gen\PLL=1313820229 | |
| Removing unused module `$abstract\service'. | |
| Removing unused module `$abstract\servant'. | |
| Removing unused module `$abstract\servant_ram'. | |
| Removing unused module `$abstract\servant_mux'. | |
| Removing unused module `$abstract\servant_arbiter'. | |
| Removing unused module `$abstract\servant_gpio'. | |
| Removing unused module `$abstract\servant_timer'. | |
| Removing unused module `$abstract\servant_clock_gen'. | |
| Removing unused module `$abstract\serv_rf_top'. | |
| Removing unused module `$abstract\serv_top'. | |
| Removing unused module `$abstract\serv_state'. | |
| Removing unused module `$abstract\serv_rf_ram'. | |
| Removing unused module `$abstract\serv_rf_ram_if'. | |
| Removing unused module `$abstract\serv_rf_if'. | |
| Removing unused module `$abstract\serv_mem_if'. | |
| Removing unused module `$abstract\serv_immdec'. | |
| Removing unused module `$abstract\serv_decode'. | |
| Removing unused module `$abstract\serv_ctrl'. | |
| Removing unused module `$abstract\serv_csr'. | |
| Removing unused module `$abstract\serv_alu'. | |
| Removing unused module `$abstract\serv_bufreg'. | |
| Removed 21 unused modules. | |
| 24.4. Executing PROC pass (convert processes to netlists). | |
| 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Found and cleaned up 1 empty switch in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:65$287'. | |
| Removing empty process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:65$287'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Found and cleaned up 1 empty switch in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:38$40'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:38$40'. | |
| Cleaned up 6 empty switches. | |
| 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). | |
| Marked 1 switch rules as full_case in process $proc$../src/servant_1.0.2/servant/servant_ram.v:24$17 in module $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Marked 1 switch rules as full_case in process $proc$../src/servant_1.0.2/servant/servant_timer.v:26$5 in module $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Removed a total of 0 dead cases. | |
| 24.4.3. Executing PROC_INIT pass (extract init attributes). | |
| Found init rule in `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| Set init value: \rst_reg = 5'11111 | |
| 24.4.4. Executing PROC_ARST pass (detect async resets in processes). | |
| 24.4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). | |
| Creating decoders for process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| 1/1: $0\misalign_trap_sync_r[0:0] | |
| Creating decoders for process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| 1/7: $0\o_cnt_r[3:0] | |
| 2/7: $0\o_cnt[2:0] | |
| 3/7: $0\stage_two_req[0:0] | |
| 4/7: $0\o_cnt_done[0:0] | |
| 5/7: $0\ibus_cyc[0:0] | |
| 6/7: $0\init_done[0:0] | |
| 7/7: $0\o_ctrl_jump[0:0] | |
| Creating decoders for process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| 1/40: $0\o_rd_alu_en[0:0] | |
| 2/40: $0\o_rd_csr_en[0:0] | |
| 3/40: $0\o_op_b_source[0:0] | |
| 4/40: $0\o_immdec_en[3:0] | |
| 5/40: $0\o_immdec_ctrl[3:0] | |
| 6/40: $0\o_csr_imm_en[0:0] | |
| 7/40: $0\o_csr_d_sel[0:0] | |
| 8/40: $0\o_csr_source[1:0] | |
| 9/40: $0\o_csr_mcause_en[0:0] | |
| 10/40: $0\o_csr_mie_en[0:0] | |
| 11/40: $0\o_csr_mstatus_en[0:0] | |
| 12/40: $0\o_csr_addr[1:0] | |
| 13/40: $0\o_csr_en[0:0] | |
| 14/40: $0\o_mem_cmd[0:0] | |
| 15/40: $0\o_mem_half[0:0] | |
| 16/40: $0\o_mem_word[0:0] | |
| 17/40: $0\o_mem_signed[0:0] | |
| 18/40: $0\o_alu_rd_sel[2:0] | |
| 19/40: $0\o_alu_cmp_sig[0:0] | |
| 20/40: $0\o_alu_cmp_eq[0:0] | |
| 21/40: $0\o_alu_bool_op[1:0] | |
| 22/40: $0\o_alu_sub[0:0] | |
| 23/40: $0\o_ctrl_mret[0:0] | |
| 24/40: $0\o_ctrl_pc_rel[0:0] | |
| 25/40: $0\o_ctrl_utype[0:0] | |
| 26/40: $0\o_ctrl_jal_or_jalr[0:0] | |
| 27/40: $0\o_bufreg_sh_signed[0:0] | |
| 28/40: $0\o_bufreg_clr_lsb[0:0] | |
| 29/40: $0\o_bufreg_imm_en[0:0] | |
| 30/40: $0\o_bufreg_rs1_en[0:0] | |
| 31/40: $0\o_rd_op[0:0] | |
| 32/40: $0\o_slt_op[0:0] | |
| 33/40: $0\o_shift_op[0:0] | |
| 34/40: $0\o_mem_op[0:0] | |
| 35/40: $0\o_branch_op[0:0] | |
| 36/40: $0\o_ebreak[0:0] | |
| 37/40: $0\o_e_op[0:0] | |
| 38/40: $0\o_cond_branch[0:0] | |
| 39/40: $0\o_bne_or_bge[0:0] | |
| 40/40: $0\o_sh_right[0:0] | |
| Creating decoders for process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| 1/7: $0\op22[0:0] | |
| 2/7: $0\op20[0:0] | |
| 3/7: $0\funct3[2:0] | |
| 4/7: $0\imm30[0:0] | |
| 5/7: $0\op26[0:0] | |
| 6/7: $0\op21[0:0] | |
| 7/7: $0\opcode[4:0] | |
| Creating decoders for process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| 1/6: $0\imm30_25[5:0] | |
| 2/6: $0\imm7[0:0] | |
| 3/6: $0\imm19_12_20[8:0] | |
| 4/6: $0\imm11_7[4:0] | |
| 5/6: $0\imm24_20[4:0] | |
| 6/6: $0\signbit[0:0] | |
| Creating decoders for process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| 1/3: $0\c_r[0:0] | |
| 2/3: $0\data[29:0] | |
| 3/3: $0\o_lsb[1:0] | |
| Creating decoders for process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| 1/3: $0\pc_plus_offset_cy_r[0:0] | |
| 2/3: $0\pc_plus_4_cy_r[0:0] | |
| 3/3: $0\o_ibus_adr[31:0] | |
| Creating decoders for process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| 1/2: $0\add_cy_r[0:0] | |
| 2/2: $0\cmp_r[0:0] | |
| Creating decoders for process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| 1/2: $0\signbit[0:0] | |
| 2/2: $0\dat[31:0] | |
| Creating decoders for process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| 1/10: $0\mcause3_0[3:0] [1] | |
| 2/10: $0\mcause3_0[3:0] [0] | |
| 3/10: $0\mcause3_0[3:0] [2] | |
| 4/10: $0\mcause3_0[3:0] [3] | |
| 5/10: $0\mie_mtie[0:0] | |
| 6/10: $0\mcause31[0:0] | |
| 7/10: $0\mstatus_mpie[0:0] | |
| 8/10: $0\mstatus_mie[0:0] | |
| 9/10: $0\timer_irq_r[0:0] | |
| 10/10: $0\o_new_irq[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| 1/1: $0\rdata1[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| 1/1: $0\wdata0_r[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| 1/5: $0\rdata0[1:0] | |
| 2/5: $0\rgnt[0:0] | |
| 3/5: $0\rreq_r[0:0] | |
| 4/5: $0\rcnt[4:0] | |
| 5/5: $0\rtrig1[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| 1/3: $0\wdata1_r[1:0] | |
| 2/3: $0\wen1_r[0:0] | |
| 3/3: $0\wen0_r[0:0] | |
| Creating decoders for process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| 1/4: $0\o_rdata[1:0] | |
| 2/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 | |
| 3/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_DATA[1:0]$62 | |
| 4/4: $0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_ADDR[9:0]$63 | |
| Creating decoders for process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| 1/1: $0\o_wb_cpu_ack[0:0] | |
| Creating decoders for process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| 1/13: $0\o_wb_rdt[31:0] | |
| 2/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 | |
| 3/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA[31:0]$24 | |
| 4/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_ADDR[6:0]$27 | |
| 5/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 | |
| 6/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA[31:0]$25 | |
| 7/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_ADDR[6:0]$23 | |
| 8/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 | |
| 9/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA[31:0]$29 | |
| 10/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_ADDR[6:0]$28 | |
| 11/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 | |
| 12/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_DATA[31:0]$32 | |
| 13/13: $0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_ADDR[6:0]$31 | |
| Creating decoders for process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| 1/1: $0\o_wb_ack[0:0] | |
| Creating decoders for process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| 1/2: $0\o_wb_rdt[0:0] | |
| 2/2: $0\o_gpio[0:0] | |
| Creating decoders for process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| 1/3: $0\o_irq[0:0] | |
| 2/3: $0\mtime[31:0] | |
| 3/3: $0\mtimecmp[31:0] | |
| Creating decoders for process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| 1/1: $0\o_wb_dat[31:0] | |
| Creating decoders for process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| 1/1: $1\rst_reg[4:0] | |
| Creating decoders for process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| 1/1: $0\rst_reg[4:0] | |
| 24.4.6. Executing PROC_DLATCH pass (convert process syncs to latches). | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bne_or_bge' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_cond_branch' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_e_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ebreak' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_branch_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_shift_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_slt_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_sh_right' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_rs1_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_imm_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_clr_lsb' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_bufreg_sh_signed' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_jal_or_jalr' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_utype' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_pc_rel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_ctrl_mret' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_op_b_source' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_sub' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_bool_op' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_cmp_eq' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_cmp_sig' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_alu_rd_sel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_cmd' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_signed' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_word' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_mem_half' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_addr' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mstatus_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mie_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_mcause_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_source' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_d_sel' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_csr_imm_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_immdec_ctrl' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_immdec_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_csr_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\serv_decode\PRE_REGISTER=1.\o_rd_alu_en' from process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| No latch inferred for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\o_wb_dat' from process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| 24.4.7. Executing PROC_DFF pass (convert process syncs to FFs). | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\misalign_trap_sync_r' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| created $dff cell `$procdff$660' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt_done' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$661' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_ctrl_jump' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$662' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\init_done' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$663' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$664' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\ibus_cyc' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$665' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\stage_two_req' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$666' with positive edge clock. | |
| Creating register for signal `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.\o_cnt_r' using process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| created $dff cell `$procdff$667' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\opcode' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$668' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op21' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$669' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op26' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$670' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\imm30' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$671' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\funct3' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$672' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op20' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$673' with positive edge clock. | |
| Creating register for signal `$paramod\serv_decode\PRE_REGISTER=1.\op22' using process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| created $dff cell `$procdff$674' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\signbit' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$675' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm24_20' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$676' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm11_7' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$677' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm19_12_20' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$678' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm7' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$679' with positive edge clock. | |
| Creating register for signal `\serv_immdec.\imm30_25' using process `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| created $dff cell `$procdff$680' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\o_lsb' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$681' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\c_r' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$682' with positive edge clock. | |
| Creating register for signal `\serv_bufreg.\data' using process `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| created $dff cell `$procdff$683' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\o_ibus_adr' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$684' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\pc_plus_4_cy_r' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$685' with positive edge clock. | |
| Creating register for signal `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.\pc_plus_offset_cy_r' using process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| created $dff cell `$procdff$686' with positive edge clock. | |
| Creating register for signal `\serv_alu.\cmp_r' using process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| created $dff cell `$procdff$687' with positive edge clock. | |
| Creating register for signal `\serv_alu.\add_cy_r' using process `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| created $dff cell `$procdff$688' with positive edge clock. | |
| Creating register for signal `$paramod\serv_mem_if\WITH_CSR=1.\dat' using process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| created $dff cell `$procdff$689' with positive edge clock. | |
| Creating register for signal `$paramod\serv_mem_if\WITH_CSR=1.\signbit' using process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| created $dff cell `$procdff$690' with positive edge clock. | |
| Creating register for signal `\serv_csr.\o_new_irq' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$691' with positive edge clock. | |
| Creating register for signal `\serv_csr.\timer_irq_r' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$692' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mstatus_mie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$693' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mstatus_mpie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$694' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mcause3_0' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$695' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mie_mtie' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$696' with positive edge clock. | |
| Creating register for signal `\serv_csr.\mcause31' using process `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| created $dff cell `$procdff$697' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rdata1' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| created $dff cell `$procdff$698' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wdata0_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| created $dff cell `$procdff$699' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rdata0' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$700' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rcnt' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$701' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rgnt' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$702' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rtrig1' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$703' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\rreq_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| created $dff cell `$procdff$704' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wen1_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$705' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wen0_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$706' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.\wdata1_r' using process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| created $dff cell `$procdff$707' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.\o_rdata' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$708' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_DATA' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$709' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_ADDR' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$710' with positive edge clock. | |
| Creating register for signal `$paramod\serv_rf_ram\width=2\csr_regs=4.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN' using process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| created $dff cell `$procdff$711' with positive edge clock. | |
| Creating register for signal `$paramod\servant_mux\sim=0.\o_wb_cpu_ack' using process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| created $dff cell `$procdff$712' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.\o_wb_rdt' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$713' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$714' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$715' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$716' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$717' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$718' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$719' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$720' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$721' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$722' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_ADDR' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$723' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_DATA' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$724' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| created $dff cell `$procdff$725' with positive edge clock. | |
| Creating register for signal `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.\o_wb_ack' using process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| created $dff cell `$procdff$726' with positive edge clock. | |
| Creating register for signal `\servant_gpio.\o_wb_rdt' using process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| created $dff cell `$procdff$727' with positive edge clock. | |
| Creating register for signal `\servant_gpio.\o_gpio' using process `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| created $dff cell `$procdff$728' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\o_irq' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$729' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\mtimecmp' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$730' with positive edge clock. | |
| Creating register for signal `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.\mtime' using process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| created $dff cell `$procdff$731' with positive edge clock. | |
| Creating register for signal `$paramod\servant_clock_gen\PLL=1313820229.\rst_reg' using process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| created $dff cell `$procdff$732' with positive edge clock. | |
| 24.4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). | |
| Found and cleaned up 2 empty switches in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Removing empty process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:179$523'. | |
| Found and cleaned up 3 empty switches in `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Removing empty process `$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_state.v:112$500'. | |
| Removing empty process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:240$440'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| Removing empty process `$paramod\serv_decode\PRE_REGISTER=1.$proc$../src/serv_1.0.2/rtl/serv_decode.v:228$439'. | |
| Found and cleaned up 6 empty switches in `\serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| Removing empty process `serv_immdec.$proc$../src/serv_1.0.2/rtl/serv_immdec.v:40$305'. | |
| Found and cleaned up 2 empty switches in `\serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| Removing empty process `serv_bufreg.$proc$../src/serv_1.0.2/rtl/serv_bufreg.v:30$295'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Removing empty process `$paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_ctrl.v:67$278'. | |
| Found and cleaned up 1 empty switch in `\serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| Removing empty process `serv_alu.$proc$../src/serv_1.0.2/rtl/serv_alu.v:61$264'. | |
| Found and cleaned up 2 empty switches in `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| Removing empty process `$paramod\serv_mem_if\WITH_CSR=1.$proc$../src/serv_1.0.2/rtl/serv_mem_if.v:91$204'. | |
| Found and cleaned up 6 empty switches in `\serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| Removing empty process `serv_csr.$proc$../src/serv_1.0.2/rtl/serv_csr.v:74$105'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:122$82'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:77$81'. | |
| Found and cleaned up 4 empty switches in `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:125$78'. | |
| Removing empty process `$paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:82$74'. | |
| Found and cleaned up 1 empty switch in `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| Removing empty process `$paramod\serv_rf_ram\width=2\csr_regs=4.$proc$../src/serv_1.0.2/rtl/serv_rf_ram.v:14$61'. | |
| Found and cleaned up 2 empty switches in `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| Removing empty process `$paramod\servant_mux\sim=0.$proc$../src/servant_1.0.2/servant/servant_mux.v:42$43'. | |
| Found and cleaned up 4 empty switches in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:30$21'. | |
| Found and cleaned up 1 empty switch in `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| Removing empty process `$paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram.$proc$../src/servant_1.0.2/servant/servant_ram.v:24$17'. | |
| Found and cleaned up 1 empty switch in `\servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| Removing empty process `servant_gpio.$proc$../src/servant_1.0.2/servant/servant_gpio.v:9$9'. | |
| Found and cleaned up 3 empty switches in `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| Removing empty process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:26$5'. | |
| Removing empty process `$paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801.$proc$../src/servant_1.0.2/servant/servant_timer.v:21$4'. | |
| Removing empty process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:19$3'. | |
| Removing empty process `$paramod\servant_clock_gen\PLL=1313820229.$proc$../src/servant_1.0.2/servant/servant_clock_gen.v:21$2'. | |
| Cleaned up 41 empty switches. | |
| 24.5. Executing FLATTEN pass (flatten design). | |
| Using template $paramod\servant_clock_gen\PLL=1313820229 for cells of type $paramod\servant_clock_gen\PLL=1313820229. | |
| Using template $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant for cells of type $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant. | |
| Using template servant_gpio for cells of type servant_gpio. | |
| Using template $paramod\servant_mux\sim=0 for cells of type $paramod\servant_mux\sim=0. | |
| Using template $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801 for cells of type $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Using template $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1 for cells of type $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Using template $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram for cells of type $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Using template servant_arbiter for cells of type servant_arbiter. | |
| Using template $paramod\serv_rf_ram\width=2\csr_regs=4 for cells of type $paramod\serv_rf_ram\width=2\csr_regs=4. | |
| Using template $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4 for cells of type $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4. | |
| Using template $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top for cells of type $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top. | |
| Using template $paramod\serv_decode\PRE_REGISTER=1 for cells of type $paramod\serv_decode\PRE_REGISTER=1. | |
| Using template serv_alu for cells of type serv_alu. | |
| Using template $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1 for cells of type $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Using template serv_immdec for cells of type serv_immdec. | |
| Using template serv_bufreg for cells of type serv_bufreg. | |
| Using template $paramod\serv_mem_if\WITH_CSR=1 for cells of type $paramod\serv_mem_if\WITH_CSR=1. | |
| Using template $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1 for cells of type $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1. | |
| Using template $paramod\serv_rf_if\WITH_CSR=1 for cells of type $paramod\serv_rf_if\WITH_CSR=1. | |
| Using template serv_csr for cells of type serv_csr. | |
| <suppressed ~20 debug messages> | |
| No more expansions possible. | |
| Deleting now unused module $paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Deleting now unused module $paramod\serv_decode\PRE_REGISTER=1. | |
| Deleting now unused module serv_immdec. | |
| Deleting now unused module serv_bufreg. | |
| Deleting now unused module $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1. | |
| Deleting now unused module serv_alu. | |
| Deleting now unused module $paramod\serv_rf_if\WITH_CSR=1. | |
| Deleting now unused module $paramod\serv_mem_if\WITH_CSR=1. | |
| Deleting now unused module serv_csr. | |
| Deleting now unused module $paramod\serv_rf_ram_if\width=2\reset_strategy=1296649801\csr_regs=4. | |
| Deleting now unused module $paramod\serv_rf_ram\width=2\csr_regs=4. | |
| Deleting now unused module $paramod$40566e6b020df438830ca73fa1cd78590600825c\serv_top. | |
| Deleting now unused module servant_arbiter. | |
| Deleting now unused module $paramod\servant_mux\sim=0. | |
| Deleting now unused module $paramod$fcfd487e800d6ca56b84e3b449f8bc0485108529\servant_ram. | |
| Deleting now unused module servant_gpio. | |
| Deleting now unused module $paramod\serv_rf_top\RESET_PC=0\RESET_STRATEGY=1296649801\WITH_CSR=1. | |
| Deleting now unused module $paramod\servant_timer\WIDTH=32\RESET_STRATEGY=1296649801. | |
| Deleting now unused module $paramod\servant_clock_gen\PLL=1313820229. | |
| Deleting now unused module $paramod$a443c9a07f88a40859f2d557eefca06903d747d4\servant. | |
| 24.6. Executing TRIBUF pass. | |
| 24.7. Executing DEMINOUT pass (demote inout ports to input or output). | |
| 24.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~24 debug messages> | |
| 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 3 unused cells and 319 unused wires. | |
| <suppressed ~6 debug messages> | |
| 24.10. Executing CHECK pass (checking for obvious problems). | |
| checking module service.. | |
| found and reported 0 problems. | |
| 24.11. Executing OPT pass (performing simple optimizations). | |
| 24.11.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~201 debug messages> | |
| Removed a total of 67 cells. | |
| 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~77 debug messages> | |
| 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.state.$reduce_or$../src/serv_1.0.2/rtl/serv_state.v:57$443: { \servant.cpu.cpu.state.o_cnt_r [0] \servant.cpu.cpu.state.o_cnt_r [1] \servant.cpu.cpu.state.o_cnt_r [2] \servant.cpu.cpu.state.o_cnt_r [3] } | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.rf_if.$reduce_or$../src/serv_1.0.2/rtl/serv_rf_if.v:52$212: { \servant.cpu.cpu.immdec.imm11_7 [0] \servant.cpu.cpu.immdec.imm11_7 [1] \servant.cpu.cpu.immdec.imm11_7 [2] \servant.cpu.cpu.immdec.imm11_7 [3] \servant.cpu.cpu.immdec.imm11_7 [4] } | |
| New input vector for $reduce_or cell $techmap\servant.cpu.cpu.decode.$reduce_or$../src/serv_1.0.2/rtl/serv_decode.v:120$370: { \servant.cpu.cpu.decode.funct3 [0] \servant.cpu.cpu.decode.funct3 [1] \servant.cpu.cpu.decode.funct3 [2] } | |
| Consolidated identical input bits for $mux cell $techmap\servant.cpu.rf_ram.$procmux$613: | |
| Old ports: A=2'00, B=2'11, Y=$techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [0] | |
| New connections: $techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [1] = $techmap\servant.cpu.rf_ram.$0$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$60_EN[1:0]$64 [0] | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$623: | |
| Old ports: A=0, B=255, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] | |
| New connections: $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [31:1] = { 24'000000000000000000000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22 [0] } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$629: | |
| Old ports: A=0, B=65280, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [31:9] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [7:0] } = { 16'0000000000000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26 [8] 8'00000000 } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$635: | |
| Old ports: A=0, B=16711680, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [31:17] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [15:0] } = { 8'00000000 $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30 [16] 16'0000000000000000 } | |
| Consolidated identical input bits for $mux cell $techmap\servant.ram.$procmux$641: | |
| Old ports: A=0, B=32'11111111000000000000000000000000, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 | |
| New ports: A=1'0, B=1'1, Y=$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] | |
| New connections: { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [31:25] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [23:0] } = { $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] $techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$14_EN[31:0]$33 [24] 24'000000000000000000000000 } | |
| Optimizing cells in module \service. | |
| Performed a total of 8 changes. | |
| 24.11.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.11.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 71 unused wires. | |
| <suppressed ~5 debug messages> | |
| 24.11.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~77 debug messages> | |
| 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.11.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.11.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.11.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.11.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.12. Executing WREDUCE pass (reducing word size of cells). | |
| Removed top 25 address bits (of 32) from memory init port service.$techmap\servant.ram.$meminit$\mem$../src/servant_1.0.2/servant/servant_ram.v:43$35 (servant.ram.mem). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.servant_mux.$eq$../src/servant_1.0.2/servant/servant_mux.v:58$48 ($eq). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7 ($add). | |
| Removed top 8 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$722 ($dff). | |
| Removed top 7 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$725 ($dff). | |
| Removed top 16 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$718 ($dff). | |
| Removed top 24 bits (of 32) from FF cell service.$techmap\servant.ram.$procdff$714 ($dff). | |
| Removed cell service.$techmap\servant.ram.$procmux$645 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$643 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$639 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$637 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$633 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$631 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$627 ($mux). | |
| Removed cell service.$techmap\servant.ram.$procmux$625 ($mux). | |
| Removed top 23 bits (of 32) from mux cell service.$techmap\servant.arbiter.$ternary$../src/servant_1.0.2/servant/servant_arbiter.v:33$54 ($mux). | |
| Removed top 1 bits (of 2) from FF cell service.$techmap\servant.cpu.rf_ram.$procdff$711 ($dff). | |
| Removed cell service.$techmap\servant.cpu.rf_ram.$procmux$617 ($mux). | |
| Removed cell service.$techmap\servant.cpu.rf_ram.$procmux$615 ($mux). | |
| Removed top 4 bits (of 5) from port B of cell service.$techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79 ($add). | |
| Removed top 30 bits (of 32) from port B of cell service.$techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| Removed top 27 bits (of 32) from port Y of cell service.$techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.decode.$eq$../src/serv_1.0.2/rtl/serv_decode.v:211$428 ($eq). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.decode.$eq$../src/serv_1.0.2/rtl/serv_decode.v:117$367 ($eq). | |
| Removed top 2 bits (of 3) from port B of cell service.$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510 ($add). | |
| Removed top 2 bits (of 3) from port B of cell service.$techmap\servant.cpu.cpu.state.$eq$../src/serv_1.0.2/rtl/serv_state.v:67$455 ($eq). | |
| Removed top 1 bits (of 2) from port A of cell service.$techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| Removed top 31 bits (of 32) from port A of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$211 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port A of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$210 ($or). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$209 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208 ($and). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208 ($and). | |
| Removed top 31 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$207 ($or). | |
| Removed top 26 bits (of 32) from mux cell service.$techmap\servant.cpu.cpu.mem_if.$ternary$../src/serv_1.0.2/rtl/serv_mem_if.v:86$203 ($mux). | |
| Removed top 31 bits (of 32) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| Removed top 26 bits (of 32) from port Y of cell service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.mem_if.$eq$../src/serv_1.0.2/rtl/serv_mem_if.v:53$171 ($eq). | |
| Removed top 1 bits (of 2) from port A of cell service.$techmap\servant.cpu.cpu.rf_if.$or$../src/serv_1.0.2/rtl/serv_rf_if.v:114$231 ($or). | |
| Removed top 4 bits (of 6) from mux cell service.$techmap\servant.cpu.cpu.rf_if.$ternary$../src/serv_1.0.2/rtl/serv_rf_if.v:78$223 ($mux). | |
| Removed cell service.$techmap\servant.cpu.cpu.csr.$ternary$../src/serv_1.0.2/rtl/serv_csr.v:58$91 ($mux). | |
| Removed top 1 bits (of 2) from port B of cell service.$techmap\servant.cpu.cpu.csr.$eq$../src/serv_1.0.2/rtl/serv_csr.v:54$84 ($eq). | |
| Removed top 7 bits (of 24) from FF cell service.$techmap\servant.ram.$procdff$722 ($dff). | |
| Removed top 7 bits (of 16) from FF cell service.$techmap\servant.ram.$procdff$718 ($dff). | |
| Removed top 7 bits (of 8) from FF cell service.$techmap\servant.ram.$procdff$714 ($dff). | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$208_Y. | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$and$../src/serv_1.0.2/rtl/serv_mem_if.v:104$209_Y. | |
| Removed top 31 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$or$../src/serv_1.0.2/rtl/serv_mem_if.v:104$207_Y. | |
| Removed top 26 bits (of 32) from wire service.$techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199_Y. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_DATA[31:0]$24. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN[31:0]$22. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_DATA[31:0]$25. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN[31:0]$26. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_DATA[31:0]$29. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$0$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN[31:0]$30. | |
| Removed top 24 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$11_EN. | |
| Removed top 16 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$12_EN. | |
| Removed top 8 bits (of 32) from wire service.$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$13_EN. | |
| Removed top 23 bits (of 32) from wire service.servant.arbiter.o_wb_cpu_adr. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.cpu.o_wreg1. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.cpu.rf_if.o_wreg1. | |
| Removed top 4 bits (of 6) from wire service.servant.cpu.rf_ram_if.i_wreg1. | |
| 24.13. Executing PEEPOPT pass (run peephole optimizers). | |
| 24.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 1 unused cells and 32 unused wires. | |
| <suppressed ~2 debug messages> | |
| 24.15. Executing SHARE pass (SAT-based resource sharing). | |
| 24.16. Executing TECHMAP pass (map to technology primitives). | |
| 24.16.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_lut_cmp_'. | |
| Successfully finished Verilog frontend. | |
| 24.16.2. Continuing TECHMAP pass. | |
| Using template $paramod$6816abac91a51b405c3de5bceb2855c03dd44485\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$df71d3c5c306636e78c1ede81ccfd95a4d222f85\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$0760830c1e6c196382cd2cb153e9fff2d84c061d\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$77ad031fce233083715243f95e3cd2547d931e42\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$d87a48a4cd82717ae6bd57e6fe5ce90d87c44016\_90_lut_cmp_ for cells of type $eq. | |
| Using template $paramod$99e5b0ecd4c7f9fb6cd3a733593eba894c42613f\_90_lut_cmp_ for cells of type $eq. | |
| No more expansions possible. | |
| <suppressed ~148 debug messages> | |
| 24.17. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~1 debug messages> | |
| 24.18. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 43 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.19. Executing ALUMACC pass (create $alu and $macc cells). | |
| Extracting $alu and $macc cells in module service: | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$242 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$245 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$266 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$274 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275 ($add). | |
| creating $macc model for $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199 ($sub). | |
| creating $macc model for $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510 ($add). | |
| creating $macc model for $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79 ($add). | |
| creating $macc model for $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73 ($sub). | |
| creating $macc model for $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7 ($add). | |
| merging $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$274 into $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275. | |
| merging $macc model for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$266 into $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267. | |
| merging $macc model for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$293 into $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294. | |
| merging $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$245 into $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246. | |
| merging $macc model for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$242 into $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294. | |
| creating $alu model for $macc $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246. | |
| creating $alu model for $macc $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73. | |
| creating $alu model for $macc $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243. | |
| creating $alu model for $macc $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7. | |
| creating $alu model for $techmap\servant.timer.$ge$../src/servant_1.0.2/servant/servant_timer.v:30$8 ($ge): new $alu | |
| creating $alu cell for $techmap\servant.timer.$ge$../src/servant_1.0.2/servant/servant_timer.v:30$8: $auto$alumacc.cc:474:replace_alu$771 | |
| creating $alu cell for $techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7: $auto$alumacc.cc:474:replace_alu$780 | |
| creating $alu cell for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:34$243: $auto$alumacc.cc:474:replace_alu$783 | |
| creating $alu cell for $techmap\servant.cpu.rf_ram_if.$sub$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:80$73: $auto$alumacc.cc:474:replace_alu$786 | |
| creating $alu cell for $techmap\servant.cpu.cpu.alu.$add$../src/serv_1.0.2/rtl/serv_alu.v:36$246: $auto$alumacc.cc:474:replace_alu$789 | |
| creating $alu cell for $techmap\servant.cpu.rf_ram_if.$add$../src/serv_1.0.2/rtl/serv_rf_ram_if.v:127$79: $auto$alumacc.cc:474:replace_alu$792 | |
| creating $alu cell for $techmap\servant.cpu.cpu.bufreg.$add$../src/serv_1.0.2/rtl/serv_bufreg.v:28$294: $auto$alumacc.cc:474:replace_alu$795 | |
| creating $alu cell for $techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510: $auto$alumacc.cc:474:replace_alu$798 | |
| creating $alu cell for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:49$267: $auto$alumacc.cc:474:replace_alu$801 | |
| creating $alu cell for $techmap\servant.cpu.cpu.mem_if.$sub$../src/serv_1.0.2/rtl/serv_mem_if.v:84$199: $auto$alumacc.cc:474:replace_alu$804 | |
| creating $alu cell for $techmap\servant.cpu.cpu.ctrl.$add$../src/serv_1.0.2/rtl/serv_ctrl.v:61$275: $auto$alumacc.cc:474:replace_alu$807 | |
| created 11 $alu and 0 $macc cells. | |
| 24.20. Executing OPT pass (performing simple optimizations). | |
| 24.20.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~12 debug messages> | |
| Removed a total of 4 cells. | |
| 24.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~69 debug messages> | |
| 24.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$778: { $auto$rtlil.cc:1832:Not$775 $auto$rtlil.cc:1835:ReduceAnd$777 } | |
| New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$776: { $auto$alumacc.cc:490:replace_alu$772 [0] $auto$alumacc.cc:490:replace_alu$772 [1] $auto$alumacc.cc:490:replace_alu$772 [2] $auto$alumacc.cc:490:replace_alu$772 [3] $auto$alumacc.cc:490:replace_alu$772 [4] $auto$alumacc.cc:490:replace_alu$772 [5] $auto$alumacc.cc:490:replace_alu$772 [6] $auto$alumacc.cc:490:replace_alu$772 [7] $auto$alumacc.cc:490:replace_alu$772 [8] $auto$alumacc.cc:490:replace_alu$772 [9] $auto$alumacc.cc:490:replace_alu$772 [10] $auto$alumacc.cc:490:replace_alu$772 [11] $auto$alumacc.cc:490:replace_alu$772 [12] $auto$alumacc.cc:490:replace_alu$772 [13] $auto$alumacc.cc:490:replace_alu$772 [14] $auto$alumacc.cc:490:replace_alu$772 [15] $auto$alumacc.cc:490:replace_alu$772 [16] $auto$alumacc.cc:490:replace_alu$772 [17] $auto$alumacc.cc:490:replace_alu$772 [18] $auto$alumacc.cc:490:replace_alu$772 [19] $auto$alumacc.cc:490:replace_alu$772 [20] $auto$alumacc.cc:490:replace_alu$772 [21] $auto$alumacc.cc:490:replace_alu$772 [22] $auto$alumacc.cc:490:replace_alu$772 [23] $auto$alumacc.cc:490:replace_alu$772 [24] $auto$alumacc.cc:490:replace_alu$772 [25] $auto$alumacc.cc:490:replace_alu$772 [26] $auto$alumacc.cc:490:replace_alu$772 [27] $auto$alumacc.cc:490:replace_alu$772 [28] $auto$alumacc.cc:490:replace_alu$772 [29] $auto$alumacc.cc:490:replace_alu$772 [30] $auto$alumacc.cc:490:replace_alu$772 [31] } | |
| Optimizing cells in module \service. | |
| Performed a total of 2 changes. | |
| 24.20.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.20.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.20.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 5 unused cells and 10 unused wires. | |
| <suppressed ~6 debug messages> | |
| 24.20.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.20.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~69 debug messages> | |
| 24.20.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.20.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.20.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.20.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.20.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.20.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.21. Executing FSM pass (extract and optimize FSM). | |
| 24.21.1. Executing FSM_DETECT pass (finding FSMs in design). | |
| 24.21.2. Executing FSM_EXTRACT pass (extracting FSM from design). | |
| 24.21.3. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 24.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.21.5. Executing FSM_OPT pass (simple optimizations of FSMs). | |
| 24.21.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). | |
| 24.21.7. Executing FSM_INFO pass (dumping all available information on FSM cells). | |
| 24.21.8. Executing FSM_MAP pass (mapping FSMs to basic logic). | |
| 24.22. Executing OPT pass (performing simple optimizations). | |
| 24.22.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.22.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.22.3. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.22.5. Finished fast OPT passes. | |
| 24.23. Executing MEMORY pass. | |
| 24.23.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). | |
| Checking cell `$techmap\servant.cpu.rf_ram.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$66' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$36' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$37' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$38' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39' in module `\service': merged $dff to cell. | |
| Checking cell `$techmap\servant.cpu.rf_ram.$memrd$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:17$65' in module `\service': merged data $dff to cell. | |
| Checking cell `$techmap\servant.ram.$memrd$\mem$../src/servant_1.0.2/servant/servant_ram.v:35$34' in module `\service': merged data $dff to cell. | |
| 24.23.2. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 14 unused cells and 16 unused wires. | |
| <suppressed ~15 debug messages> | |
| 24.23.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). | |
| Consolidating write ports of memory service.servant.ram.mem by address: | |
| New clock domain: posedge \i_clk | |
| Port 0 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:31$36) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000000000000000000011111111 | |
| Port 1 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:32$37) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000000000001111111100000000 | |
| Merging port 0 into this one. | |
| Active bits: 00000000000000001111111111111111 | |
| Port 2 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:33$38) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 00000000111111110000000000000000 | |
| Merging port 1 into this one. | |
| Active bits: 00000000111111111111111111111111 | |
| Port 3 ($techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39) has addr \servant.arbiter.o_wb_cpu_adr [8:2]. | |
| Active bits: 11111111000000000000000000000000 | |
| Merging port 2 into this one. | |
| Active bits: 11111111111111111111111111111111 | |
| 24.23.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.23.5. Executing MEMORY_COLLECT pass (generating $mem cells). | |
| Collecting $memrd, $memwr and $meminit for memory `\servant.cpu.rf_ram.memory' in module `\service': | |
| $techmap\servant.cpu.rf_ram.$memwr$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:16$66 ($memwr) | |
| $techmap\servant.cpu.rf_ram.$memrd$\memory$../src/serv_1.0.2/rtl/serv_rf_ram.v:17$65 ($memrd) | |
| Collecting $memrd, $memwr and $meminit for memory `\servant.ram.mem' in module `\service': | |
| $techmap\servant.ram.$meminit$\mem$../src/servant_1.0.2/servant/servant_ram.v:43$35 ($meminit) | |
| $techmap\servant.ram.$memwr$\mem$../src/servant_1.0.2/servant/servant_ram.v:34$39 ($memwr) | |
| $techmap\servant.ram.$memrd$\mem$../src/servant_1.0.2/servant/servant_ram.v:35$34 ($memrd) | |
| 24.24. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). | |
| Processing service.servant.cpu.rf_ram.memory: | |
| Properties: ports=2 bits=1152 rports=1 wports=1 dbits=2 abits=10 words=576 | |
| Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Bram geometry: abits=8 dbits=16 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M0: awaste=192 dwaste=14 bwaste=3968 waste=3968 efficiency=9 | |
| Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3968 efficiency=9 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Bram geometry: abits=9 dbits=8 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=448 dwaste=6 bwaste=3968 waste=3968 efficiency=14 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3968 efficiency=14 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Bram geometry: abits=10 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=448 dwaste=2 bwaste=2944 waste=2944 efficiency=28 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2944 efficiency=28 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Bram geometry: abits=11 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=1472 dwaste=0 bwaste=2944 waste=2944 efficiency=28 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2944 efficiency=28 | |
| Storing for later selection. | |
| Selecting best of 4 rules: | |
| Efficiency for rule 2.3: efficiency=28, cells=1, acells=1 | |
| Efficiency for rule 2.2: efficiency=28, cells=1, acells=1 | |
| Efficiency for rule 2.1: efficiency=14, cells=2, acells=2 | |
| Efficiency for rule 1.1: efficiency=9, cells=3, acells=3 | |
| Selected rule 2.3 with efficiency 28. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: servant.cpu.rf_ram.memory.0.0.0 | |
| Processing service.servant.ram.mem: | |
| Properties: ports=2 bits=4096 rports=1 wports=1 dbits=32 abits=7 words=128 | |
| Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Bram geometry: abits=8 dbits=16 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M0: awaste=128 dwaste=0 bwaste=2048 waste=2048 efficiency=50 | |
| Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=2048 efficiency=50 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Bram geometry: abits=9 dbits=8 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=384 dwaste=0 bwaste=3072 waste=3072 efficiency=25 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3072 efficiency=25 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Bram geometry: abits=10 dbits=4 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=896 dwaste=0 bwaste=3584 waste=3584 efficiency=12 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3584 efficiency=12 | |
| Storing for later selection. | |
| Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Bram geometry: abits=11 dbits=2 wports=0 rports=0 | |
| Estimated number of duplicates for more read ports: dups=1 | |
| Metrics for $__ICE40_RAM4K_M123: awaste=1920 dwaste=0 bwaste=3840 waste=3840 efficiency=6 | |
| Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. | |
| Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Updated properties: dups=1 waste=3840 efficiency=6 | |
| Storing for later selection. | |
| Selecting best of 4 rules: | |
| Efficiency for rule 2.3: efficiency=6, cells=16, acells=1 | |
| Efficiency for rule 2.2: efficiency=12, cells=8, acells=1 | |
| Efficiency for rule 2.1: efficiency=25, cells=4, acells=1 | |
| Efficiency for rule 1.1: efficiency=50, cells=2, acells=1 | |
| Selected rule 1.1 with efficiency 50. | |
| Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): | |
| Write port #0 is in clock domain \i_clk. | |
| Mapped to bram port B1. | |
| Read port #0 is in clock domain \i_clk. | |
| Mapped to bram port A1.1. | |
| Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: servant.ram.mem.0.0.0 | |
| Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: servant.ram.mem.1.0.0 | |
| 24.26. Executing TECHMAP pass (map to technology primitives). | |
| 24.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K'. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. | |
| Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. | |
| Successfully finished Verilog frontend. | |
| 24.26.2. Continuing TECHMAP pass. | |
| Using template $paramod$1cf52d6bf97abd8ac242c98f430558b534970d65\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. | |
| Using template $paramod$f99e76b470b5c9ef85019a34bf48912c9da143c7\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. | |
| Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=11\CFG_DBITS=2\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. | |
| Using template $paramod$302e632eba0ef6d8cd68a4764c637a5431c6a98c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| Using template $paramod$e0a1b09a23541879bdb850ec7d5e406ac4498a7d\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| Using template $paramod$c580e88c60026da015257f05680f05599f0d3ee1\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. | |
| No more expansions possible. | |
| <suppressed ~130 debug messages> | |
| 24.27. Executing ICE40_BRAMINIT pass. | |
| 24.28. Executing OPT pass (performing simple optimizations). | |
| 24.28.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~17 debug messages> | |
| 24.28.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.28.3. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 76 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.28.5. Finished fast OPT passes. | |
| 24.29. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). | |
| 24.30. Executing OPT pass (performing simple optimizations). | |
| 24.30.1. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.2. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~64 debug messages> | |
| 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| New input vector for $reduce_or cell $techmap$techmap825\servant.ram.mem.0.0.0.$reduce_or$/usr/bin/../share/yosys/ice40/brams_map.v:222$824: { \servant.ram.we [0] \servant.ram.we [1] } | |
| New input vector for $reduce_or cell $techmap$techmap822\servant.ram.mem.1.0.0.$reduce_or$/usr/bin/../share/yosys/ice40/brams_map.v:222$821: { \servant.ram.we [2] \servant.ram.we [3] } | |
| Optimizing cells in module \service. | |
| Performed a total of 2 changes. | |
| 24.30.5. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.6. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.30.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) | |
| 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). | |
| Running muxtree optimizer on module \service.. | |
| Creating internal representation of mux trees. | |
| Evaluating internal representation of mux trees. | |
| Analyzing evaluation results. | |
| Removed 0 multiplexer ports. | |
| <suppressed ~64 debug messages> | |
| 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). | |
| Optimizing cells in module \service. | |
| Performed a total of 0 changes. | |
| 24.30.12. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.30.13. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.30.15. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.30.16. Finished OPT passes. (There is nothing left to do.) | |
| 24.31. Executing TECHMAP pass (map to technology primitives). | |
| 24.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. | |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. | |
| Generating RTLIL representation for module `\_90_simplemap_various'. | |
| Generating RTLIL representation for module `\_90_simplemap_registers'. | |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. | |
| Generating RTLIL representation for module `\_90_shift_shiftx'. | |
| Generating RTLIL representation for module `\_90_fa'. | |
| Generating RTLIL representation for module `\_90_lcu'. | |
| Generating RTLIL representation for module `\_90_alu'. | |
| Generating RTLIL representation for module `\_90_macc'. | |
| Generating RTLIL representation for module `\_90_alumacc'. | |
| Generating RTLIL representation for module `\$__div_mod_u'. | |
| Generating RTLIL representation for module `\$__div_mod'. | |
| Generating RTLIL representation for module `\_90_div'. | |
| Generating RTLIL representation for module `\_90_mod'. | |
| Generating RTLIL representation for module `\_90_pow'. | |
| Generating RTLIL representation for module `\_90_pmux'. | |
| Generating RTLIL representation for module `\_90_lut'. | |
| Successfully finished Verilog frontend. | |
| 24.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. | |
| Generating RTLIL representation for module `\_80_ice40_alu'. | |
| Successfully finished Verilog frontend. | |
| 24.31.3. Continuing TECHMAP pass. | |
| Using extmapper simplemap for cells of type $and. | |
| Using extmapper simplemap for cells of type $dff. | |
| Using extmapper simplemap for cells of type $mux. | |
| Using extmapper simplemap for cells of type $logic_not. | |
| Using extmapper simplemap for cells of type $lut. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $not. | |
| Using extmapper simplemap for cells of type $or. | |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $reduce_and. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=2\Y_WIDTH=5 for cells of type $alu. | |
| Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $reduce_or. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $xor. | |
| Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. | |
| Using extmapper simplemap for cells of type $pos. | |
| Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. | |
| Using template $paramod\_90_lcu\WIDTH=1 for cells of type $lcu. | |
| No more expansions possible. | |
| <suppressed ~900 debug messages> | |
| 24.32. Executing ICE40_OPT pass (performing simple optimizations). | |
| 24.32.1. Running ICE40 specific optimizations. | |
| 24.32.2. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~218 debug messages> | |
| 24.32.3. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~129 debug messages> | |
| Removed a total of 43 cells. | |
| 24.32.4. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.5. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 65 unused cells and 277 unused wires. | |
| <suppressed ~70 debug messages> | |
| 24.32.6. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.32.7. Running ICE40 specific optimizations. | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$780.slice[0].carry: CO=\servant.timer.mtime [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$786.slice[0].carry: CO=\servant.cpu.rf_ram_if.rcnt [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$792.slice[0].carry: CO=\servant.cpu.rf_ram_if.rcnt [0] | |
| Optimized away SB_CARRY cell service.$auto$alumacc.cc:474:replace_alu$804.slice[0].carry: CO=\servant.cpu.cpu.mem_if.dat [0] | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$780.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$786.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$792.slice[1].adder back to logic. | |
| Mapping SB_LUT4 cell service.$auto$alumacc.cc:474:replace_alu$804.slice[1].adder back to logic. | |
| 24.32.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~52 debug messages> | |
| 24.32.9. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~15 debug messages> | |
| Removed a total of 5 cells. | |
| 24.32.10. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.11. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 0 unused cells and 12 unused wires. | |
| <suppressed ~1 debug messages> | |
| 24.32.12. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.32.13. Running ICE40 specific optimizations. | |
| 24.32.14. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.32.15. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.32.16. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.32.17. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.32.18. Finished OPT passes. (There is nothing left to do.) | |
| 24.33. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). | |
| 24.34. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). | |
| Selected cell types for direct conversion: | |
| $_DFF_PP1_ -> $__DFFE_PP1 | |
| $_DFF_PP0_ -> $__DFFE_PP0 | |
| $_DFF_PN1_ -> $__DFFE_PN1 | |
| $_DFF_PN0_ -> $__DFFE_PN0 | |
| $_DFF_NP1_ -> $__DFFE_NP1 | |
| $_DFF_NP0_ -> $__DFFE_NP0 | |
| $_DFF_NN1_ -> $__DFFE_NN1 | |
| $_DFF_NN0_ -> $__DFFE_NN0 | |
| $_DFF_N_ -> $_DFFE_NP_ | |
| $_DFF_P_ -> $_DFFE_PP_ | |
| Transforming FF to FF+Enable cells in module service: | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1029 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [0] -> \servant.timer.mtimecmp [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1030 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [1] -> \servant.timer.mtimecmp [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1031 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [2] -> \servant.timer.mtimecmp [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1032 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [3] -> \servant.timer.mtimecmp [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1033 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [4] -> \servant.timer.mtimecmp [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1034 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [5] -> \servant.timer.mtimecmp [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1035 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [6] -> \servant.timer.mtimecmp [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1036 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [7] -> \servant.timer.mtimecmp [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1037 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [8] -> \servant.timer.mtimecmp [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1038 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [9] -> \servant.timer.mtimecmp [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1039 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [10] -> \servant.timer.mtimecmp [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1040 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [11] -> \servant.timer.mtimecmp [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1041 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [12] -> \servant.timer.mtimecmp [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1042 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [13] -> \servant.timer.mtimecmp [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1043 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [14] -> \servant.timer.mtimecmp [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1044 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [15] -> \servant.timer.mtimecmp [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1045 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [16] -> \servant.timer.mtimecmp [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1046 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [17] -> \servant.timer.mtimecmp [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1047 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [18] -> \servant.timer.mtimecmp [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1048 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [19] -> \servant.timer.mtimecmp [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1049 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [20] -> \servant.timer.mtimecmp [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1050 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [21] -> \servant.timer.mtimecmp [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1051 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [22] -> \servant.timer.mtimecmp [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1052 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [23] -> \servant.timer.mtimecmp [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1053 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [24] -> \servant.timer.mtimecmp [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1054 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [25] -> \servant.timer.mtimecmp [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1055 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [26] -> \servant.timer.mtimecmp [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1056 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [27] -> \servant.timer.mtimecmp [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1057 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [28] -> \servant.timer.mtimecmp [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1058 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [29] -> \servant.timer.mtimecmp [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1059 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [30] -> \servant.timer.mtimecmp [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1060 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtimecmp[31:0] [31] -> \servant.timer.mtimecmp [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1194 to $_DFFE_PP_ for $techmap\servant.cpu.rf_ram_if.$0\rdata1[0:0] -> \servant.cpu.rf_ram_if.rdata1. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1231 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [0] -> \servant.cpu.cpu.decode.funct3 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1232 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [1] -> \servant.cpu.cpu.decode.funct3 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1233 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\funct3[2:0] [2] -> \servant.cpu.cpu.decode.funct3 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1315 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op22[0:0] -> \servant.cpu.cpu.decode.op22. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1316 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op20[0:0] -> \servant.cpu.cpu.decode.op20. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1317 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\imm30[0:0] -> \servant.cpu.cpu.decode.imm30. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1318 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op26[0:0] -> \servant.cpu.cpu.decode.op26. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1319 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\op21[0:0] -> \servant.cpu.cpu.decode.op21. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1320 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [0] -> \servant.cpu.cpu.decode.opcode [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1321 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [1] -> \servant.cpu.cpu.decode.opcode [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1322 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [2] -> \servant.cpu.cpu.decode.opcode [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1323 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [3] -> \servant.cpu.cpu.decode.opcode [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1324 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.decode.$0\opcode[4:0] [4] -> \servant.cpu.cpu.decode.opcode [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1453 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.alu.$0\cmp_r[0:0] -> \servant.cpu.cpu.alu.cmp_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1476 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\init_done[0:0] -> \servant.cpu.cpu.state.init_done. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1477 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [0] -> \servant.cpu.cpu.immdec.imm19_12_20 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1478 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [1] -> \servant.cpu.cpu.immdec.imm19_12_20 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1479 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [2] -> \servant.cpu.cpu.immdec.imm19_12_20 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1480 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [3] -> \servant.cpu.cpu.immdec.imm19_12_20 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1481 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [4] -> \servant.cpu.cpu.immdec.imm19_12_20 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1482 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [5] -> \servant.cpu.cpu.immdec.imm19_12_20 [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1483 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [6] -> \servant.cpu.cpu.immdec.imm19_12_20 [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1484 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [7] -> \servant.cpu.cpu.immdec.imm19_12_20 [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1485 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm19_12_20[8:0] [8] -> \servant.cpu.cpu.immdec.imm19_12_20 [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1491 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\ibus_cyc[0:0] -> \servant.cpu.cpu.state.ibus_cyc. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1495 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\o_ctrl_jump[0:0] -> \servant.cpu.cpu.state.o_ctrl_jump. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1497 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.state.$0\misalign_trap_sync_r[0:0] -> \servant.cpu.cpu.state.misalign_trap_sync_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1591 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [0] -> \servant.cpu.cpu.immdec.imm30_25 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1592 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [1] -> \servant.cpu.cpu.immdec.imm30_25 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1593 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [2] -> \servant.cpu.cpu.immdec.imm30_25 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1594 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [3] -> \servant.cpu.cpu.immdec.imm30_25 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1595 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [4] -> \servant.cpu.cpu.immdec.imm30_25 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1596 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm30_25[5:0] [5] -> \servant.cpu.cpu.immdec.imm30_25 [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1597 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm7[0:0] -> \servant.cpu.cpu.immdec.imm7. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1598 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [0] -> \servant.cpu.cpu.immdec.imm11_7 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1599 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [1] -> \servant.cpu.cpu.immdec.imm11_7 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1600 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [2] -> \servant.cpu.cpu.immdec.imm11_7 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1601 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [3] -> \servant.cpu.cpu.immdec.imm11_7 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1602 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm11_7[4:0] [4] -> \servant.cpu.cpu.immdec.imm11_7 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1603 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [0] -> \servant.cpu.cpu.immdec.imm24_20 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1604 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [1] -> \servant.cpu.cpu.immdec.imm24_20 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1605 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [2] -> \servant.cpu.cpu.immdec.imm24_20 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1606 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [3] -> \servant.cpu.cpu.immdec.imm24_20 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1607 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\imm24_20[4:0] [4] -> \servant.cpu.cpu.immdec.imm24_20 [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1608 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.immdec.$0\signbit[0:0] -> \servant.cpu.cpu.immdec.signbit. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1750 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [0] -> \servant.cpu.cpu.bufreg.data [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1751 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [1] -> \servant.cpu.cpu.bufreg.data [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1752 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [2] -> \servant.cpu.cpu.bufreg.data [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1753 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [3] -> \servant.cpu.cpu.bufreg.data [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1754 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [4] -> \servant.cpu.cpu.bufreg.data [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1755 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [5] -> \servant.cpu.cpu.bufreg.data [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1756 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [6] -> \servant.cpu.cpu.bufreg.data [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1757 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [7] -> \servant.cpu.cpu.bufreg.data [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1758 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [8] -> \servant.cpu.cpu.bufreg.data [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1759 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [9] -> \servant.cpu.cpu.bufreg.data [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1760 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [10] -> \servant.cpu.cpu.bufreg.data [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1761 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [11] -> \servant.cpu.cpu.bufreg.data [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1762 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [12] -> \servant.cpu.cpu.bufreg.data [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1763 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [13] -> \servant.cpu.cpu.bufreg.data [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1764 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [14] -> \servant.cpu.cpu.bufreg.data [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1765 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [15] -> \servant.cpu.cpu.bufreg.data [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1766 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [16] -> \servant.cpu.cpu.bufreg.data [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1767 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [17] -> \servant.cpu.cpu.bufreg.data [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1768 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [18] -> \servant.cpu.cpu.bufreg.data [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1769 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [19] -> \servant.cpu.cpu.bufreg.data [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1770 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [20] -> \servant.cpu.cpu.bufreg.data [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1771 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [21] -> \servant.cpu.cpu.bufreg.data [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1772 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [22] -> \servant.cpu.cpu.bufreg.data [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1773 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [23] -> \servant.cpu.cpu.bufreg.data [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1774 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [24] -> \servant.cpu.cpu.bufreg.data [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1775 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [25] -> \servant.cpu.cpu.bufreg.data [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1776 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [26] -> \servant.cpu.cpu.bufreg.data [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1777 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [27] -> \servant.cpu.cpu.bufreg.data [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1778 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [28] -> \servant.cpu.cpu.bufreg.data [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1779 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\data[29:0] [29] -> \servant.cpu.cpu.bufreg.data [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1781 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\o_lsb[1:0] [0] -> \servant.cpu.cpu.bufreg.o_lsb [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1782 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.bufreg.$0\o_lsb[1:0] [1] -> \servant.cpu.cpu.bufreg.o_lsb [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1799 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [0] -> \servant.cpu.cpu.ctrl.o_ibus_adr [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1800 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [1] -> \servant.cpu.cpu.ctrl.o_ibus_adr [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1801 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [2] -> \servant.cpu.cpu.ctrl.o_ibus_adr [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1802 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [3] -> \servant.cpu.cpu.ctrl.o_ibus_adr [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1803 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [4] -> \servant.cpu.cpu.ctrl.o_ibus_adr [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1804 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [5] -> \servant.cpu.cpu.ctrl.o_ibus_adr [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1805 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [6] -> \servant.cpu.cpu.ctrl.o_ibus_adr [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1806 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [7] -> \servant.cpu.cpu.ctrl.o_ibus_adr [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1807 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [8] -> \servant.cpu.cpu.ctrl.o_ibus_adr [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1808 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [9] -> \servant.cpu.cpu.ctrl.o_ibus_adr [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1809 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [10] -> \servant.cpu.cpu.ctrl.o_ibus_adr [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1810 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [11] -> \servant.cpu.cpu.ctrl.o_ibus_adr [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1811 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [12] -> \servant.cpu.cpu.ctrl.o_ibus_adr [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1812 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [13] -> \servant.cpu.cpu.ctrl.o_ibus_adr [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1813 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [14] -> \servant.cpu.cpu.ctrl.o_ibus_adr [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1814 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [15] -> \servant.cpu.cpu.ctrl.o_ibus_adr [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1815 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [16] -> \servant.cpu.cpu.ctrl.o_ibus_adr [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1816 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [17] -> \servant.cpu.cpu.ctrl.o_ibus_adr [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1817 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [18] -> \servant.cpu.cpu.ctrl.o_ibus_adr [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1818 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [19] -> \servant.cpu.cpu.ctrl.o_ibus_adr [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1819 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [20] -> \servant.cpu.cpu.ctrl.o_ibus_adr [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1820 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [21] -> \servant.cpu.cpu.ctrl.o_ibus_adr [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1821 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [22] -> \servant.cpu.cpu.ctrl.o_ibus_adr [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1822 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [23] -> \servant.cpu.cpu.ctrl.o_ibus_adr [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1823 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [24] -> \servant.cpu.cpu.ctrl.o_ibus_adr [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1824 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [25] -> \servant.cpu.cpu.ctrl.o_ibus_adr [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1825 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [26] -> \servant.cpu.cpu.ctrl.o_ibus_adr [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1826 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [27] -> \servant.cpu.cpu.ctrl.o_ibus_adr [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1827 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [28] -> \servant.cpu.cpu.ctrl.o_ibus_adr [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1828 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [29] -> \servant.cpu.cpu.ctrl.o_ibus_adr [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1829 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [30] -> \servant.cpu.cpu.ctrl.o_ibus_adr [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1830 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.ctrl.$0\o_ibus_adr[31:0] [31] -> \servant.cpu.cpu.ctrl.o_ibus_adr [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1831 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\signbit[0:0] -> \servant.cpu.cpu.mem_if.signbit. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1832 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [0] -> \servant.cpu.cpu.mem_if.dat [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1833 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [1] -> \servant.cpu.cpu.mem_if.dat [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1834 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [2] -> \servant.cpu.cpu.mem_if.dat [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1835 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [3] -> \servant.cpu.cpu.mem_if.dat [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1836 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [4] -> \servant.cpu.cpu.mem_if.dat [4]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1837 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [5] -> \servant.cpu.cpu.mem_if.dat [5]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1838 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [6] -> \servant.cpu.cpu.mem_if.dat [6]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1839 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [7] -> \servant.cpu.cpu.mem_if.dat [7]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1840 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [8] -> \servant.cpu.cpu.mem_if.dat [8]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1841 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [9] -> \servant.cpu.cpu.mem_if.dat [9]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1842 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [10] -> \servant.cpu.cpu.mem_if.dat [10]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1843 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [11] -> \servant.cpu.cpu.mem_if.dat [11]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1844 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [12] -> \servant.cpu.cpu.mem_if.dat [12]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1845 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [13] -> \servant.cpu.cpu.mem_if.dat [13]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1846 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [14] -> \servant.cpu.cpu.mem_if.dat [14]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1847 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [15] -> \servant.cpu.cpu.mem_if.dat [15]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1848 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [16] -> \servant.cpu.cpu.mem_if.dat [16]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1849 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [17] -> \servant.cpu.cpu.mem_if.dat [17]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1850 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [18] -> \servant.cpu.cpu.mem_if.dat [18]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1851 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [19] -> \servant.cpu.cpu.mem_if.dat [19]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1852 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [20] -> \servant.cpu.cpu.mem_if.dat [20]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1853 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [21] -> \servant.cpu.cpu.mem_if.dat [21]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1854 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [22] -> \servant.cpu.cpu.mem_if.dat [22]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1855 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [23] -> \servant.cpu.cpu.mem_if.dat [23]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1856 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [24] -> \servant.cpu.cpu.mem_if.dat [24]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1857 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [25] -> \servant.cpu.cpu.mem_if.dat [25]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1858 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [26] -> \servant.cpu.cpu.mem_if.dat [26]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1859 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [27] -> \servant.cpu.cpu.mem_if.dat [27]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1860 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [28] -> \servant.cpu.cpu.mem_if.dat [28]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1861 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [29] -> \servant.cpu.cpu.mem_if.dat [29]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1862 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [30] -> \servant.cpu.cpu.mem_if.dat [30]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1863 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.mem_if.$0\dat[31:0] [31] -> \servant.cpu.cpu.mem_if.dat [31]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2044 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mstatus_mie[0:0] -> \servant.cpu.cpu.csr.mstatus_mie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2095 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause31[0:0] -> \servant.cpu.cpu.csr.mcause31. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2096 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mie_mtie[0:0] -> \servant.cpu.cpu.csr.mie_mtie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2097 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [0] -> \servant.cpu.cpu.csr.mcause3_0 [0]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2098 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [1] -> \servant.cpu.cpu.csr.mcause3_0 [1]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2099 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [2] -> \servant.cpu.cpu.csr.mcause3_0 [2]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2100 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mcause3_0[3:0] [3] -> \servant.cpu.cpu.csr.mcause3_0 [3]. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2101 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\mstatus_mpie[0:0] -> \servant.cpu.cpu.csr.mstatus_mpie. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2102 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\timer_irq_r[0:0] -> \servant.cpu.cpu.csr.timer_irq_r. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2103 to $_DFFE_PP_ for $techmap\servant.cpu.cpu.csr.$0\o_new_irq[0:0] -> \servant.cpu.cpu.csr.o_new_irq. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$888 to $_DFFE_PP_ for $techmap\servant.gpio.$0\o_gpio[0:0] -> \servant.gpio.o_gpio. | |
| converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$998 to $_DFFE_PP_ for $techmap\servant.timer.$0\mtime[31:0] [1] -> \servant.timer.mtime [1]. | |
| 24.35. Executing TECHMAP pass (map to technology primitives). | |
| 24.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DFF_N_'. | |
| Generating RTLIL representation for module `\$_DFF_P_'. | |
| Generating RTLIL representation for module `\$_DFFE_NN_'. | |
| Generating RTLIL representation for module `\$_DFFE_PN_'. | |
| Generating RTLIL representation for module `\$_DFFE_NP_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP_'. | |
| Generating RTLIL representation for module `\$_DFF_NN0_'. | |
| Generating RTLIL representation for module `\$_DFF_NN1_'. | |
| Generating RTLIL representation for module `\$_DFF_PN0_'. | |
| Generating RTLIL representation for module `\$_DFF_PN1_'. | |
| Generating RTLIL representation for module `\$_DFF_NP0_'. | |
| Generating RTLIL representation for module `\$_DFF_NP1_'. | |
| Generating RTLIL representation for module `\$_DFF_PP0_'. | |
| Generating RTLIL representation for module `\$_DFF_PP1_'. | |
| Generating RTLIL representation for module `\$__DFFE_NN0'. | |
| Generating RTLIL representation for module `\$__DFFE_NN1'. | |
| Generating RTLIL representation for module `\$__DFFE_PN0'. | |
| Generating RTLIL representation for module `\$__DFFE_PN1'. | |
| Generating RTLIL representation for module `\$__DFFE_NP0'. | |
| Generating RTLIL representation for module `\$__DFFE_NP1'. | |
| Generating RTLIL representation for module `\$__DFFE_PP0'. | |
| Generating RTLIL representation for module `\$__DFFE_PP1'. | |
| Successfully finished Verilog frontend. | |
| 24.35.2. Continuing TECHMAP pass. | |
| Using template \$_DFF_P_ for cells of type $_DFF_P_. | |
| Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. | |
| No more expansions possible. | |
| <suppressed ~255 debug messages> | |
| 24.36. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~412 debug messages> | |
| 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). | |
| 24.38. Executing ICE40_FFINIT pass (implement FF init values). | |
| Handling FF init values in service. | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$883 (SB_DFF): \clock_gen.rst_reg [0] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$884 (SB_DFF): \clock_gen.rst_reg [1] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$885 (SB_DFF): \clock_gen.rst_reg [2] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$886 (SB_DFF): \clock_gen.rst_reg [3] = 1 | |
| FF init value for cell $auto$simplemap.cc:420:simplemap_dff$887 (SB_DFF): \clock_gen.rst_reg [4] = 1 | |
| 24.39. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). | |
| Merging set/reset $_MUX_ cells into SB_FFs in service. | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1098 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1001 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1099 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1002 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2002 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1799 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1101 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1004 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1103 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1006 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1198 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [3], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1190 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1104 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1007 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1105 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1008 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1106 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1009 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1108 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1011 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1109 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1012 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1110 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1013 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1111 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1014 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1112 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1015 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1114 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1017 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1115 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1018 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1116 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1019 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1117 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1020 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1119 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1022 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1062 (A=\servant.cpu.cpu.mem_if.dat [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1029 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1120 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1023 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1121 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1024 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1122 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1025 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1123 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1026 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1124 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1027 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1505 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1494 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1118 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1021 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1063 (A=\servant.cpu.cpu.mem_if.dat [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1030 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1064 (A=\servant.cpu.cpu.mem_if.dat [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1031 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1065 (A=\servant.cpu.cpu.mem_if.dat [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1032 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1066 (A=\servant.cpu.cpu.mem_if.dat [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1033 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1067 (A=\servant.cpu.cpu.mem_if.dat [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1034 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1068 (A=\servant.cpu.cpu.mem_if.dat [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1035 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1069 (A=\servant.cpu.cpu.mem_if.dat [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1036 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1071 (A=\servant.cpu.cpu.mem_if.dat [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1038 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1102 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1005 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1072 (A=\servant.cpu.cpu.mem_if.dat [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1039 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1073 (A=\servant.cpu.cpu.mem_if.dat [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1040 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1074 (A=\servant.cpu.cpu.mem_if.dat [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1041 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1075 (A=\servant.cpu.cpu.mem_if.dat [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1042 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1076 (A=\servant.cpu.cpu.mem_if.dat [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1043 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1077 (A=\servant.cpu.cpu.mem_if.dat [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1044 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1078 (A=\servant.cpu.cpu.mem_if.dat [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1045 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1079 (A=\servant.cpu.cpu.mem_if.dat [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1046 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1080 (A=\servant.cpu.cpu.mem_if.dat [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1047 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1081 (A=\servant.cpu.cpu.mem_if.dat [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1048 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1082 (A=\servant.cpu.cpu.mem_if.dat [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1049 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1083 (A=\servant.cpu.cpu.mem_if.dat [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1050 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1084 (A=\servant.cpu.cpu.mem_if.dat [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1051 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1085 (A=\servant.cpu.cpu.mem_if.dat [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1052 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1086 (A=\servant.cpu.cpu.mem_if.dat [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1053 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1087 (A=\servant.cpu.cpu.mem_if.dat [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1054 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1088 (A=\servant.cpu.cpu.mem_if.dat [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1055 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1089 (A=\servant.cpu.cpu.mem_if.dat [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1056 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1090 (A=\servant.cpu.cpu.mem_if.dat [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1057 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1091 (A=\servant.cpu.cpu.mem_if.dat [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1058 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1500 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:126$505_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1476 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1205 (A=\servant.cpu.rf_ram_if.i_rreq, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1184 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1146 (A=$techmap\servant.ram.$and$../src/servant_1.0.2/servant/servant_ram.v:28$20_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1145 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1070 (A=\servant.cpu.cpu.mem_if.dat [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1037 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1196 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [1], B=1'1, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1188 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1195 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [0], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1187 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1197 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [2], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1189 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1199 (A=$techmap\servant.cpu.rf_ram_if.$procmux$609_Y [4], B=1'0, S=\servant.cpu.rf_ram_if.i_wreq) into $auto$simplemap.cc:420:simplemap_dff$1191 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1208 (A=1'0, B=\servant.cpu.rf_ram.o_rdata [1], S=\servant.cpu.rf_ram_if.rcnt [0]) into $auto$simplemap.cc:420:simplemap_dff$1193 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1206 (A=\servant.cpu.rf_ram_if.rreq_r, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1186 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1510 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:181$524_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1497 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1092 (A=\servant.cpu.cpu.mem_if.dat [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1059 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2003 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1800 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1093 (A=\servant.cpu.cpu.mem_if.dat [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1060 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1125 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1028 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1506 (A=$techmap\servant.cpu.cpu.state.$or$../src/serv_1.0.2/rtl/serv_state.v:157$515_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1486 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1508 (A=\servant.cpu.cpu.state.o_cnt_r [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1488 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1509 (A=\servant.cpu.cpu.state.o_cnt_r [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1489 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1504 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1493 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1113 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1016 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1498 (A=$techmap\servant.cpu.cpu.state.$and$../src/serv_1.0.2/rtl/serv_state.v:127$506_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1495 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1503 (A=$techmap\servant.cpu.cpu.state.$add$../src/serv_1.0.2/rtl/serv_state.v:156$510_Y [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1492 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1107 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1010 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2017 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [16], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1814 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1100 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1003 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2024 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [23], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1821 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2025 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [24], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1822 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2026 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [25], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1823 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2027 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [26], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1824 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2028 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [27], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1825 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2029 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [28], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1826 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2030 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [29], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1827 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2031 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [30], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1828 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2032 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [31], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1829 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2033 (A=\servant.cpu.cpu.ctrl.new_pc, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1830 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1507 (A=\servant.cpu.cpu.state.o_cnt_r [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1487 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2004 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1801 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2007 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [6], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1804 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2006 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [5], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1803 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2008 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [7], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1805 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2009 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [8], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1806 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2010 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [9], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1807 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2011 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [10], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1808 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2012 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [11], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1809 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2013 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [12], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1810 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2014 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [13], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1811 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2015 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [14], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1812 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2016 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [15], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1813 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2019 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [18], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1816 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2020 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [19], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1817 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2018 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [17], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1815 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2023 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [22], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1820 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2021 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [20], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1818 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1094 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [0], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$997 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2022 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [21], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1819 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$925 (A=$techmap\servant.servant_mux.$and$../src/servant_1.0.2/servant/servant_mux.v:44$45_Y, B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$924 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$2005 (A=\servant.cpu.cpu.ctrl.o_ibus_adr [4], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1802 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1095 (A=$auto$alumacc.cc:474:replace_alu$771.BB [1], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$998 (SB_DFFE). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1096 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [2], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$999 (SB_DFF). | |
| Merging $auto$simplemap.cc:277:simplemap_mux$1097 (A=$techmap\servant.timer.$add$../src/servant_1.0.2/servant/servant_timer.v:29$7_Y [3], B=1'0, S=\clock_gen.rst_reg [0]) into $auto$simplemap.cc:420:simplemap_dff$1000 (SB_DFF). | |
| 24.40. Executing ICE40_OPT pass (performing simple optimizations). | |
| 24.40.1. Running ICE40 specific optimizations. | |
| 24.40.2. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~242 debug messages> | |
| 24.40.3. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| <suppressed ~102 debug messages> | |
| Removed a total of 34 cells. | |
| 24.40.4. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.5. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| Removed 120 unused cells and 1419 unused wires. | |
| <suppressed ~121 debug messages> | |
| 24.40.6. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.40.7. Running ICE40 specific optimizations. | |
| 24.40.8. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| <suppressed ~4 debug messages> | |
| 24.40.9. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.40.10. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.11. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.40.12. Rerunning OPT passes. (Removed registers in this run.) | |
| 24.40.13. Running ICE40 specific optimizations. | |
| 24.40.14. Executing OPT_EXPR pass (perform const folding). | |
| Optimizing module service. | |
| 24.40.15. Executing OPT_MERGE pass (detect identical cells). | |
| Finding identical cells in module `\service'. | |
| Removed a total of 0 cells. | |
| 24.40.16. Executing OPT_RMDFF pass (remove dff with constant values). | |
| 24.40.17. Executing OPT_CLEAN pass (remove unused cells and wires). | |
| Finding unused cells or wires in module \service.. | |
| 24.40.18. Finished OPT passes. (There is nothing left to do.) | |
| 24.41. Executing TECHMAP pass (map to technology primitives). | |
| 24.41.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DLATCH_N_'. | |
| Generating RTLIL representation for module `\$_DLATCH_P_'. | |
| Successfully finished Verilog frontend. | |
| 24.41.2. Continuing TECHMAP pass. | |
| No more expansions possible. | |
| 24.42. Executing ABC pass (technology mapping using ABC). | |
| 24.42.1. Extracting gate netlist of module `\service' to `<abc-temp-dir>/input.blif'.. | |
| Extracted 682 gates and 929 wires to a netlist network with 245 inputs and 185 outputs. | |
| 24.42.1.1. Executing ABC. | |
| Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1 | |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". | |
| ABC: | |
| ABC: + read_blif <abc-temp-dir>/input.blif | |
| ABC: + read_lut <abc-temp-dir>/lutdefs.txt | |
| ABC: + strash | |
| ABC: + ifraig | |
| ABC: + scorr | |
| ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). | |
| ABC: + dc2 | |
| ABC: + dretime | |
| ABC: + retime | |
| ABC: + strash | |
| ABC: + dch -f | |
| ABC: + if | |
| ABC: + mfs2 | |
| ABC: + lutpack -S 1 | |
| ABC: + dress | |
| ABC: Total number of equiv classes = 292. | |
| ABC: Participating nodes from both networks = 607. | |
| ABC: Participating nodes from the first network = 291. ( 81.97 % of nodes) | |
| ABC: Participating nodes from the second network = 316. ( 89.01 % of nodes) | |
| ABC: Node pairs (any polarity) = 291. ( 81.97 % of names can be moved) | |
| ABC: Node pairs (same polarity) = 233. ( 65.63 % of names can be moved) | |
| ABC: Total runtime = 0.01 sec | |
| ABC: + write_blif <abc-temp-dir>/output.blif | |
| 24.42.1.2. Re-integrating ABC results. | |
| ABC RESULTS: $lut cells: 708 | |
| ABC RESULTS: internal signals: 499 | |
| ABC RESULTS: input signals: 245 | |
| ABC RESULTS: output signals: 185 | |
| Removing temp directory. | |
| Removed 0 unused cells and 859 unused wires. | |
| 24.43. Executing TECHMAP pass (map to technology primitives). | |
| 24.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v | |
| Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. | |
| Generating RTLIL representation for module `\$_DFF_N_'. | |
| Generating RTLIL representation for module `\$_DFF_P_'. | |
| Generating RTLIL representation for module `\$_DFFE_NN_'. | |
| Generating RTLIL representation for module `\$_DFFE_PN_'. | |
| Generating RTLIL representation for module `\$_DFFE_NP_'. | |
| Generating RTLIL representation for module `\$_DFFE_PP_'. | |
| Generating RTLIL representation for module `\$_DFF_NN0_'. | |
| Generating RTLIL representation for module `\$_DFF_NN1_'. | |
| Generating RTLIL representation for module `\$_DFF_PN0_'. | |
| Generating RTLIL representation for module `\$_DFF_PN1_'. | |
| Generating RTLIL representation for module `\$_DFF_NP0_'. | |
| Generating RTLIL representation for module `\$_DFF_NP1_'. | |
| Generating RTLIL representation for module `\$_DFF_PP0_'. | |
| Generating RTLIL representation for module `\$_DFF_PP1_'. | |
| Generating RTLIL representation for module `\$__DFFE_NN0'. | |
| Generating RTLIL representation for module `\$__DFFE_NN1'. | |
| Generating RTLIL representation for module `\$__DFFE_PN0'. | |
| Generating RTLIL representation for module `\$__DFFE_PN1'. | |
| Generating RTLIL representation for module `\$__DFFE_NP0'. | |
| Generating RTLIL representation for module `\$__DFFE_NP1'. | |
| Generating RTLIL representation for module `\$__DFFE_PP0'. | |
| Generating RTLIL representation for module `\$__DFFE_PP1'. | |
| Generating RTLIL representation for module `\$lut'. | |
| Successfully finished Verilog frontend. | |
| 24.43.2. Continuing TECHMAP pass. | |
| Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111101011000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00011100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101010101100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0101000011001111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110100010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000000010001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111000100010111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000011101111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111001000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0100001101110101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100110011001010 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0001011101110111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1011111000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100000001 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1110100000000000 for cells of type $lut. | |
| Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. | |
| No more expansions possible. | |
| <suppressed ~1498 debug messages> | |
| Removed 0 unused cells and 708 unused wires. | |
| 24.44. Executing HIERARCHY pass (managing design hierarchy). | |
| 24.44.1. Analyzing design hierarchy.. | |
| Top module: \service | |
| 24.44.2. Analyzing design hierarchy.. | |
| Top module: \service | |
| Removed 0 unused modules. | |
| 24.45. Printing statistics. | |
| === service === | |
| Number of wires: 673 | |
| Number of wire bits: 2510 | |
| Number of public wires: 334 | |
| Number of public wire bits: 2046 | |
| Number of memories: 0 | |
| Number of memory bits: 0 | |
| Number of processes: 0 | |
| Number of cells: 733 | |
| SB_CARRY 74 | |
| SB_DFF 20 | |
| SB_DFFE 119 | |
| SB_DFFESR 68 | |
| SB_DFFSR 47 | |
| SB_DFFSS 1 | |
| SB_LUT4 401 | |
| SB_RAM40_4K 3 | |
| 24.46. Executing CHECK pass (checking for obvious problems). | |
| checking module service.. | |
| found and reported 0 problems. | |
| 25. Executing BLIF backend. | |
| 26. Executing JSON backend. | |
| 27. Executing EDIF backend. | |
| Warning: Bit 0 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 1 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 2 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 3 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 4 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 5 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 6 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 7 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 8 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 9 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 10 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 11 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 12 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 13 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 14 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 15 of cell port service.servant.cpu.rf_ram.memory.0.0.0.MASK driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 0 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 1 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 2 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 4 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 5 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 6 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 7 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 8 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 9 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 10 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 12 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 13 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 14 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warning: Bit 15 of cell port service.servant.cpu.rf_ram.memory.0.0.0.WDATA driven by 1'x will be left unconnected in EDIF output. | |
| Warnings: 30 unique messages, 30 total | |
| End of script. Logfile hash: 90989b5104 | |
| CPU: user 1.99s system 0.05s, MEM: 80.79 MB total, 63.09 MB resident | |
| Yosys 0.9 (git sha1 1979e0b) | |
| Time spent: 25% 23x opt_clean (0 sec), 12% 22x opt_expr (0 sec), ... |
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Work in progress changes: olofk/serv@main...ddribin:wip/go-board
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