KiCad DRC rules for JLCPCB, 4-layer PCB

rules.txt

(version 1)

# 4-layer, 1oz copper
(rule "Minimum Trace Width and Spacing (inner layer)"
	(constraint track_width (min 5mil))
	(constraint clearance (min 5mil))
	(layer inner)
	(condition "A.Type == 'track'"))

(rule "Minimum Trace Width and Spacing (outer layer)"
	(constraint track_width (min 3.5mil))
	(constraint clearance (min 3.5mil))
	(layer outer)
	(condition "A.Type == 'track'"))

# silkscreen
(rule "Minimum line width"
	(constraint track_width (min 6mil))
	(layer "F.Silkscreen") (layer "B.Silkscreen"))

(rule "Pad to Silkscreen"
	(constraint clearance (min 0.15mm))
	(layer outer)
	(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

# edge clearance
(rule "Trace to Outline"
	(constraint edge_clearance (min 0.2mm))
	(condition "A.Type == 'track'"))

(rule "Trace to V-Cut"
	(constraint clearance (min 0.4mm))
	(condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))

# drill/hole size
(rule "drill hole size (mechanical)"
	(constraint hole (min 0.2mm) (max 6.3mm))
	(condition "A.Type == 'hole'"))

(rule "Minimum Via Hole Size"
	(constraint hole (min 0.2mm))
	(condition "A.Type == 'via'"))

(rule "Minimum Via Diameter"
	(constraint length (min 0.4mm))
	(condition "A.Type == 'via'"))

(rule "PTH Hole Size"
	(constraint hole (min 0.2mm) (max 6.35mm))
	(condition "A.isPlated()"))

(rule "PTH Size"
	(constraint length (min 0.7mm) (max 6.35mm))
	(condition "A.isPlated()"))

(rule "Minimum Non-plated Hole Size"
	(constraint hole (min 0.5mm))
	(condition "A.Type == 'pad' && !A.isPlated()"))

# clearance
(rule "via to track clearance"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == 'track'"))

(rule "via to via clearance (same nets)"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == 'via' && A.Net == B.Net"))

(rule "pad to pad clearance (with hole, different nets)"
	(constraint hole_clearance (min 0.5mm))
	(condition "A.Type == 'through-hole' && B.Type == A.Type && A.Net != B.Net"))

(rule "pad to pad clearance (without hole, different nets)"
	(constraint clearance (min 0.127mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "NPTH to Track clearance)"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))

(rule "PTH to Track clearance)"
	(constraint hole_clearance (min 0.33mm))
	(condition "A.isPlated() && B.Type == 'track'"))

(rule "Pad to Track clearance)"
	(constraint clearance (min 0.2mm))
	(condition "A.isPlated() && B.Type == 'track'"))

Hi,

shouldn't instead of:

(rule "Minimum Via Diameter"
	(constraint length (min 0.4mm))
	(condition "A.Type == 'via'"))

be:

(rule "Minimum Via Diameter"
	(constraint via_diameter (min 0.4mm))
	(condition "A.Type == 'via'"))

?

And the same for the PTH Size rule?

From where is number 0.7 mm in PTH Size rule? I don't see 0.7 mm in any JLCPCB parameter. Did you calculate that parameter as 0.2*PI and rounded it to 0.7?

The Minimum line width rule for silkscreen doesn't work for 2 reasons:

1. layer can be specified only once. Instead of (layer "F.Silkscreen") (layer "B.Silkscreen") it should be (layer "?.Silkscreen")
2. track_width is not thickness of the silkscreen and there isn't thickness constraint type

Text thickness constraint has been added in Kicad 7.

# silkscreen
(rule "Minimum Text"
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
	(layer "?.Silkscreen"))

There are also some rules which incorrectly use hole_clearance, these should work with Kicad 6.

(rule "via to via clearance (same nets)"
	(constraint hole_to_hole (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))

(rule "pad to pad clearance (with hole, different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

Kicad 7 - Rules.txt