Makefile

Makefile

# GHDL simulation makefile
# This requires the top level entity to have "_tb" as a suffix.

# VHDL compiler
VHDLC = ghdl

# Our waveform viewer
WAVEVIEWER = gtkwave
WORKDIR = work

# The source file extension; ie `.vhd` or `.vhdl` SRC_EXT = .vhd The source 
# files are any files with the source extension
SRC_EXT = vhd

SOURCES := $(wildcard *.$(SRC_EXT))

# Test bench files have "_tb" (case-insensitive) somewhere in the file and end
# in the file extension.
TEST_BENCH_FILE := $(shell basename $$(find . -iname "*_tb.$(SRC_EXT)"))

SOURCES := $(filter-out $(TEST_BENCH_FILE), $(SOURCES))

# This is the top level entity that we will elaborate on. It is the test bench
# file with the extension stripped.
TOP_LEVEL_ENTITY := $(basename $(TEST_BENCH_FILE))

# Remove the top-level entity from the sources because we want to analyze all 
# SOURCES := $(filter-out $(wildcard $(TOP_LEVEL_ENTITY)*.$(SRC_EXT)), $(SOURCES))

# The object files are the same as the source files except ending in .o
OBJECTS := $(patsubst %$.(SRC_EXT), %.o, $(SOURCES))

VHDLC_FLAGS = -Wuseless --workdir=$(WORKDIR) --std=08

STOP_TIME = 20us
SIM_FLAGS = --stop-time=$(STOP_TIME)

all: build

build:
	mkdir -p $(WORKDIR)
	$(MAKE) elaborate

analyze:
	$(VHDLC) -a $(VHDLC_FLAGS) $(SOURCES)
	$(VHDLC) -a $(VHDLC_FLAGS) $(TEST_BENCH_FILE)

elaborate: analyze
	$(VHDLC) -e $(VHDLC_FLAGS) $(TOP_LEVEL_ENTITY)

# We must analyze the source files and elaborate on the top level entity before
# running a simulation
run: $(OBJECTS) 
	$(VHDLC) -r $(VHDLC_FLAGS) $(TOP_LEVEL_ENTITY) --vcd=$(TOP_LEVEL_ENTITY).vcd $(SIM_FLAGS)
	mv $(TOP_LEVEL_ENTITY).vcd $(WORKDIR)/

view:
	$(WAVEVIEWER) --dump=$(WORKDIR)/$(TOP_LEVEL_ENTITY).vcd

clean:
	rm -rfd $(WORKDIR)
	rm -rf *.o
	rm -f $(shell echo $(TOP_LEVEL_ENTITY) | tr '[:upper:]' '[:lower:]')

.PHONY: clean all