Attempt at register file

register_file.hs

module Hs8b.Register where

import Clash.Prelude

type Reg = Unsigned 4
type Value = Unsigned 8

{-# ANN registerFileMono Synthesize
    { t_name = "register_file"
    , t_inputs = PortName <$> words "clk rst write read"
    , t_output = PortName "out"
    } #-}

registerFileMono
    :: Clock XilinxSystem
    -> Reset XilinxSystem
    -> Signal XilinxSystem (Maybe (Reg, Value))
    -> Signal XilinxSystem Reg
    -> Signal XilinxSystem Reg
    -> (Signal XilinxSystem Value, Signal XilinxSystem Value)
registerFileMono clk rst = exposeClockResetEnable registerFile clk rst enableGen

registerFile
    ::
    ( KnownDomain dom
    , HiddenClockResetEnable dom
    )
    => Signal dom (Maybe (Reg, Value))
    -> Signal dom Reg
    -> Signal dom Reg
    -> (Signal dom Value, Signal dom Value)
registerFile w a1 a2 = (liftA2 fetch file a1, liftA2 fetch file a2)
    where
        file = register (replicate d16 0) next
        next = liftA2 go w file

        fetch f r = f !! r

        go Nothing rs = rs
        go (Just (wr, new)) rs = replace wr new rs

register_file.v

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.0.0. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module register_file
    ( // Inputs
      input  clk // clock
    , input  rst // reset
    , input [12:0] write
    , input [3:0] read
    , input [3:0] eta2

      // Outputs
    , output wire [15:0] out
    );
  wire [7:0] result;
  wire [7:0] result_0;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire signed [63:0] wild2;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire signed [63:0] wild2_0;
  wire [127:0] result_1;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire [127:0] c$file_app_arg;
  wire [127:0] result_2;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire [7:0] new;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire [11:0] ds1;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire signed [63:0] wild2_1;
  // /home/dram/code/hs8b/src/Hs8b/Register.hs:(23,1)-(31,43)
  wire [3:0] wr;

  assign out = {result_0,result};

  // index begin
  wire [7:0] vecArray [0:16-1];
  genvar i;
  generate
  for (i=0; i < 16; i=i+1) begin : mk_array
    assign vecArray[(16-1)-i] = result_1[i*8+:8];
  end
  endgenerate
  assign result = vecArray[(wild2)];
  // index end

  // index begin
  wire [7:0] vecArray_0 [0:16-1];
  genvar i_0;
  generate
  for (i_0=0; i_0 < 16; i_0=i_0+1) begin : mk_array_0
    assign vecArray_0[(16-1)-i_0] = result_1[i_0*8+:8];
  end
  endgenerate
  assign result_0 = vecArray_0[(wild2_0)];
  // index end

  assign wild2 = $signed(($signed({{(64-4) {1'b0}},eta2})));

  assign wild2_0 = $signed(($signed({{(64-4) {1'b0}},read})));

  // register begin
  reg [127:0] result_1_reg  = {8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0} ;
  always @(posedge clk ) begin : result_1_register
    if ( rst) begin
      result_1_reg <= {8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0,8'd0};
    end else   begin
      result_1_reg <= c$file_app_arg;
    end
  end
  assign result_1 = result_1_reg;
  // register end

  assign c$file_app_arg = write[12:12] ? result_2 : result_1;

  // vector replace begin
  genvar i_1;
  generate
  for (i_1=0;i_1<16;i_1=i_1+1) begin : vector_replace
    assign result_2[(15-i_1)*8+:8] = (wild2_1) == i_1 ? new : result_1[(15-i_1)*8+:8];
  end
  endgenerate
  // vector replace end

  assign new = ds1[7:0];

  assign ds1 = write[11:0];

  assign wild2_1 = $signed(($signed({{(64-4) {1'b0}},wr})));

  assign wr = ds1[11:8];


endmodule