Yosys the Verilog pretty printer?

chisel-acc.scala

class AccModule extends Module {
    val io = IO(new Bundle{
        val in = Input(UInt(32.W))
        val out = Output(UInt(32.W))
    })
    
    val reg = RegInit(0.U(32.W))
    reg := reg + io.in
    io.out := reg
}

print(getVerilog(new AccModule))

chisel-acc.v

module cmd4HelperAccModule(
  input         clock,
  input         reset,
  input  [31:0] io_in,
  output [31:0] io_out
);
  reg [31:0] reg_; // @[cmd4.sc 7:22]
  reg [31:0] _RAND_0;
  wire [31:0] _T_1; // @[cmd4.sc 8:16]
  assign _T_1 = reg_ + io_in; // @[cmd4.sc 8:16]
  assign io_out = reg_; // @[cmd4.sc 9:12]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[31:0];
  `endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end
  always @(posedge clock) begin
    if (reset) begin
      reg_ <= 32'h0;
    end else begin
      reg_ <= _T_1;
    end
  end
endmodule

clash-acc.hs

module PlayClash.Stateful where

import Clash.Prelude

type Sys = XilinxSystem

acc
    :: (KnownDomain dom, HiddenClockResetEnable dom)
    => Signal dom (Unsigned 32) -> Signal dom (Unsigned 32)
acc a = r
    where r = register 0 (r + a)

-- And all the following is really just to define an interface (:facepalm:)

{-# ANN acc32 Synthesize
    { t_name = "acc"
    , t_inputs =
        [ PortName "clk"
        , PortName "rst"
        , PortName "in"
        ]
    , t_output = PortName "out"
    } #-}
acc32
    :: Clock Sys
    -> Reset Sys
    -> Signal Sys (Unsigned 32)
    -> Signal Sys (Unsigned 32)
acc32 clk rst = exposeClockResetEnable (acc @Sys) clk rst enableGen

clash-acc.v

/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.0.0. DO NOT MODIFY.
*/
`timescale 100fs/100fs
module acc
    ( // Inputs
      input  clk // clock
    , input  rst // reset
    , input [31:0] in

      // Outputs
    , output wire [31:0] out
    );
  wire [31:0] c$result_rec;

  // register begin
  reg [31:0] c$result_rec_reg  = 32'd0 ;
  always @(posedge clk ) begin : c$result_rec_register
    if ( rst) begin
      c$result_rec_reg <= 32'd0;
    end else   begin
      c$result_rec_reg <= (c$result_rec + in);
    end
  end
  assign c$result_rec = c$result_rec_reg;
  // register end

  assign out = c$result_rec;


endmodule

yosys-chisel-acc.v

module cmd4HelperAccModule(clock, reset, io_in, io_out);
  wire [31:0] _0_;
  wire [31:0] _T_1;
  input clock;
  input [31:0] io_in;
  output [31:0] io_out;
  reg [31:0] io_out;
  input reset;
  assign _T_1 = io_out + io_in;
  always @(posedge clock)
      io_out <= _0_;
  assign _0_ = reset ? 32'd0 : _T_1;
endmodule

yosys-clash-acc.v

module acc(clk, rst, in, out);
  wire [31:0] _0_;
  wire [31:0] _1_;
  wire [31:0] \c$result_rec_reg ;
  input clk;
  input [31:0] in;
  output [31:0] out;
  reg [31:0] out;
  input rst;
  assign _1_ = out + in;
  always @(posedge clk)
      out <= _0_;
  assign _0_ = rst ? 32'd0 : _1_;
  assign \c$result_rec_reg  = out;
endmodule

yosys-command.txt

read_verilog verilog_file.v
proc ;;; write_verilog -noattr /dev/stdout ; show -notitle -width -colors 1

No important differences in graphs, as expected:

• Yosys show for Chisel:
  

• Yosys show for Clash: