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August 16, 2021 02:17
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IDA ATmega328P config
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| .ATmega328P | |
| ; Append to your IDA avr.cfg | |
| SUBARCH=5 | |
| RAM=2048 | |
| ROM=32768 | |
| EEPROM=1024 | |
| ; MEMORY MAP | |
| ; Memory configuration A | |
| area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers | |
| area DATA FSR_ 0x0020:0x0060 I/O registers | |
| area DATA EXTIO_ 0x0060:0x0100 I/O registers | |
| area DATA I_SRAM 0x0100:0x08ff Internal SRAM | |
| ; Interrupt and reset vector assignments | |
| entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset | |
| entry INT0_ 0x0002 External Interrupt Request 0 | |
| entry INT1_ 0x0004 External Interrupt Request 1 | |
| entry PCINT0_ 0x0006 Pin Change Interrupt Request 0 | |
| entry PCINT1_ 0x0008 Pin Change Interrupt Request 1 | |
| entry PCINT2_ 0x000A Pin Change Interrupt Request 2 | |
| entry WDT 0x000C Watchdog Time-out Interrupt | |
| entry TIMER2_COMPA 0x000E Timer/Counter2 Compare Match A | |
| entry TIMER2_COMPB 0x0010 Timer/Counter2 Compare Match B | |
| entry TIMER2_OVF 0x0012 Timer/Counter2 Overflow | |
| entry TIMER1_CAPT 0x0014 Timer/Counter1 Compare Match | |
| entry TIMER1_COMPA 0x0016 Timer/Counter1 Compare Match A | |
| entry TIMER1_COMPB 0x0018 Timer/Counter1 Compare Match A | |
| entry TIMER2_OVF 0x001A Timer/Counter1 Overflow | |
| entry TIMER0_COMPA 0x001C Timer/Counter0 Compare Match A | |
| entry TIMER0_COMPB 0x001E Timer/Counter0 Compare Match B | |
| entry TIMER0_OVF 0x0020 Timer/Counter0 Overflow | |
| entry SPI_STC 0x0022 Serial Transfer Complete | |
| entry USART0_RXC 0x0024 USART Rx Complete | |
| entry USART0_UDRE 0x0026 USART Data Register Empty | |
| entry USART0_TXC 0x0028 USART Tx Complete | |
| entry ADC 0x002A ADC Conversion Complete | |
| entry EE_READY 0x002C EEPROM Ready | |
| entry ANALOG_COMP 0x002E Analog Comparator | |
| entry TWI 0x0030 2-wire Serial Interface | |
| entry SPM_READY 0x0032 Store Program Memory Ready | |
| ; INPUT/OUTPUT PORTS | |
| ; 0x0000 Reserved | |
| ; 0x0001 Reserved | |
| ; 0x0002 Reserved | |
| PINB 0x0003 | |
| PINB.PINB7 7 | |
| PINB.PINB6 6 | |
| PINB.PINB5 5 | |
| PINB.PINB4 4 | |
| PINB.PINB3 3 | |
| PINB.PINB2 2 | |
| PINB.PINB1 1 | |
| PINB.PINB0 0 | |
| DDRB 0x0004 | |
| DDRB.DDB7 7 | |
| DDRB.DDB6 6 | |
| DDRB.DDB5 5 | |
| DDRB.DDB4 4 | |
| DDRB.DDB3 3 | |
| DDRB.DDB2 2 | |
| DDRB.DDB1 1 | |
| DDRB.DDB0 0 | |
| PORTB 0x0005 | |
| PORTB.PORTB7 7 | |
| PORTB.PORTB6 6 | |
| PORTB.PORTB5 5 | |
| PORTB.PORTB4 4 | |
| PORTB.PORTB3 3 | |
| PORTB.PORTB2 2 | |
| PORTB.PORTB1 1 | |
| PORTB.PORTB0 0 | |
| PINC 0x0006 | |
| PINC.PINC7 7 | |
| PINC.PINC6 6 | |
| PINC.PINC5 5 | |
| PINC.PINC4 4 | |
| PINC.PINC3 3 | |
| PINC.PINC2 2 | |
| PINC.PINC1 1 | |
| PINC.PINC0 0 | |
| DDRC 0x0007 | |
| DDRC.DDC7 7 | |
| DDRC.DDC6 6 | |
| DDRC.DDC5 5 | |
| DDRC.DDC4 4 | |
| DDRC.DDC3 3 | |
| DDRC.DDC2 2 | |
| DDRC.DDC1 1 | |
| DDRC.DDC0 0 | |
| PORTC 0x0008 | |
| PORTC.PORTC7 7 | |
| PORTC.PORTC6 6 | |
| PORTC.PORTC5 5 | |
| PORTC.PORTC4 4 | |
| PORTC.PORTC3 3 | |
| PORTC.PORTC2 2 | |
| PORTC.PORTC1 1 | |
| PORTC.PORTC0 0 | |
| PIND 0x0009 | |
| PIND.PIND7 7 | |
| PIND.PIND6 6 | |
| PIND.PIND5 5 | |
| PIND.PIND4 4 | |
| PIND.PIND3 3 | |
| PIND.PIND2 2 | |
| PIND.PIND1 1 | |
| PIND.PIND0 0 | |
| DDRD 0x000A Port D Data Direction Register | |
| DDRD.DDD7 7 | |
| DDRD.DDD6 6 | |
| DDRD.DDD5 5 | |
| DDRD.DDD4 4 | |
| DDRD.DDD3 3 | |
| DDRD.DDD2 2 | |
| DDRD.DDD1 1 | |
| DDRD.DDD0 0 | |
| PORTD 0x000B | |
| PORTD.PORTD7 7 | |
| PORTD.PORTD6 6 | |
| PORTD.PORTD5 5 | |
| PORTD.PORTD4 4 | |
| PORTD.PORTD3 3 | |
| PORTD.PORTD2 2 | |
| PORTD.PORTD1 1 | |
| PORTD.PORTD0 0 | |
| ;0x0c-0x14 Reserved | |
| TIFR0 0x0015 Timer/Counter Interrupt Flag Register | |
| TIFR0.OCF0B 2 Timer/Counter0, Output Compare B Match Flag | |
| TIFR0.OCF0A 1 Timer/Counter0, Output Compare A Match Flag | |
| TIFR0.TOV0 0 Timer/Counter0 Overflow Flag | |
| TIFR1 0x0016 Timer/Counter Interrupt Flag Register | |
| TIFR1.ICF1 5 Timer/Counter1, Input Capture Flag | |
| TIFR1.OCF1B 2 Timer/Counter1, Output Compare B Match Flag | |
| TIFR1.OCF1A 1 Timer/Counter1, Output Compare A Match Flag | |
| TIFR1.TOV1 0 Timer/Counter1 Overflow Flag | |
| TIFR2 0x0017 Timer/Counter Interrupt Flag Register | |
| TIFR2.OCF2B 2 Timer/Counter2, Output Compare B Match Flag | |
| TIFR2.OCF2A 1 Timer/Counter2, Output Compare A Match Flag | |
| TIFR2.TOV2 0 Timer/Counter2 Overflow Flag | |
| PCIFR 0x001B | |
| PCIFR.PCIF2 2 | |
| PCIFR.PCIF1 1 | |
| PCIFR.PCIF0 0 | |
| EIFR 0x001C | |
| EIFR.INTF1 1 | |
| EIFR.INTF0 0 | |
| EIMSK 0x001D | |
| EIMSK.INT1 1 | |
| EIMSK.INT0 0 | |
| GPIOR0 0x001E | |
| EECR 0x001F The EEPROM Control Register | |
| EECR.EERIE 3 EEPROM Ready Interrupt Enable | |
| EECR.EEMWE 2 EEPROM Master Write Enable | |
| EECR.EEWE 1 EEPROM Write Enable | |
| EECR.EERE 0 EEPROM Read Enable | |
| EEDR 0x0020 EEPROM Data Register | |
| EEARL 0x0021 EEPROM Address Register Low Byte | |
| EEARH 0x0022 The EEPROM Address Register High | |
| EEARH.EEAR8 8 EEPROM Address 8 | |
| GTCCR 0x0023 | |
| GTCCR.TSM 7 | |
| GTCCR.PSRASY 1 | |
| GTCCR.PSRSYNC 0 | |
| TCCR0A 0x0024 | |
| TCCR0A.COM0A1 7 | |
| TCCR0A.COM0A0 6 | |
| TCCR0A.COM0B1 5 | |
| TCCR0A.COM0B0 4 | |
| TCCR0A.WGM01 1 | |
| TCCR0A.WGM00 0 | |
| TCCR0B 0x0025 | |
| TCCR0B.FOC0A 7 | |
| TCCR0B.FOC0B 6 | |
| TCCR0B.WGM02 3 | |
| TCCR0B.CS02 2 | |
| TCCR0B.CS01 1 | |
| TCCR0B.CS00 0 | |
| TCNT0 0x0026 Timer/Counter0 | |
| OCR0A 0x0027 | |
| OCR0B 0x0028 | |
| GPIOR1 0x002A | |
| GPIOR2 0x002B | |
| SPCR 0x002C SPI Control Register- | |
| SPCR.SPIE 7 SPI Interrupt Enable | |
| SPCR.SPE 6 SPI Enable | |
| SPCR.DORD 5 Data Order | |
| SPCR.MSTR 4 Master/Slave Select | |
| SPCR.CPOL 3 Clock Polarity | |
| SPCR.CPHA 2 Clock Phase | |
| SPCR.SPR1 1 SPI Clock Rate Select 1 | |
| SPCR.SPR0 0 SPI Clock Rate Select 0 | |
| SPSR 0x002D SPI Status Register | |
| SPSR.SPIF 7 SPI Interrupt Flag | |
| SPSR.WCOL 6 Write COLlision Flag | |
| SPSR.SPI2X 0 Double SPI Speed Bit | |
| SPDR 0x002E SPI Data Register | |
| ACSR 0x0030 Analog Comparator Control and Status Register | |
| ACSR.ACD 7 Analog Comparator Disable | |
| ACSR.ACBG 6 Analog Comparator Bandgap Select | |
| ACSR.ACO 5 Analog Comparator Output | |
| ACSR.ACI 4 Analog Comparator Interrupt Flag | |
| ACSR.ACIE 3 Analog Comparator Interrupt Enable | |
| ACSR.ACIC 2 Analog Comparator Input Capture Enable | |
| ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1 | |
| ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0 | |
| SMCR 0x0033 | |
| SMCR.SM2 3 | |
| SMCR.SM1 2 | |
| SMCR.SM0 1 | |
| SMCR.SE 0 | |
| MCUSR 0x0034 | |
| MCUSR.WDRF 3 | |
| MCUSR.BORF 2 | |
| MCUSR.EXTRF 1 | |
| MCUSR.PORF 0 | |
| MCUCR 0x0035 | |
| MCUCR.BODS 6 | |
| MCUCR.BODSE 5 | |
| MCUCR.PUD 4 | |
| MCUCR.IVSEL 1 | |
| MCUCR.IVCE 0 | |
| SPMCSR 0x0037 | |
| SPMCSR.SPMIE 7 | |
| SPMCSR.(RWWSB)5. 6 | |
| SPMCSR.(RWWSRE)5. 4 | |
| SPMCSR.BLBSET 3 | |
| SPMCSR.PGWRT 2 | |
| SPMCSR.PGERS 1 | |
| SPMCSR.SELFPRGEN 0 | |
| SPL 0x003D | |
| SPL.SP7 7 | |
| SPL.SP6 6 | |
| SPL.SP5 5 | |
| SPL.SP4 4 | |
| SPL.SP3 3 | |
| SPL.SP2 2 | |
| SPL.SP1 1 | |
| SPL.SP0 0 | |
| SPH 0x003E | |
| SPH.(SP10) 2 | |
| SPH.5. 1 | |
| SPH.SP9 0 | |
| SREG 0x003F | |
| SREG.I 7 | |
| SREG.T 6 | |
| SREG.H 5 | |
| SREG.S 4 | |
| SREG.V 3 | |
| SREG.N 2 | |
| SREG.Z 1 | |
| SREG.C 0 | |
| ;; was able to mirror the rest from Atmega168P | |
| WDTCSR 0x0040 | |
| WDTCSR.WDIF 7 | |
| WDTCSR.WDIE 6 | |
| WDTCSR.WDP3 5 | |
| WDTCSR.WDCE 4 | |
| WDTCSR.WDE 3 | |
| WDTCSR.WDP2 2 | |
| WDTCSR.WDP1 1 | |
| WDTCSR.WDP0 0 | |
| CLKPR 0x0041 | |
| CLKPR.CLKPCE 7 | |
| CLKPR.CLKPS3 3 | |
| CLKPR.CLKPS2 2 | |
| CLKPR.CLKPS1 1 | |
| CLKPR.CLKPS0 0 | |
| PRR 0x0044 | |
| PRR.PRTWI 7 | |
| PRR.PRTIM2 6 | |
| PRR.PRTIM0 5 | |
| PRR.PRTIM1 3 | |
| PRR.PRSPI 2 | |
| PRR.PRUSART0 1 | |
| PRR.PRADC 0 | |
| OSCCAL 0x0046 | |
| PCICR 0x0048 | |
| PCICR.PCIE2 2 | |
| PCICR.PCIE1 1 | |
| PCICR.PCIE0 0 | |
| ADCH 0x0059 | |
| ADCL 0x0058 | |
| TIMSK2 0x0050 | |
| TIMSK2.OCIE2B 2 | |
| TIMSK2.OCIE2A 1 | |
| TIMSK2.TOIE2 0 | |
| TIMSK1 0x004F | |
| TIMSK1.ICIE1 5 | |
| TIMSK1.OCIE1B 2 | |
| TIMSK1.OCIE1A 1 | |
| TIMSK1.TOIE1 0 | |
| TIMSK0 0x004E | |
| TIMSK0.OCIE0B 2 | |
| TIMSK0.OCIE0A 1 | |
| TIMSK0.TOIE0 0 | |
| PCMSK2 0x004D | |
| PCMSK2.PCINT23 7 | |
| PCMSK2.PCINT22 6 | |
| PCMSK2.PCINT21 5 | |
| PCMSK2.PCINT20 4 | |
| PCMSK2.PCINT19 3 | |
| PCMSK2.PCINT18 2 | |
| PCMSK2.PCINT17 1 | |
| PCMSK2.PCINT16 0 | |
| PCMSK1 0x004C | |
| PCMSK1.PCINT14 6 | |
| PCMSK1.PCINT13 5 | |
| PCMSK1.PCINT12 4 | |
| PCMSK1.PCINT11 3 | |
| PCMSK1.PCINT10 2 | |
| PCMSK1.PCINT9 1 | |
| PCMSK1.PCINT8 0 | |
| PCMSK0 0x004B | |
| PCMSK0.PCINT7 7 | |
| PCMSK0.PCINT6 6 | |
| PCMSK0.PCINT5 5 | |
| PCMSK0.PCINT4 4 | |
| PCMSK0.PCINT3 3 | |
| PCMSK0.PCINT2 2 | |
| PCMSK0.PCINT1 1 | |
| PCMSK0.PCINT0 0 | |
| EICRA 0x0049 | |
| EICRA.ISC11 3 | |
| EICRA.ISC10 2 | |
| EICRA.ISC01 1 | |
| EICRA.ISC00 0 | |
| DIDR1 0x005F | |
| DIDR1.AIN1D 1 | |
| DIDR1.AIN0D 0 | |
| DIDR0 0x005E | |
| DIDR0.ADC5D 5 | |
| DIDR0.ADC4D 4 | |
| DIDR0.ADC3D 3 | |
| DIDR0.ADC2D 2 | |
| DIDR0.ADC1D 1 | |
| DIDR0.ADC0D 0 | |
| ADMUX 0x005C | |
| ADMUX.REFS1 7 | |
| ADMUX.REFS0 6 | |
| ADMUX.ADLAR 5 | |
| ADMUX.MUX3 3 | |
| ADMUX.MUX2 2 | |
| ADMUX.MUX1 1 | |
| ADMUX.MUX0 0 | |
| ADCSRB 0x005B | |
| ADCSRB.ACME 6 | |
| ADCSRB.ADTS2 2 | |
| ADCSRB.ADTS1 1 | |
| ADCSRB.ADTS0 0 | |
| ADCSRA 0x005A | |
| ADCSRA.ADEN 7 | |
| ADCSRA.ADSC 6 | |
| ADCSRA.ADATE 5 | |
| ADCSRA.ADIF 4 | |
| ADCSRA.ADIE 3 | |
| ADCSRA.ADPS2 2 | |
| ADCSRA.ADPS1 1 | |
| ADCSRA.ADPS0 0 | |
| UDR0 0x00A6 | |
| UBRR0H 0x00A5 | |
| UBRR0L 0x00A4 | |
| UCSR0C 0x00A2 | |
| UCSR0C.UMSEL01 7 | |
| UCSR0C.UMSEL00 6 | |
| UCSR0C.UPM01 5 | |
| UCSR0C.UPM00 4 | |
| UCSR0C.USBS0 3 | |
| UCSR0C.UCSZ01 2 | |
| UCSR0C._UDORD0 1 | |
| UCSR0C.UCSZ00 0 | |
| UCSR0B 0x00A1 | |
| UCSR0B.RXCIE0 7 | |
| UCSR0B.TXCIE0 6 | |
| UCSR0B.UDRIE0 5 | |
| UCSR0B.RXEN0 4 | |
| UCSR0B.TXEN0 3 | |
| UCSR0B.UCSZ02 2 | |
| UCSR0B.RXB80 1 | |
| UCSR0B.TXB80 0 | |
| UCSR0A 0x00A0 | |
| UCSR0A.RXC0 7 | |
| UCSR0A.TXC0 6 | |
| UCSR0A.UDRE0 5 | |
| UCSR0A.FE0 4 | |
| UCSR0A.DOR0 3 | |
| UCSR0A.UPE0 2 | |
| UCSR0A.U2X0 1 | |
| UCSR0A.MPCM0 0 | |
| TWAMR 0x009D | |
| TWAMR.TWAM6 7 | |
| TWAMR.TWAM5 6 | |
| TWAMR.TWAM4 5 | |
| TWAMR.TWAM3 4 | |
| TWAMR.TWAM2 3 | |
| TWAMR.TWAM1 2 | |
| TWAMR.TWAM0 1 | |
| TWCR 0x009C | |
| TWCR.TWINT 7 | |
| TWCR.TWEA 6 | |
| TWCR.TWSTA 5 | |
| TWCR.TWSTO 4 | |
| TWCR.TWWC 3 | |
| TWCR.TWEN 2 | |
| TWCR.TWIE 0 | |
| TWDR 0x009B | |
| TWAR 0x009A | |
| TWAR.TWA6 7 | |
| TWAR.TWA5 6 | |
| TWAR.TWA4 5 | |
| TWAR.TWA3 4 | |
| TWAR.TWA2 3 | |
| TWAR.TWA1 2 | |
| TWAR.TWA0 1 | |
| TWAR.TWGCE 0 | |
| TWSR 0x0099 | |
| TWSR.TWS7 7 | |
| TWSR.TWS6 6 | |
| TWSR.TWS5 5 | |
| TWSR.TWS4 4 | |
| TWSR.TWS3 3 | |
| TWSR.TWPS1 1 | |
| TWSR.TWPS0 0 | |
| TWBR 0x0098 | |
| ASSR 0x0096 | |
| ASSR.EXCLK 6 | |
| ASSR.AS2 5 | |
| ASSR.TCN2UB 4 | |
| ASSR.OCR2AUB 3 | |
| ASSR.OCR2BUB 2 | |
| ASSR.TCR2AUB 1 | |
| ASSR.TCR2BUB 0 | |
| OCR2B 0x0094 | |
| OCR2A 0x0093 | |
| TCNT2 0x0092 | |
| TCCR2B 0x0091 | |
| TCCR2B.FOC2A 7 | |
| TCCR2B.FOC2B 6 | |
| TCCR2B.WGM22 3 | |
| TCCR2B.CS22 2 | |
| TCCR2B.CS21 1 | |
| TCCR2B.CS20 0 | |
| TCCR2A 0x0090 | |
| TCCR2A.COM2A1 7 | |
| TCCR2A.COM2A0 6 | |
| TCCR2A.COM2B1 5 | |
| TCCR2A.COM2B0 4 | |
| TCCR2A.WGM21 1 | |
| TCCR2A.WGM20 0 | |
| OCR1BH 0x006B | |
| OCR1BH.Timer_Counter1 7 | |
| OCR1BH.Output 5 | |
| OCR1BH.Compare 4 | |
| OCR1BH.Register 3 | |
| OCR1BH.B 2 | |
| OCR1BH.High 1 | |
| OCR1BH.Byte 0 | |
| OCR1BL 0x006A | |
| OCR1BL.Timer_Counter1 7 | |
| OCR1BL.Output 5 | |
| OCR1BL.Compare 4 | |
| OCR1BL.Register 3 | |
| OCR1BL.B 2 | |
| OCR1BL.Low 1 | |
| OCR1BL.Byte 0 | |
| OCR1AH 0x0069 | |
| OCR1AH.Timer_Counter1 7 | |
| OCR1AH.Output 5 | |
| OCR1AH.Compare 4 | |
| OCR1AH.Register 3 | |
| OCR1AH.A 2 | |
| OCR1AH.High 1 | |
| OCR1AH.Byte 0 | |
| OCR1AL 0x0068 | |
| OCR1AL.Timer_Counter1 7 | |
| OCR1AL.Output 5 | |
| OCR1AL.Compare 4 | |
| OCR1AL.Register 3 | |
| OCR1AL.A 2 | |
| OCR1AL.Low 1 | |
| OCR1AL.Byte 0 | |
| ICR1H 0x0067 | |
| ICR1H.Timer_Counter1 7 | |
| ICR1H.Input 5 | |
| ICR1H.Capture 4 | |
| ICR1H.Register 3 | |
| ICR1H.High 2 | |
| ICR1H.Byte 1 | |
| ICR1H.136 0 | |
| ICR1L 0x0066 | |
| ICR1L.Timer_Counter1 7 | |
| ICR1L.Input 5 | |
| ICR1L.Capture 4 | |
| ICR1L.Register 3 | |
| ICR1L.Low 2 | |
| ICR1L.Byte 1 | |
| ICR1L.136 0 | |
| TCNT1H 0x0065 | |
| TCNT1L 0x0064 | |
| TCCR1C 0x0062 | |
| TCCR1C.FOC1A 7 | |
| TCCR1C.FOC1B 6 | |
| TCCR1B 0x0061 | |
| TCCR1B.ICNC1 7 | |
| TCCR1B.ICES1 6 | |
| TCCR1B.WGM13 4 | |
| TCCR1B.WGM12 3 | |
| TCCR1B.CS12 2 | |
| TCCR1B.CS11 1 | |
| TCCR1B.CS10 0 | |
| TCCR1A 0x0060 | |
| TCCR1A.COM1A1 7 | |
| TCCR1A.COM1A0 6 | |
| TCCR1A.COM1B1 5 | |
| TCCR1A.COM1B0 4 | |
| TCCR1A.WGM11 1 | |
| TCCR1A.WGM10 0 |
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