uet_ip.log

[run_tests] run tmpdir: /tmp/platform-test_o9i2b65l
[run_tests] cpus=24  sem limits: SEMMSL=32000 SEMMNS=1024000000 SEMOPM=500 SEMMNI=32000
PYTHONPATH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test:/home/dsebastian/workspace/aif/platform-test/prebuilt:/home/dsebastian/workspace/aif/platform-test:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/python:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/paris-driver/src/Common/testlib:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/aswitch:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/bm_runtime:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/targets/a1na_switch:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/tools
LD_LIBRARY_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/lib
A1_PLATFORM=fpga
A1_SYS_SW_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw
A1NA_SWITCH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/build-p4p/targets/a1na_switch/a1na_switch
ASAN_OPTIONS=verify_asan_link_order=0:detect_leaks=0:intercept_throw=0
CRYPTOGRAPHY_OPENSSL_NO_LEGACY=1
VEPY_REMOTE=0
VEPY_HOST=
VEPY_DOMAIN=0
VEPY_PCAP_PATH=/tmp/vepy_rx.pcap
VEPY_RELAY=0
VEPY_RELAY_HOST=
VEPY_RELAY_PORT=9876
A1_VEPY=0
A1_VEPY_REMOTE=0
[uet_ip.py] [devicelib] PRISM_SHM_ROOT=/tmp/platform-test_o9i2b65l/uet_ip.py/prism pid=1764453
[uet_ip.py] 
[uet_ip.py] --- SDK version ---
[uet_ip.py]   {"a1-silicon": "sw-emu-special-2026-0703-a2pp-2026-0629", "p4-programs-build": "a2pp-2026-0629", "platform": "fpga"}
[uet_ip.py] 
[uet_ip.py] 
[uet_ip.py] --- Kernel module setup ---
[uet_ip.py]   Found FPGA at 0000:21:00.0
[uet_ip.py]   Loading /home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/build/paris-driver/src/KernelModule/paris_dev.ko ...
[uet_ip.py]   0000:21:00.0 already bound
[uet_ip.py]   /dev/paris_main ready
[uet_ip.py] 
[uet_ip.py] --- Creating HwPcie + Ham ---
[uet_ip.py]   HwPcie + Ham created (BAR size=0x8000000)
[uet_ip.py] [loadILDmaOffsets] cppyy.cppdef() succeeded
[uet_ip.py] [loadILDmaOffsets] Successfully loaded 47 values
[uet_ip.py] [loadILDmaOffsets] Result keys: ['FREE_MEM_START_LO', 'FREE_MEM_START_LO_CHn', 'FREE_MEM_START_HI', 'FREE_MEM_START_HI_CHn', 'FREE_MEM_END_LO']...
[uet_ip.py] [loadILDmaOffsets] FREE_MEM_WR_PTR_CHn: len=12
[uet_ip.py] 
[uet_ip.py] --- FPGA version ---
[uet_ip.py]   {"PROJECT": "hello_pp-vpk180", "ARISTA_FDK_VERSION": "3.1.1", "BUILD_VERSION": "6.6", "PP_VERSION": "C41", "PP_FILENAME": "a2pp-2026-0629/ppu_top-0711a.svm", "AIFABRICS_HASH": "9b52b5aa12ea75219df39fe789b241c993428369", "FPGAEMU_HASH": "8e89189a793cd2c1311ed5c8fa458b6ecfa71053", "TIMESTAMP": "2026-07-24 05:18:16 UTC"}
[uet_ip.py]   WARNING: FPGA/SDK p4-programs-build version mismatch -- may not work as intended
[uet_ip.py]     FPGA PP_VERSION:      C41
[uet_ip.py]     SDK p4-programs-build: a2pp-2026-0629
[uet_ip.py] 
[uet_ip.py] --- ILDMA channel reset ---
[uet_ip.py]   chan=0 ctrl=0x00000001  intr=0x00000000  fsm=0x00000000
[uet_ip.py]   chan=1 ctrl=0x00000001  intr=0x00000000  fsm=0x00000000
[uet_ip.py] ### mgid 131 device 0 rids [[0, [2, 3, 4], (0, 0, 1)]]
[uet_ip.py] ### mgid 232 device 0 rids [[0, [1, 2, 5], (0, 0, 1)]]
[uet_ip.py] pvs_add completed
[uet_ip.py] ### mgid 42 device 0 rids [[0, [1, 2], (0, 0, 1)]]
[uet_ip.py] pvs_add SwitchIngressParser.pvs_uet_ipv4_proto 99 UNSUPPORTED
[uet_ip.py] Traceback (most recent call last):
[uet_ip.py]   File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/uet_ip.py", line 48, in <module>
[uet_ip.py]     UetOverIpv4Test().run()
[uet_ip.py]   File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/uet_testlib.py", line 78, in run
[uet_ip.py]     self.forwardingSetup()
[uet_ip.py]   File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/uet_ip.py", line 25, in forwardingSetup
[uet_ip.py]     out = self.cli( 'pvs_add SwitchIngressParser.pvs_uet_ipv4_proto ' +
[uet_ip.py]           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[uet_ip.py]   File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/p4testlib.py", line 400, in cli
[uet_ip.py]     out = self.devices[ dev ].cli( cmd, echo=echo )
[uet_ip.py]           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[uet_ip.py]   File "/home/dsebastian/workspace/aif/platform-test/platformlib/fpga_platform.py", line 466, in cli
[uet_ip.py]     raise NotImplementedError( "FPGA does not support CLI" )
[uet_ip.py] NotImplementedError: FPGA does not support CLI
[uet_ip.py]   WARNING: rmmod failed: rmmod: ERROR: Module paris_dev is in use
[uet_ip.py] Completed in 0m19.7s

============================================================
FAILED:
  uet_ip.py
Results: 1 test(s) — 0 passed, 0 vdiff, 1 failed
============================================================