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July 11, 2026 04:45
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| Test: csig_l3unicast_route_encap_vxlan | |
| Date: Fri Jul 10 10:49:37 AM UTC 2026 | |
| FPGA_VERSION: 106.1 | |
| Bit: /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi | |
| ======================================== | |
| === FPGA PROGRAMMING (version 106.1) | |
| ======================================== | |
| # ------------------------------------------------------------------------------ | |
| # Maggie testing application | |
| # - FPGA Programming In Progress : /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi | |
| # - FPGA Programming Complete | |
| # - IIC : Port opened on ftdi://ftdi:4232:P1ABSDE36/2 to DEVICEID 0x58 at 1000.0kHz | |
| # - PCIE : Port opened on 0000:21:00.0 | |
| # - QSPI : Detected Micron manufacturer ID: 0x20 Device ID: 0xbb21 | |
| # - UART : Port opened on ftdi://ftdi:4232:P1ABSDE36/3 at 115200 baud | |
| FPGA programmed OK (79s) | |
| ======================================== | |
| === TEST RUN | |
| ======================================== | |
| [run_tests] run tmpdir: /tmp/platform-test_ad7zdgb0 | |
| [run_tests] cpus=24 sem limits: SEMMSL=32000 SEMMNS=1024000000 SEMOPM=500 SEMMNI=32000 | |
| PYTHONPATH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test:/home/dsebastian/workspace/aif/platform-test/prebuilt:/home/dsebastian/workspace/aif/platform-test:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/python:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/paris-driver/src/Common/testlib:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/aswitch:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/bm_runtime:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/targets/a1na_switch:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/tools | |
| LD_LIBRARY_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/lib | |
| A1_PLATFORM=fpga | |
| A1_SYS_SW_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw | |
| A1NA_SWITCH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/build-p4p/targets/a1na_switch/a1na_switch | |
| ASAN_OPTIONS=verify_asan_link_order=0:detect_leaks=0:intercept_throw=0 | |
| CRYPTOGRAPHY_OPENSSL_NO_LEGACY=1 | |
| [csig_l3unicast_route_encap_vxlan.py] [devicelib] PRISM_SHM_ROOT=/tmp/platform-test_ad7zdgb0/csig_l3unicast_route_encap_vxlan.py/prism pid=1075781 | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] --- SDK version --- | |
| [csig_l3unicast_route_encap_vxlan.py] {"a1-silicon": "a1_main_regr_07_03_26_v1", "p4-programs-build": "a2pp-2026-0619", "platform": "fpga"} | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] --- Kernel module setup --- | |
| [csig_l3unicast_route_encap_vxlan.py] Found FPGA at 0000:21:00.0 | |
| [csig_l3unicast_route_encap_vxlan.py] Loading /home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/build/paris-driver/src/KernelModule/paris_dev.ko ... | |
| [csig_l3unicast_route_encap_vxlan.py] 0000:21:00.0 already bound | |
| [csig_l3unicast_route_encap_vxlan.py] /dev/paris_main ready | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] --- Creating HwPcie + Ham --- | |
| [csig_l3unicast_route_encap_vxlan.py] HwPcie + Ham created (BAR size=0x8000000) | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] --- FPGA version --- | |
| [csig_l3unicast_route_encap_vxlan.py] {"PROJECT": "hello_pp-vpk180", "ARISTA_FDK_VERSION": "3.1.1", "BUILD_VERSION": "106.1", "PP_VERSION": "C41", "PP_FILENAME": "a2pp-2026-0629/ppu_top-0702a.svm", "AIFABRICS_HASH": "c940ed75122742f487e56fbabba6efdf8761432b", "FPGAEMU_HASH": "dfed8809adc05913c2e66fd2ca18176aa840b1bb", "TIMESTAMP": "2026-07-10 01:50:04 UTC"} | |
| [csig_l3unicast_route_encap_vxlan.py] WARNING: FPGA/SDK p4-programs-build version mismatch -- may not work as intended | |
| [csig_l3unicast_route_encap_vxlan.py] FPGA PP_VERSION: C41 | |
| [csig_l3unicast_route_encap_vxlan.py] SDK p4-programs-build: a2pp-2026-0619 | |
| [csig_l3unicast_route_encap_vxlan.py] | |
| [csig_l3unicast_route_encap_vxlan.py] --- ILDMA channel reset --- | |
| [csig_l3unicast_route_encap_vxlan.py] ctrl=0x00000001 intr=0x00000000 fsm=0x00000000 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902 | |
| [csig_l3unicast_route_encap_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902 | |
| [csig_l3unicast_route_encap_vxlan.py] ### mgid 132 device 0 rids [[0, [2, 3], (0, 0, 1)]] | |
| [csig_l3unicast_route_encap_vxlan.py] ### mgid 133 device 0 rids [[0, [1], (0, 0, 1)]] | |
| [csig_l3unicast_route_encap_vxlan.py] ### mgid 232 device 0 rids [[0, [4], (0, 0, 1)]] | |
| [csig_l3unicast_route_encap_vxlan.py] Sent forwardCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:24.882] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=0 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=224 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 3A 32 C0 0C 80 00 00 00 1C 15 00 00 00 00 ..:2............ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 00 00 00 00 4C D9 80 00 ............L... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 CC D9 0C D9 4C D8 8C D8 0C CE 4C D8 8C CD CC CE ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 0C CD 4C CD 8C CC CC CD 0C CC 4C CC 4C 99 8C CC ..L.......L.L... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 CC 99 0C 99 4C 98 8C 98 0C 8E 4C 98 8C 8D CC 8E ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 0C 8D 4C 8D 8C 8C CC 8D 0C 8C 4C 8C 4C 59 8C 8C ..L.......L.LY.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 CC 59 0C 59 4C 58 8C 58 0C 4E 4C 58 8C 4D CC 4E .Y.YLX.X.NLX.M.N | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 0C 4D 4C 4D 8C 4C CC 4D 0C 4C 4C 4C 4C 19 8C 4C .MLM.L.M.LLLL..L | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 CC 19 0C 19 4C 18 8C 18 0C 0E 4C 18 8C 0D CC 0E ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 0C 0D 4C 0D 8C 0C CC 0D 0C 0C 4C 0C 80 C1 0C 0C ..L.......L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 40 40 42 80 1A ED 40 40 40 00 0F C0 40 25 00 00 @@B...@@@...@%.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 82 00 11 6B A6 1D 95 0C D1 15 77 2E 40 04 48 8C ...k......w.@.H. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 00 09 C4 01 02 00 00 00 40 2C 80 00 6A 90 04 AD ........@,..j... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 02 01 C1 81 80 40 80 C1 10 04 4A 05 80 00 10 00 .....@....J..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 11 40 00 31 40 00 02 00 00 19 42 40 95 0C A0 40 .@.1@.....B@...@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=170 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=1 csigwide=0 csig_type=1 csig_wf=0 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=174 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 21 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 174 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] Sent stripCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:24.927] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=220 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 36 2E C0 0B 80 00 00 00 1B 95 00 00 00 00 ..6............. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 4C D9 80 00 CC D9 0C D9 4C D8 8C D8 0C CE 4C D8 L.......L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 8C CD CC CE 0C CD 4C CD 8C CC CC CD 0C CC 4C CC ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 4C 99 8C CC CC 99 0C 99 4C 98 8C 98 0C 8E 4C 98 L.......L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 8C 8D CC 8E 0C 8D 4C 8D 8C 8C CC 8D 0C 8C 4C 8C ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 4C 59 8C 8C CC 59 0C 59 4C 58 8C 58 0C 4E 4C 58 LY...Y.YLX.X.NLX | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 8C 4D CC 4E 0C 4D 4C 4D 8C 4C CC 4D 0C 4C 4C 4C .M.N.MLM.L.M.LLL | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 4C 19 8C 4C CC 19 0C 19 4C 18 8C 18 0C 0E 4C 18 L..L....L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 8C 0D CC 0E 0C 0D 4C 0D 8C 0C CC 0D 0C 0C 4C 0C ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 80 C1 0C 0C 40 40 42 80 1A ED 40 40 40 00 0F C0 ....@@B...@@@... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 40 25 00 00 82 00 11 6B A6 1D 95 0C D1 15 77 2E @%.....k......w. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 40 04 48 8C 00 09 C4 01 02 00 00 00 40 2C 80 00 @.H.........@,.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 6A 90 04 AD 02 01 C1 81 80 40 80 C1 10 04 4A 05 j........@....J. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 80 00 10 00 11 40 00 31 00 19 42 00 95 0C A0 40 .....@.1..B....@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=170 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=1 csigwide=0 csig_type=1 csig_wf=0 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=174 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 21 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 174 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] Sent encapCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:25.258] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=224 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 3A 32 C0 0C 80 00 00 00 1C 15 00 00 00 00 ..:2............ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 00 00 00 00 4C D9 80 00 ............L... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 CC D9 0C D9 4C D8 8C D8 0C CE 4C D8 8C CD CC CE ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 0C CD 4C CD 8C CC CC CD 0C CC 4C CC 4C 99 8C CC ..L.......L.L... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 CC 99 0C 99 4C 98 8C 98 0C 8E 4C 98 8C 8D CC 8E ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 0C 8D 4C 8D 8C 8C CC 8D 0C 8C 4C 8C 4C 59 8C 8C ..L.......L.LY.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 CC 59 0C 59 4C 58 8C 58 0C 4E 4C 58 8C 4D CC 4E .Y.YLX.X.NLX.M.N | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 0C 4D 4C 4D 8C 4C CC 4D 0C 4C 4C 4C 4C 19 8C 4C .MLM.L.M.LLLL..L | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 CC 19 0C 19 4C 18 8C 18 0C 0E 4C 18 8C 0D CC 0E ....L.....L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 0C 0D 4C 0D 8C 0C CC 0D 0C 0C 4C 0C 80 C1 0C 0C ..L.......L..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 40 40 42 80 1A ED 40 40 40 00 0F C0 40 25 00 00 @@B...@@@...@%.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 02 00 11 6B 82 40 40 00 A6 1D 95 0C D1 15 77 2E ...k.@@.......w. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 40 04 48 8C 00 09 C4 01 02 00 00 00 40 2D 80 00 @.H.........@-.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 6A 90 04 AD 02 01 C1 81 80 40 80 C1 10 04 4A 04 j........@....J. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 80 00 10 00 11 40 00 32 00 19 42 00 95 0C A0 40 .....@.2..B....@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=170 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=1 csigwide=0 csig_type=1 csig_wf=0 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=174 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 21 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 174 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] Sent forwardCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:25.590] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=228 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 3A 32 40 0C 80 00 00 00 1C 96 00 00 00 00 ..:2@........... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 4C D9 80 00 CC D9 0C D9 ........L....... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 4C D8 8C D8 0C CE 4C D8 8C CD CC CE 0C CD 4C CD L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 8C CC CC CD 0C CC 4C CC 4C 99 8C CC CC 99 0C 99 ......L.L....... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 4C 98 8C 98 0C 8E 4C 98 8C 8D CC 8E 0C 8D 4C 8D L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 8C 8C CC 8D 0C 8C 4C 8C 4C 59 8C 8C CC 59 0C 59 ......L.LY...Y.Y | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 4C 58 8C 58 0C 4E 4C 58 8C 4D CC 4E 0C 4D 4C 4D LX.X.NLX.M.N.MLM | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 8C 4C CC 4D 0C 4C 4C 4C 4C 19 8C 4C CC 19 0C 19 .L.M.LLLL..L.... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 4C 18 8C 18 0C 0E 4C 18 8C 0D CC 0E 0C 0D 4C 0D L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 8C 0C CC 0D 0C 0C 4C 0C 80 C1 0C 0C 40 40 42 80 ......L.....@@B. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 1A ED 40 40 40 00 0F C0 40 25 00 00 82 00 11 6B ..@@@...@%.....k | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 A6 1D 95 0C D1 15 77 2E 40 04 48 8C 00 09 C4 01 ......w.@.H..... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 02 00 00 00 40 2C 80 00 6A 90 04 AD 02 01 C1 81 ....@,..j....... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 80 40 80 C1 10 04 4A 05 80 00 10 00 11 40 00 31 .@....J......@.1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 00 00 02 00 80 00 00 00 00 19 42 40 95 0C A0 40 ..........B@...@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=174 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=0 csigwide=1 csig_type=1 csig_wf=1 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=178 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 23 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 178 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] Sent stripCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:25.606] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=220 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 32 2A 40 0A 80 00 00 00 1B 96 00 00 00 00 ..2*@........... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 4C D9 80 00 CC D9 0C D9 4C D8 8C D8 0C CE 4C D8 L.......L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 8C CD CC CE 0C CD 4C CD 8C CC CC CD 0C CC 4C CC ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 4C 99 8C CC CC 99 0C 99 4C 98 8C 98 0C 8E 4C 98 L.......L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 8C 8D CC 8E 0C 8D 4C 8D 8C 8C CC 8D 0C 8C 4C 8C ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 4C 59 8C 8C CC 59 0C 59 4C 58 8C 58 0C 4E 4C 58 LY...Y.YLX.X.NLX | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 8C 4D CC 4E 0C 4D 4C 4D 8C 4C CC 4D 0C 4C 4C 4C .M.N.MLM.L.M.LLL | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 4C 19 8C 4C CC 19 0C 19 4C 18 8C 18 0C 0E 4C 18 L..L....L.....L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 8C 0D CC 0E 0C 0D 4C 0D 8C 0C CC 0D 0C 0C 4C 0C ......L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 80 C1 0C 0C 40 40 42 80 1A ED 40 40 40 00 0F C0 ....@@B...@@@... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 40 25 00 00 82 00 11 6B A6 1D 95 0C D1 15 77 2E @%.....k......w. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 40 04 48 8C 00 09 C4 01 02 00 00 00 40 2C 80 00 @.H.........@,.. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 6A 90 04 AD 02 01 C1 81 80 40 80 C1 10 04 4A 05 j........@....J. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 80 00 10 00 11 40 00 31 00 19 42 00 95 0C A0 40 .....@.1..B....@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=174 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=0 csigwide=1 csig_type=1 csig_wf=1 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=178 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 23 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 178 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] Sent encapCsig | |
| [csig_l3unicast_route_encap_vxlan.py] [03:52:25.927] dev:0 port:2 sending packet | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] pre-send emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] counts: emrg=1 mirr=0 bcnt=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0]: portId=1 err=0 discard=0 new_len=228 bcntBytes=0 bcntPort=0 bcntErr=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0000 00 00 3A 32 40 0C 80 00 00 00 1C 96 00 00 00 00 ..:2@........... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0040 00 00 00 00 00 00 00 00 4C D9 80 00 CC D9 0C D9 ........L....... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0050 4C D8 8C D8 0C CE 4C D8 8C CD CC CE 0C CD 4C CD L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0060 8C CC CC CD 0C CC 4C CC 4C 99 8C CC CC 99 0C 99 ......L.L....... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0070 4C 98 8C 98 0C 8E 4C 98 8C 8D CC 8E 0C 8D 4C 8D L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0080 8C 8C CC 8D 0C 8C 4C 8C 4C 59 8C 8C CC 59 0C 59 ......L.LY...Y.Y | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0090 4C 58 8C 58 0C 4E 4C 58 8C 4D CC 4E 0C 4D 4C 4D LX.X.NLX.M.N.MLM | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00a0 8C 4C CC 4D 0C 4C 4C 4C 4C 19 8C 4C CC 19 0C 19 .L.M.LLLL..L.... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00b0 4C 18 8C 18 0C 0E 4C 18 8C 0D CC 0E 0C 0D 4C 0D L.....L.......L. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00c0 8C 0C CC 0D 0C 0C 4C 0C 80 C1 0C 0C 40 40 42 80 ......L.....@@B. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00d0 1A ED 40 40 40 00 0F C0 40 25 00 00 02 00 11 6B ..@@@...@%.....k | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00e0 00 00 00 00 82 40 80 00 A6 1D 95 0C D1 15 77 2E .....@........w. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 00f0 40 04 48 8C 00 09 C4 01 02 00 00 00 40 2E 80 00 @.H.........@... | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0100 6A 90 04 AD 02 01 C1 81 80 40 80 C1 10 04 4A 03 j........@....J. | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0110 80 00 10 00 11 40 00 33 00 19 42 00 95 0C A0 40 .....@.3..B....@ | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] emrg[0] raw 0120 37 2E A6 1D AB 6F BB C0 00 01 00 37 7....o.....7 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0]: port=1 bcnt=174 eop=1 err=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea: inport=2 dmac=00:11:22:33:44:55 l2dom=200 routed=1 nh=0x0064 vlan0=1 vlan1=0 ip4=0 ip6=0 l4proto=0 srcport=0 dstport=0 csigcmp=0 csigwide=1 csig_type=1 csig_wf=1 csig_inv=0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm: eport=1 pkt_len=178 c2cpu=0 mirror=0 repl_id=0x0000 pipe_qid=0 sch_tag=0x000 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingress_timestamp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressport: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea decaplen: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_cpureasoncode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_decaptype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_dmac: '00:11:22:33:44:55' | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_egrl2domain: 200 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_encaptype: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_ingressporttype: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_routed: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea hashmd_lag: 43484 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea icos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmd_ingl2domain: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea phase0_switchport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cfi: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_cos: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_exp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_ecn: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea qosmd_dscp: 43 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnelidx: 5 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea tunnell2idx: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6dipshift: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6blocksize: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatedipfromsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6updatesrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea srv6popsrh: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdsrcport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmddstport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdprotocol: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingmdl4attr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie0: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea iecookie1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ingl2aintf: 4096 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrl2aintf: 2048 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea nh: 100 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_type: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_wide_format: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea csig_invalid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ect: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea trimmable: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea localtrimming: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea earlyqdiscardeligible: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea l1_prun_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea egrmd_mplsttlmode: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ptp: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flowlet_disabled: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea mirrormgid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_outer_toomanyhdr: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan0: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_vlan1: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigwide: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_csigcompact: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_mpls: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip4: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_ip6: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea flag_ip_udp_vxlan: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] ia2ea ip_udp_payload_offset: 23 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eop: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c0_eport: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm spdd_trace_tag: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm bts: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm csig_val: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm src_port: 2 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm eport: 1 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ce: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm ct: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm c2cpu: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm mirror: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm dod: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_copy: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm repl_id_first: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pipe_qid: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm pkt_length: 178 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm trimmed: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] [pktgen] mhe[0] tm sch_tag_id: 0 | |
| [csig_l3unicast_route_encap_vxlan.py] WARNING: rmmod failed: rmmod: ERROR: Module paris_dev is in use | |
| [csig_l3unicast_route_encap_vxlan.py] ╭──────────────────────────────── Shadow Validation ────────────────────────────────╮ | |
| [csig_l3unicast_route_encap_vxlan.py] │ validate: 9206/9206 PASS 0 MISMATCH 0 ERR │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ (log: /tmp/platform-test_ad7zdgb0/csig_l3unicast_route_encap_vxlan.py/shadow… │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ Table rows PASS FAIL ERR │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ cpuAndMirrorPacketEncap 8 8 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ cpuReasonCodeToCpuQidIcos 26 26 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ csigIngressExtract 30 30 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ csigNormalizeValues 30 30 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ csigPortCheck 1 1 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ecmpFixup 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ecmpHashMixEnable 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ecmpHashSelection 66 66 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ egrChipModeSel 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ egrVlanCheck 8 8 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ egressIntfMac 4 4 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ egressPortDropCheck 31 31 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ encapDecap 160 160 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ eosIntfToPhysical 24 24 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ fabricLagAttr 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ finalDropControl 95 95 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ingChipModeSel 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ingVlanCheck 2180 2180 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ingressPortDropCheck 21 21 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ ipv4Lpm 8 8 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ l2DmacCompress 10 10 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ l2DomainLookup 28 28 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ l3DmacCheck 14 14 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ lagHashMixEnable 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ lagHashSelection 66 66 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ mdgRemap 10 10 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ mplsLookup 4 4 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ nextHop 12 12 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ nextHopOverlay 4 4 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ normalizeDscp 5 5 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ systemAcl 995 995 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ taggedPktToL3 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tcModeSelect 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelActionData 4 4 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelAttr 4097 4097 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelDipV4 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelL2IdxToPort 1025 1025 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelL2Info 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ tunnelVniAndVti 4 4 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ untaggedPktToL3 2 2 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ vlanEncap 6 6 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ wredAction 208 208 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ TOTAL 9206 9206 0 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] ╰───────────────────────────────────────────────────────────────────────────────────╯ | |
| [csig_l3unicast_route_encap_vxlan.py] ╭──────────────────────────── Paris SDK Ops Statistics ─────────────────────────────╮ | |
| [csig_l3unicast_route_encap_vxlan.py] │ Paris SDK Ops 225 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ Passed 225 │ | |
| [csig_l3unicast_route_encap_vxlan.py] │ Failed 0 │ | |
| [csig_l3unicast_route_encap_vxlan.py] ╰───────────────────────────────────────────────────────────────────────────────────╯ | |
| [csig_l3unicast_route_encap_vxlan.py] Completed in 1m47.5s | |
| ============================================================ | |
| PASSED: | |
| csig_l3unicast_route_encap_vxlan.py | |
| Results: 1 test(s) — 1 passed, 0 failed | |
| ============================================================ | |
| RESULT: PASS (107s) |
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