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dsebastian-arista/clb_v6_switch_to_v6_vxlan.run.2026-07-10.txt

Created July 11, 2026 04:45
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clb_v6_switch_to_v6_vxlan.run.2026-07-10.txt
Test: clb_v6_switch_to_v6_vxlan
Date: Fri Jul 10 10:10:21 AM UTC 2026
FPGA_VERSION: 106.1
Bit: /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi
========================================
=== FPGA PROGRAMMING (version 106.1)
========================================
# ------------------------------------------------------------------------------
# Maggie testing application
# - FPGA Programming In Progress : /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi
# - FPGA Programming Complete
# - IIC : Port opened on ftdi://ftdi:4232:P1ABSDE36/2 to DEVICEID 0x58 at 1000.0kHz
# - PCIE : Port opened on 0000:21:00.0
# - QSPI : Detected Micron manufacturer ID: 0x20 Device ID: 0xbb21
# - UART : Port opened on ftdi://ftdi:4232:P1ABSDE36/3 at 115200 baud
FPGA programmed OK (78s)
========================================
=== TEST RUN
========================================
[run_tests] run tmpdir: /tmp/platform-test_30e21dat
[run_tests] cpus=24 sem limits: SEMMSL=32000 SEMMNS=1024000000 SEMOPM=500 SEMMNI=32000
PYTHONPATH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test:/home/dsebastian/workspace/aif/platform-test/prebuilt:/home/dsebastian/workspace/aif/platform-test:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/python:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/paris-driver/src/Common/testlib:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/aswitch:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/bm_runtime:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/targets/a1na_switch:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/tools
LD_LIBRARY_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/lib
A1_PLATFORM=fpga
A1_SYS_SW_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw
A1NA_SWITCH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/build-p4p/targets/a1na_switch/a1na_switch
ASAN_OPTIONS=verify_asan_link_order=0:detect_leaks=0:intercept_throw=0
CRYPTOGRAPHY_OPENSSL_NO_LEGACY=1
[clb_v6_switch_to_v6_vxlan.py] [devicelib] PRISM_SHM_ROOT=/tmp/platform-test_30e21dat/clb_v6_switch_to_v6_vxlan.py/prism pid=1063856
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py] --- SDK version ---
[clb_v6_switch_to_v6_vxlan.py] {"a1-silicon": "a1_main_regr_07_03_26_v1", "p4-programs-build": "a2pp-2026-0619", "platform": "fpga"}
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py] --- Kernel module setup ---
[clb_v6_switch_to_v6_vxlan.py] Found FPGA at 0000:21:00.0
[clb_v6_switch_to_v6_vxlan.py] Loading /home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/build/paris-driver/src/KernelModule/paris_dev.ko ...
[clb_v6_switch_to_v6_vxlan.py] 0000:21:00.0 already bound
[clb_v6_switch_to_v6_vxlan.py] /dev/paris_main ready
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py] --- Creating HwPcie + Ham ---
[clb_v6_switch_to_v6_vxlan.py] HwPcie + Ham created (BAR size=0x8000000)
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py] --- FPGA version ---
[clb_v6_switch_to_v6_vxlan.py] {"PROJECT": "hello_pp-vpk180", "ARISTA_FDK_VERSION": "3.1.1", "BUILD_VERSION": "106.1", "PP_VERSION": "C41", "PP_FILENAME": "a2pp-2026-0629/ppu_top-0702a.svm", "AIFABRICS_HASH": "c940ed75122742f487e56fbabba6efdf8761432b", "FPGAEMU_HASH": "dfed8809adc05913c2e66fd2ca18176aa840b1bb", "TIMESTAMP": "2026-07-10 01:50:04 UTC"}
[clb_v6_switch_to_v6_vxlan.py] WARNING: FPGA/SDK p4-programs-build version mismatch -- may not work as intended
[clb_v6_switch_to_v6_vxlan.py] FPGA PP_VERSION: C41
[clb_v6_switch_to_v6_vxlan.py] SDK p4-programs-build: a2pp-2026-0619
[clb_v6_switch_to_v6_vxlan.py]
[clb_v6_switch_to_v6_vxlan.py] --- ILDMA channel reset ---
[clb_v6_switch_to_v6_vxlan.py] ctrl=0x00000001 intr=0x00000000 fsm=0x00000000
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[clb_v6_switch_to_v6_vxlan.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[clb_v6_switch_to_v6_vxlan.py] ### mgid 131 device 0 rids [[0, [2], (0, 0, 1)]]
[clb_v6_switch_to_v6_vxlan.py] ### mgid 233 device 0 rids [[0, [1], (0, 0, 1)]]
[clb_v6_switch_to_v6_vxlan.py] ### mgid 235 device 0 rids [[0, [3], (0, 0, 1)]]
[clb_v6_switch_to_v6_vxlan.py] ### mgid 237 device 0 rids [[0, [5], (0, 0, 1)]]
[clb_v6_switch_to_v6_vxlan.py] ### mgid 239 device 0 rids [[0, [7], (0, 0, 1)]]
[clb_v6_switch_to_v6_vxlan.py] peek_config_set SwitchIngressParser.customExtract0 0 UNSUPPORTED
[clb_v6_switch_to_v6_vxlan.py] Traceback (most recent call last):
[clb_v6_switch_to_v6_vxlan.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/clb_v6_switch_to_v6_vxlan.py", line 12, in <module>
[clb_v6_switch_to_v6_vxlan.py] ClbSwitchV6VxlanV6Encap().run()
[clb_v6_switch_to_v6_vxlan.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/clb_v4_switch_to_vxlan.py", line 189, in run
[clb_v6_switch_to_v6_vxlan.py] self.forwardingSetup()
[clb_v6_switch_to_v6_vxlan.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/clb_v4_switch_to_vxlan.py", line 154, in forwardingSetup
[clb_v6_switch_to_v6_vxlan.py] self.cli( "peek_config_set SwitchIngressParser.customExtract0 0",
[clb_v6_switch_to_v6_vxlan.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/p4testlib.py", line 400, in cli
[clb_v6_switch_to_v6_vxlan.py] out = self.devices[ dev ].cli( cmd, echo=echo )
[clb_v6_switch_to_v6_vxlan.py] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[clb_v6_switch_to_v6_vxlan.py] File "/home/dsebastian/workspace/aif/platform-test/platformlib/fpga_platform.py", line 446, in cli
[clb_v6_switch_to_v6_vxlan.py] raise NotImplementedError( "FPGA does not support CLI" )
[clb_v6_switch_to_v6_vxlan.py] NotImplementedError: FPGA does not support CLI
[clb_v6_switch_to_v6_vxlan.py] WARNING: rmmod failed: rmmod: ERROR: Module paris_dev is in use
[clb_v6_switch_to_v6_vxlan.py] ╭──────────────────────────────── Shadow Validation ────────────────────────────────╮
[clb_v6_switch_to_v6_vxlan.py] │ validate: 9223/9223 PASS 0 MISMATCH 0 ERR │
[clb_v6_switch_to_v6_vxlan.py] │ (log: /tmp/platform-test_30e21dat/clb_v6_switch_to_v6_vxlan.py/shadow_valida… │
[clb_v6_switch_to_v6_vxlan.py] │ │
[clb_v6_switch_to_v6_vxlan.py] │ Table rows PASS FAIL ERR │
[clb_v6_switch_to_v6_vxlan.py] │ cpuAndMirrorPacketEncap 8 8 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ cpuReasonCodeToCpuQidIcos 26 26 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ csigIngressExtract 30 30 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ csigNormalizeValues 30 30 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ecmpFixup 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ecmpHashMixEnable 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ecmpHashSelection 66 66 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ egrChipModeSel 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ egrVlanCheck 10 10 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ egressIntfMac 4 4 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ egressPortDropCheck 31 31 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ encapDecap 160 160 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ eosIntfToPhysical 24 24 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ fabricLagAttr 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ finalDropControl 95 95 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ingChipModeSel 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ingVlanCheck 2181 2181 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ ingressPortDropCheck 21 21 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ l2DmacCompress 10 10 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ l2DomainLookup 28 28 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ l2Lookup 6 6 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ l3DmacCheck 14 14 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ lagHashMixEnable 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ lagHashSelection 66 66 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ lampPortVector 16 16 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ mdgRemap 14 14 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ mplsLookup 4 4 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ nextHop 8 8 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ nextHopOverlay 4 4 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ normalizeDscp 5 5 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ systemAcl 995 995 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ taggedPktToL3 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelActionData 7 7 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelAttr 4097 4097 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelDipV6 2 2 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelL2IdxToPort 1028 1028 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelL2Info 7 7 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ tunnelVniAndVti 4 4 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ wredAction 208 208 0 0 │
[clb_v6_switch_to_v6_vxlan.py] │ TOTAL 9223 9223 0 0 │
[clb_v6_switch_to_v6_vxlan.py] ╰───────────────────────────────────────────────────────────────────────────────────╯
[clb_v6_switch_to_v6_vxlan.py] ╭──────────────────────────── Paris SDK Ops Statistics ─────────────────────────────╮
[clb_v6_switch_to_v6_vxlan.py] │ Paris SDK Ops 229 │
[clb_v6_switch_to_v6_vxlan.py] │ Passed 229 │
[clb_v6_switch_to_v6_vxlan.py] │ Failed 0 │
[clb_v6_switch_to_v6_vxlan.py] ╰───────────────────────────────────────────────────────────────────────────────────╯
[clb_v6_switch_to_v6_vxlan.py] Completed in 1m49.2s
============================================================
FAILED:
clb_v6_switch_to_v6_vxlan.py
Results: 1 test(s) — 0 passed, 1 failed
============================================================
RESULT: FAIL (109s)
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