Skip to content

Instantly share code, notes, and snippets.

@dsebastian-arista

dsebastian-arista/bts_src_csig.TestBTSCsig.test_v4CsigTruncateWide.run.2026-07-10.txt

Created July 11, 2026 04:45
Show Gist options

  • Select an option

    Learn more about clone URLs
  • Save dsebastian-arista/f769199c1d9553380a7339d972ccbf29 to your computer and use it in GitHub Desktop.

Select an option

Learn more about clone URLs
Save dsebastian-arista/f769199c1d9553380a7339d972ccbf29 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
bts_src_csig.TestBTSCsig.test_v4CsigTruncateWide.run.2026-07-10.txt
Test: bts_src_csig::TestBTSCsig.test_v4CsigTruncateWide
Date: Fri Jul 10 09:49:12 AM UTC 2026
FPGA_VERSION: 106.1
Bit: /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi
========================================
=== FPGA PROGRAMMING (version 106.1)
========================================
# ------------------------------------------------------------------------------
# Maggie testing application
# - FPGA Programming In Progress : /persist2/releases/hw.pp.rel106.1/hello_pp-vpk180-rel106.1.pdi
# - FPGA Programming Complete
# - IIC : Port opened on ftdi://ftdi:4232:P1ABSDE36/2 to DEVICEID 0x58 at 1000.0kHz
# - PCIE : Port opened on 0000:21:00.0
# - QSPI : Detected Micron manufacturer ID: 0x20 Device ID: 0xbb21
# - UART : Port opened on ftdi://ftdi:4232:P1ABSDE36/3 at 115200 baud
FPGA programmed OK (78s)
========================================
=== TEST RUN
========================================
[run_tests] run tmpdir: /tmp/platform-test_x7infr03
[run_tests] cpus=24 sem limits: SEMMSL=32000 SEMMNS=1024000000 SEMOPM=500 SEMMNI=32000
PYTHONPATH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test:/home/dsebastian/workspace/aif/platform-test/prebuilt:/home/dsebastian/workspace/aif/platform-test:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/python:/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/paris-driver/src/Common/testlib:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/aswitch:/home/dsebastian/workspace/aif/platform-test/prebuilt/gen-py/bm_runtime:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/targets/a1na_switch:/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/tools
LD_LIBRARY_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/install/lib
A1_PLATFORM=fpga
A1_SYS_SW_PATH=/home/dsebastian/workspace/aif/platform-test/submodules/sys-sw
A1NA_SWITCH=/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/submodules/behavioral-model/build-p4p/targets/a1na_switch/a1na_switch
ASAN_OPTIONS=verify_asan_link_order=0:detect_leaks=0:intercept_throw=0
CRYPTOGRAPHY_OPENSSL_NO_LEGACY=1
[bts_src_csig.py] [devicelib] PRISM_SHM_ROOT=/tmp/platform-test_x7infr03/bts_src_csig.py/prism pid=1057374
[bts_src_csig.py]
[bts_src_csig.py] --- SDK version ---
[bts_src_csig.py] {"a1-silicon": "a1_main_regr_07_03_26_v1", "p4-programs-build": "a2pp-2026-0619", "platform": "fpga"}
[bts_src_csig.py]
[bts_src_csig.py]
[bts_src_csig.py] --- Kernel module setup ---
[bts_src_csig.py] Found FPGA at 0000:21:00.0
[bts_src_csig.py] Loading /home/dsebastian/workspace/aif/platform-test/submodules/sys-sw/build/paris-driver/src/KernelModule/paris_dev.ko ...
[bts_src_csig.py] 0000:21:00.0 already bound
[bts_src_csig.py] /dev/paris_main ready
[bts_src_csig.py]
[bts_src_csig.py] --- Creating HwPcie + Ham ---
[bts_src_csig.py] HwPcie + Ham created (BAR size=0x8000000)
[bts_src_csig.py]
[bts_src_csig.py] --- FPGA version ---
[bts_src_csig.py] {"PROJECT": "hello_pp-vpk180", "ARISTA_FDK_VERSION": "3.1.1", "BUILD_VERSION": "106.1", "PP_VERSION": "C41", "PP_FILENAME": "a2pp-2026-0629/ppu_top-0702a.svm", "AIFABRICS_HASH": "c940ed75122742f487e56fbabba6efdf8761432b", "FPGAEMU_HASH": "dfed8809adc05913c2e66fd2ca18176aa840b1bb", "TIMESTAMP": "2026-07-10 01:50:04 UTC"}
[bts_src_csig.py] WARNING: FPGA/SDK p4-programs-build version mismatch -- may not work as intended
[bts_src_csig.py] FPGA PP_VERSION: C41
[bts_src_csig.py] SDK p4-programs-build: a2pp-2026-0619
[bts_src_csig.py]
[bts_src_csig.py] --- ILDMA channel reset ---
[bts_src_csig.py] ctrl=0x00000001 intr=0x00000000 fsm=0x00000000
[bts_src_csig.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[bts_src_csig.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[bts_src_csig.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGCompact: set compact=0x0901 wide=0x0000 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=0 csig64=0x0000
[bts_src_csig.py] [parserValueSetAdd] SwitchIngressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[bts_src_csig.py] [parserValueSetAdd] SwitchEgressParser.tpidDecapCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[bts_src_csig.py] [parserValueSetAdd] SwitchEgressParser.tpidCSIGWide: set compact=0x0901 wide=0x0902 readback rv=0 csig32_valid=1 csig32=0x0901 csig64_valid=1 csig64=0x0902
[bts_src_csig.py] ### mgid 132 device 0 rids [[0, [1, 2, 3], (0, 0, 1)]]
[bts_src_csig.py] ### mgid 131 device 0 rids [[0, [4], (0, 0, 1)]]
[bts_src_csig.py] test_v4CsigTruncateWide (__main__.TestBTSCsig.test_v4CsigTruncateWide) ... [02:51:57.446] dev:0 port:2 sending packet
[bts_src_csig.py] [pktgen] pre-send emrg=0 mirr=0 bcnt=0
[bts_src_csig.py] [pktgen] tm_meta 0x4003818=0x00000000 0x400381c=0x00000000 0x4003820=0x00000000 0x4003824=0x00000002 0x4003814=0x00000001
[bts_src_csig.py] [pktgen] post-send ctrl=0xffffffff emrg=1 mirr=0 bcnt=0
[bts_src_csig.py] [pktgen] emrg[0]: portId=1 err=0 discard=0
[bts_src_csig.py] [pktgen] mhe[0] tm: eport=1 c2cpu=0 mirror=0 bts=0 dod=0 ce=0 ct=0 csig_val=0x00000 trimmed=0
[bts_src_csig.py] FAIL
[bts_src_csig.py]
[bts_src_csig.py] ======================================================================
[bts_src_csig.py] FAIL: test_v4CsigTruncateWide (__main__.TestBTSCsig.test_v4CsigTruncateWide)
[bts_src_csig.py] ----------------------------------------------------------------------
[bts_src_csig.py] Traceback (most recent call last):
[bts_src_csig.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/p4testlib.py", line 521, in verifyPkts
[bts_src_csig.py] pkts = self.ports[ port ].expectTx( timeout=timeout )
[bts_src_csig.py] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[bts_src_csig.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/platformlib/port_base.py", line 156, in expectTx
[bts_src_csig.py] waitFor( self._hasPackets, timeout=timeout )
[bts_src_csig.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/testutils.py", line 51, in waitFor
[bts_src_csig.py] raise TimeoutError( excMsg )
[bts_src_csig.py] TimeoutError: timed out
[bts_src_csig.py]
[bts_src_csig.py] During handling of the above exception, another exception occurred:
[bts_src_csig.py]
[bts_src_csig.py] Traceback (most recent call last):
[bts_src_csig.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/bts_src_csig.py", line 76, in test_v4CsigTruncateWide
[bts_src_csig.py] self.a1.verifyPkts( self.a1.srcPort,
[bts_src_csig.py] File "/home/dsebastian/workspace/aif/platform-test/submodules/p4-programs/test/p4testlib.py", line 523, in verifyPkts
[bts_src_csig.py] raise AssertionError( assertMsg
[bts_src_csig.py] AssertionError: Expected packets on port 2 but timed out
[bts_src_csig.py]
[bts_src_csig.py] ----------------------------------------------------------------------
[bts_src_csig.py] Ran 1 test in 96.386s
[bts_src_csig.py]
[bts_src_csig.py] FAILED (failures=1)
[bts_src_csig.py] WARNING: rmmod failed: rmmod: ERROR: Module paris_dev is in use
[bts_src_csig.py] ╭──────────────────────────────── Shadow Validation ────────────────────────────────╮
[bts_src_csig.py] │ validate: 4065/4065 PASS 0 MISMATCH 0 ERR │
[bts_src_csig.py] │ (log: /tmp/platform-test_x7infr03/bts_src_csig.py/shadow_validation.txt) │
[bts_src_csig.py] │ │
[bts_src_csig.py] │ Table rows PASS FAIL ERR │
[bts_src_csig.py] │ cpuAndMirrorPacketEncap 8 8 0 0 │
[bts_src_csig.py] │ cpuReasonCodeToCpuQidIcos 26 26 0 0 │
[bts_src_csig.py] │ csigIngressExtract 30 30 0 0 │
[bts_src_csig.py] │ csigNormalizeValues 30 30 0 0 │
[bts_src_csig.py] │ dodCsigCompact 2 2 0 0 │
[bts_src_csig.py] │ dodCsigOverride 2 2 0 0 │
[bts_src_csig.py] │ dodCsigWide 2 2 0 0 │
[bts_src_csig.py] │ dodQosFromDscp 2 2 0 0 │
[bts_src_csig.py] │ ecmpFixup 2 2 0 0 │
[bts_src_csig.py] │ ecmpHashMixEnable 2 2 0 0 │
[bts_src_csig.py] │ ecmpHashSelection 66 66 0 0 │
[bts_src_csig.py] │ egrChipModeSel 2 2 0 0 │
[bts_src_csig.py] │ egrVlanCheck 8 8 0 0 │
[bts_src_csig.py] │ egressIntfMac 4 4 0 0 │
[bts_src_csig.py] │ egressPortDropCheck 31 31 0 0 │
[bts_src_csig.py] │ encapDecap 160 160 0 0 │
[bts_src_csig.py] │ eosIntfToPhysical 24 24 0 0 │
[bts_src_csig.py] │ fabricLagAttr 2 2 0 0 │
[bts_src_csig.py] │ finalDropControl 95 95 0 0 │
[bts_src_csig.py] │ ingChipModeSel 2 2 0 0 │
[bts_src_csig.py] │ ingVlanCheck 2180 2180 0 0 │
[bts_src_csig.py] │ ingressPortDropCheck 21 21 0 0 │
[bts_src_csig.py] │ ingressTrafficClass 6 6 0 0 │
[bts_src_csig.py] │ l2DmacCompress 10 10 0 0 │
[bts_src_csig.py] │ l2DomainLookup 28 28 0 0 │
[bts_src_csig.py] │ l2Lookup 6 6 0 0 │
[bts_src_csig.py] │ l3DmacCheck 14 14 0 0 │
[bts_src_csig.py] │ lagHashMixEnable 2 2 0 0 │
[bts_src_csig.py] │ lagHashSelection 66 66 0 0 │
[bts_src_csig.py] │ mdgRemap 6 6 0 0 │
[bts_src_csig.py] │ mplsLookup 4 4 0 0 │
[bts_src_csig.py] │ nextHop 4 4 0 0 │
[bts_src_csig.py] │ normalizeDscp 5 5 0 0 │
[bts_src_csig.py] │ systemAcl 995 995 0 0 │
[bts_src_csig.py] │ taggedPktToL3 2 2 0 0 │
[bts_src_csig.py] │ taggedXlatePktToL3 2 2 0 0 │
[bts_src_csig.py] │ vlanEncap 6 6 0 0 │
[bts_src_csig.py] │ wredAction 208 208 0 0 │
[bts_src_csig.py] │ TOTAL 4065 4065 0 0 │
[bts_src_csig.py] ╰───────────────────────────────────────────────────────────────────────────────────╯
[bts_src_csig.py] ╭──────────────────────────── Paris SDK Ops Statistics ─────────────────────────────╮
[bts_src_csig.py] │ Paris SDK Ops 214 │
[bts_src_csig.py] │ Passed 214 │
[bts_src_csig.py] │ Failed 0 │
[bts_src_csig.py] ╰───────────────────────────────────────────────────────────────────────────────────╯
[bts_src_csig.py] Completed in 1m43.7s
============================================================
FAILED:
bts_src_csig.py
Results: 1 test(s) — 0 passed, 1 failed
============================================================
RESULT: FAIL (104s)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment