msrs.c

#include <stdio.h>

#define HV_X64_MSR_CRASH_CTL      0x40000105

#define MAX_MCG_BANKS 32 /* The limit in the Linux kernel */
#define MCE_BANKS_DEF   10 /* The default */
#define MCG_BANKS MAX_MCG_BANKS

/* Macros copied from other files: */
#define MAX_FIXED_COUNTERS 3

#define MSR_P6_EVNTSEL0                 0x186

#define MSR_IA32_PERF_STATUS            0x198

#define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)

#define HV_X64_MSR_CRASH_P0     0x40000100
#define HV_X64_MSR_CRASH_P1     0x40000101
#define HV_X64_MSR_CRASH_P2     0x40000102
#define HV_X64_MSR_CRASH_P3     0x40000103
#define HV_X64_MSR_CRASH_P4     0x40000104
#define HV_X64_MSR_CRASH_CTL      0x40000105
#define HV_X64_MSR_CRASH_CTL_NOTIFY   (1ULL << 63)
#define HV_X64_MSR_CRASH_PARAMS   \
    (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))

#define MSR_MTRRcap_VCNT                8

static int num_architectural_pmu_counters = MAX_GP_COUNTERS;

/* Helpers to keep track of kvm_msr_entry_set() calls: */

struct kvm_msr_entry {
  int e;
};

static void entry_set(struct kvm_msr_entry *e)
{
}

#define kvm_msr_entry_set(e, idx, v) entry_set(e)

int main(int argc, char *argv[])
{
    struct {
        struct kvm_msr_entry entries[150];
    } msr_data;
    struct kvm_msr_entry *msrs = msr_data.entries;
    int n = 0, i;

    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
    kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
                          env->msr_ia32_misc_enable);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
    }
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
    }
#if 1
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
        kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
        kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
        kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
    }
#endif
    /*
     * The following MSRs have side effects on the guest or are too heavy
     * for normal writeback. Limit them to reset or full state updates.
     */
    if (1) {
        kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
        kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
                          env->system_time_msr);
        kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
        if (1) {
            kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
                              env->async_pf_en_msr);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
                              env->pv_eoi_en_msr);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
                              env->steal_time_msr);
        }
        if (1) {
            /* Stop the counter.  */
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);

            /* Set the counter values.  */
            for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
                kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
                                  env->msr_fixed_counters[i]);
            }
            for (i = 0; i < num_architectural_pmu_counters; i++) {
                kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
                                  env->msr_gp_counters[i]);
                kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
                                  env->msr_gp_evtsel[i]);
            }
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
                              env->msr_global_status);
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
                              env->msr_global_ovf_ctrl);

            /* Now start the PMU.  */
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
                              env->msr_fixed_ctr_ctrl);
            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
                              env->msr_global_ctrl);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
                              env->msr_hv_guest_os_id);
            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
                              env->msr_hv_hypercall);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
                              env->msr_hv_vapic);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
                              env->msr_hv_tsc);
        }
        if (1) {
            int j;

            for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
                kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
                                  env->msr_hv_crash_params[j]);

            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
                              HV_X64_MSR_CRASH_CTL_NOTIFY);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
                              env->msr_hv_runtime);
        }
        if (1) {
            kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
            kvm_msr_entry_set(&msrs[n++],
                              MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
            for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
                kvm_msr_entry_set(&msrs[n++],
                                  MSR_MTRRphysBase(i), env->mtrr_var[i].base);
                kvm_msr_entry_set(&msrs[n++],
                                  MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
            }
        }

        /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
         *       kvm_put_msr_feature_control. */
    }
    if (1) {
        int i;

        kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
        kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
        for (i = 0; i < MCG_BANKS * 4; i++) {
            kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
        }
    }

    printf("will put %d MSRs\n", n);

    return 0;
}