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KodoPenLight - ATtiny102
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| ; | |
| ; KodoPenLight - ATtiny102 | |
| ; | |
| ; main.asm | |
| ; | |
| ; Created: 2018/06/02 | |
| ; Author : applause | |
| ; | |
| .org 0 | |
| rjmp start | |
| .org 2 | |
| rjmp _PCINT0 | |
| .org 5 | |
| rjmp _TIM0_OVF | |
| ldi r18, 14 | |
| out DDRB, r18 | |
| ldi r18, 5 | |
| out DDRA, r18 | |
| ldi r18, 2 | |
| out PUEA, r18 | |
| test: | |
| in r18, PINA | |
| andi r18, 2 | |
| rjmp next | |
| brne nz | |
| ldi r18, 0 | |
| rjmp next | |
| nz: | |
| ldi r18, 2 | |
| next: | |
| out PORTB, r18 | |
| rjmp test | |
| start: | |
| ldi r18, 1 | |
| out TCCR0B, r18 | |
| ldi r18, 0xD8 | |
| out CCP, r18 | |
| ldi r18, 1 | |
| out CLKMSR, r18 | |
| ldi r18, 0xD8 | |
| out CCP, r18 | |
| ldi r18, 1 | |
| out CLKPSR, r18 | |
| ldi r18, 2 | |
| out PUEA, r18 | |
| ldi r18, 14 | |
| out DDRB, r18 | |
| ldi r18, 14 | |
| out PORTB, r18 | |
| ldi r18, 1 | |
| out PCIFR, r18 ; PCIF0 clear | |
| out PCICR, r18 ; PCIE0 = enabled | |
| ldi r18, 2 | |
| out PCMSK0, r18 ; PCINT1 = enabled | |
| //sei | |
| ldi r21, 3 | |
| again: | |
| loop: | |
| ldi r18, 14 | |
| out PORTB, r18 | |
| sbis PINA, 1 | |
| rjmp loop | |
| ldi r18, 5 ; Sleep Mode = Power Down | |
| out SMCR, r18 | |
| ldi r18, 1 | |
| out PCIFR, r18 ; PCIF0 clear | |
| sei | |
| sleep | |
| cli | |
| ldi r18, 0 | |
| out SMCR, r18 | |
| ldi r18, 1 | |
| out PCIFR, r18 ; PCIF0 clear | |
| ldi r20, 0 | |
| ldi r21, 16 | |
| ldi r22, 5 | |
| loop1: | |
| ldi r16, 16 | |
| wait1: | |
| ; RED | |
| cp r16, r20 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 3 | |
| ; GREEN | |
| cp r16, r21 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 1 | |
| ; BLUE | |
| cp r16, r22 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 2 | |
| out PORTB, r19 | |
| dec r16 | |
| brne wait1 | |
| sbis PCIFR, 0 ; skip if PCIF0 set | |
| rjmp loop1 | |
| ldi r18, 1 | |
| out PCIFR, r18 | |
| sbic PINA, 1 | |
| rjmp loop1 | |
| ldi r20, 15 ; RED | |
| ldi r21, 12 ; GREEN | |
| ldi r22, 0 ; BLUE | |
| loop2: | |
| ldi r16, 16 | |
| wait2: | |
| ; RED | |
| cp r16, r20 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 3 | |
| ; GREEN | |
| cp r16, r21 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 1 | |
| ; BLUE | |
| cp r16, r22 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 2 | |
| out PORTB, r19 | |
| dec r16 | |
| brne wait2 | |
| sbis PCIFR, 0 ; skip if PCIF0 set | |
| rjmp loop2 | |
| ldi r18, 1 | |
| out PCIFR, r18 | |
| sbic PINA, 1 | |
| rjmp loop2 | |
| ldi r20, 15 ; RED | |
| ldi r21, 4 ; GREEN | |
| ldi r22, 5 ; BLUE | |
| loop3: | |
| ldi r16, 16 | |
| wait3: | |
| ; RED | |
| cp r16, r20 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 3 | |
| ; GREEN | |
| cp r16, r21 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 1 | |
| ; BLUE | |
| cp r16, r22 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 2 | |
| out PORTB, r19 | |
| dec r16 | |
| brne wait3 | |
| sbis PCIFR, 0 ; skip if PCIF0 set | |
| rjmp loop3 | |
| ldi r18, 1 | |
| out PCIFR, r18 | |
| sbic PINA, 1 | |
| rjmp loop3 | |
| ldi r20, 16 ; RED | |
| ldi r21, 0 ; GREEN | |
| ldi r22, 0 ; BLUE | |
| loop4: | |
| ldi r16, 16 | |
| wait4: | |
| ; RED | |
| cp r16, r20 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 3 | |
| ; GREEN | |
| cp r16, r21 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 1 | |
| ; BLUE | |
| cp r16, r22 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 2 | |
| out PORTB, r19 | |
| dec r16 | |
| brne wait4 | |
| sbis PCIFR, 0 ; skip if PCIF0 set | |
| rjmp loop4 | |
| ldi r18, 1 | |
| out PCIFR, r18 | |
| sbic PINA, 1 | |
| rjmp loop4 | |
| ldi r20, 0 ; RED | |
| ldi r21, 0 ; GREEN | |
| ldi r22, 16 ; BLUE | |
| loop5: | |
| ldi r16, 16 | |
| wait5: | |
| ; RED | |
| cp r16, r20 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 3 | |
| ; GREEN | |
| cp r16, r21 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 1 | |
| ; BLUE | |
| cp r16, r22 | |
| in r23, SREG | |
| inc r23 ; invert bit 0 | |
| bst r23, 0 | |
| bld r19, 2 | |
| out PORTB, r19 | |
| dec r16 | |
| brne wait5 | |
| sbis PCIFR, 0 ; skip if PCIF0 set | |
| rjmp loop5 | |
| ldi r18, 1 | |
| out PCIFR, r18 | |
| sbic PINA, 1 | |
| rjmp loop5 | |
| rjmp loop | |
| wait99: | |
| ldi r19, 14 | |
| out PORTB, r19 | |
| rjmp wait99 | |
| ldi r19, 14 | |
| out PORTB, r19 | |
| ldi r18, 1 | |
| out SMCR, r18 ; Sleep Mode = Idle | |
| ldi r18, 1 | |
| out PCIFR, r18 ; PCIF0 clear | |
| ldi r18, 1 | |
| out TIFR0, r18 ; TOV0 clear | |
| ldi r18, 1 | |
| out TIMSK0, r18 ; TOIE0 = ebaled | |
| ldi r18, 1 | |
| out TCCR0B, r18 ; CS = 1 (Clk_{I/O}) | |
| sei | |
| sleep | |
| cli | |
| ldi r18, 0 | |
| out TCCR0B, r18 ; CS = 0 (no clock, timer stopped) | |
| ldi r18, 0 | |
| out SMCR, r18 | |
| rjmp again | |
| end: | |
| rjmp end | |
| _PCINT0: | |
| reti | |
| _TIM0_OVF: | |
| reti |
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