SR mandali, D flib-flobu

D_latch.v

module D_latch (Clk, D, Q);
	input Clk, D;
	output Q;

	wire R, S_g, R_g, Qa, Qb /* synthesis keep */ ;

	assign R = ~D;
	assign S_g = ~(D & Clk);
	assign R_g = ~(R & Clk);
	assign Qa = ~(S_g & Qb);
	assign Qb = ~(R_g & Qa);

	assign Q = Qa;

endmodule

uygulama1.v

module uygulama1 (Clk, R, S, Q);
	input Clk, R, S;
	output Q;

	wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

	and (R_g, R, Clk);
	and (S_g, S, Clk);
	nor (Qa, R_g, Qb);
	nor (Qb, S_g, Qa);

	assign Q = Qa;

endmodule

uygulama1b.v

module uygulama1 (Clk, R, S, Q);
	input Clk, R, S;
	output Q;

	wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

	assign R_g = R & Clk;
	assign S_g = S & Clk;
	assign Qa = ~(R_g | Qb);
	assign Qb = ~(S_g | Qa);

	assign Q = Qa;

endmodule

uygulama2.v

// Girisler:
//	Clk: saat
//	D: data
//
// Cikisler:
//	Qa: D flip-flopu cikisi
//	Qb: pozitif kenar tetiklemeli D flip-flopu cikisi
//	Qc: negatif kenar tetiklemeli D flip-flopu cikisi
module uygulama2 (Clk, D, Qa, Qb, Qc);
	input Clk, D;
	output reg Qa, Qb, Qc;
	
	// D flip-flopu
	always @( * )
		if (Clk == 1'b1)
			Qa = D;
	
	// pozitif kenar tetiklemeli D FF
	always @(posedge Clk) 
		Qb <= D;
	
	// negatif kenar tetiklemeli D FF
	always @(negedge Clk)
		Qc <= D;
endmodule