Chained FSM

test.v

module stage(clock, reset, in, out);
  input wire clock;
  input wire reset;
  input wire in;
  output reg out;
  always @(posedge clock) begin
    if (reset) begin
      out <= 1;
    end else begin
      out <= !in;
    end
  end
endmodule

module stage_test;
  reg in = 1;
  wire between;
  wire out;
  reg reset;

  reg clock = 2;
  always #6 clock = !clock;
  
  stage stage2(clock, reset, in, between);
  stage stage3(clock, reset, between, out);
  initial begin
    # 11 reset = 1;
    # 11 reset = 0;
    # 1 in = 1;
    # 11 in = 0;
    # 11 in = 1;
    # 101 $stop;
  end
    
  initial
     $monitor("At time %t, reset=%d clock=%d in=%d between=%d out=%d", $time, reset, clock, in, between, out);

endmodule

Good job :)

You can of course which that more tersely in modern Verilog:

module stage(
  input clock,
  input reset
  input in;
  output reg out);
  always @(posedge clock) out <= reset ? 1'd 1 : !in;
endmodule

Note explicit sizing the constant isn't strictly required, but tools will yell at you about assigning a 32-bit value to a 1-bit register otherwise.