Created
October 3, 2016 11:28
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| VertexShaderHeader | |
| index = 0 | |
| size = 312 | |
| mode = UniformRegister | |
| uniformBlockCount = 0 | |
| uniformVarCount = 1 | |
| uniformVars[0] | |
| name = u_offset | |
| type = Float4 | |
| count = 1 | |
| offset = 0 | |
| block = -1 | |
| initialValueCount = 0 | |
| loopVarCount = 0 | |
| samplerVarCount = 0 | |
| attribVarCount = 2 | |
| attribVars[0] | |
| name = a_position | |
| type = Float4 | |
| count = 0 | |
| location = 0 | |
| attribVars[1] | |
| name = a_texCoord | |
| type = Float2 | |
| count = 0 | |
| location = 1 | |
| ringItemsize = 0 | |
| hasStreamOut = 0 | |
| SQ_PGM_RESOURCES_VS | |
| NUM_GPRS = 3 | |
| STACK_SIZE = 1 | |
| DX10_CLAMP = false | |
| PRIME_CACHE_PGM_EN = false | |
| PRIME_CACHE_ON_DRAW = false | |
| FETCH_CACHE_LINES = 0 | |
| UNCACHED_FIRST_INST = false | |
| PRIME_CACHE_ENABLE = false | |
| PRIME_CACHE_ON_CONST = false | |
| VGT_PRIMITIVEID_EN | |
| PRIMITIVEID_EN = false | |
| SPI_VS_OUT_CONFIG | |
| VS_PER_COMPONENT = false | |
| VS_EXPORT_COUNT = 0 | |
| VS_EXPORTS_FOG = false | |
| VS_OUT_FOG_VEC_ADDR = 0 | |
| NUM_SPI_VS_OUT_ID = 1 | |
| SPI_VS_OUT_ID[0] | |
| SEMANTIC_0 = 0 | |
| SEMANTIC_1 = 255 | |
| SEMANTIC_2 = 255 | |
| SEMANTIC_3 = 255 | |
| PA_CL_VS_OUT_CNTL | |
| CLIP_DIST_ENA_0 = false | |
| CLIP_DIST_ENA_1 = false | |
| CLIP_DIST_ENA_2 = false | |
| CLIP_DIST_ENA_3 = false | |
| CLIP_DIST_ENA_4 = false | |
| CLIP_DIST_ENA_5 = false | |
| CLIP_DIST_ENA_6 = false | |
| CLIP_DIST_ENA_7 = false | |
| CULL_DIST_ENA_0 = false | |
| CULL_DIST_ENA_1 = false | |
| CULL_DIST_ENA_2 = false | |
| CULL_DIST_ENA_3 = false | |
| CULL_DIST_ENA_4 = false | |
| CULL_DIST_ENA_5 = false | |
| CULL_DIST_ENA_6 = false | |
| CULL_DIST_ENA_7 = false | |
| USE_VTX_POINT_SIZE = false | |
| USE_VTX_EDGE_FLAG = false | |
| USE_VTX_RENDER_TARGET_INDX = false | |
| USE_VTX_VIEWPORT_INDX = false | |
| USE_VTX_KILL_FLAG = false | |
| VS_OUT_MISC_VEC_ENA = false | |
| VS_OUT_CCDIST0_VEC_ENA = false | |
| VS_OUT_CCDIST1_VEC_ENA = false | |
| VS_OUT_MISC_SIDE_BUS_ENA = false | |
| USE_VTX_GS_CUT_FLAG = false | |
| SQ_VTX_SEMANTIC_CLEAR | |
| CLEAR = 4294967292 | |
| NUM_SQ_VTX_SEMANTIC = 2 | |
| SQ_VTX_SEMANTIC[0] | |
| SEMANTIC_ID = 0 | |
| SQ_VTX_SEMANTIC[1] | |
| SEMANTIC_ID = 1 | |
| VGT_STRMOUT_BUFFER_EN | |
| BUFFER_0_EN = false | |
| BUFFER_1_EN = false | |
| BUFFER_2_EN = false | |
| BUFFER_3_EN = false | |
| VGT_VERTEX_REUSE_BLOCK_CNTL | |
| VTX_REUSE_DEPTH = 14 | |
| VGT_HOS_REUSE_DEPTH | |
| REUSE_DEPTH = 16 | |
| VertexShaderProgram | |
| index = 0 | |
| size = 312 | |
| 00 CALL_FS NO_BARRIER | |
| 01 ALU ADDR(32) CNT(6) | |
| 0 x: ADD R1.x, R1.x, C0.x | |
| y: ADD R1.y, R1.y, C0.y | |
| z: ADD R1.z, R1.z, C0.z | |
| w: ADD R1.w, R1.w, C0.w | |
| t: MOV R0.x, R2.x | |
| 1 y: MOV R0.y, R2.y | |
| 02 EXP_DONE POS0, R1.xyzw | |
| 03 EXP_DONE PARAM0, R0.xyzz NO_BARRIER | |
| 04 ALU ADDR(38) CNT(1) | |
| 2 x: NOP ____ | |
| 05 NOP | |
| PixelShaderHeader | |
| index = 0 | |
| size = 144 | |
| mode = UniformRegister | |
| uniformBlockCount = 0 | |
| uniformVarCount = 0 | |
| initialValueCount = 0 | |
| loopVarCount = 0 | |
| samplerVarCount = 1 | |
| samplerVars[0] | |
| name = s_texture | |
| type = Sampler2D | |
| location = 0 | |
| SQ_PGM_RESOURCES_PS | |
| NUM_GPRS = 1 | |
| STACK_SIZE = 0 | |
| DX10_CLAMP = false | |
| PRIME_CACHE_PGM_EN = false | |
| PRIME_CACHE_ON_DRAW = false | |
| FETCH_CACHE_LINES = 0 | |
| UNCACHED_FIRST_INST = false | |
| PRIME_CACHE_ENABLE = false | |
| PRIME_CACHE_ON_CONST = false | |
| CLAMP_CONSTS = false | |
| SQ_PGM_EXPORTS_PS | |
| EXPORT_MODE = 2 | |
| SPI_PS_IN_CONTROL_0 | |
| NUM_INTERP = 1 | |
| POSITION_ENA = false | |
| POSITION_CENTROID = false | |
| POSITION_ADDR = 0 | |
| PARAM_GEN = 0 | |
| PARAM_GEN_ADDR = 0 | |
| BARYC_SAMPLE_CNTL = 1 | |
| PERSP_GRADIENT_ENA = true | |
| LINEAR_GRADIENT_ENA = false | |
| POSITION_SAMPLE = false | |
| BARYC_AT_SAMPLE_ENA = false | |
| SPI_PS_IN_CONTROL_1 | |
| GEN_INDEX_PIX = false | |
| GEN_INDEX_PIX_ADDR = 0 | |
| FRONT_FACE_ENA = false | |
| FRONT_FACE_CHAN = 0 | |
| FRONT_FACE_ALL_BITS = false | |
| FRONT_FACE_ADDR = 0 | |
| FOG_ADDR = 0 | |
| FIXED_PT_POSITION_ENA = false | |
| FIXED_PT_POSITION_ADDR = 0 | |
| POSITION_ULC = false | |
| NUM_SPI_PS_INPUT_CNTL = 1 | |
| SEMANTIC = 0 | |
| DEFAULT_VAL = 1 | |
| FLAT_SHADE = false | |
| SEL_CENTROID = false | |
| SEL_LINEAR = false | |
| CYL_WRAP = 0 | |
| PT_SPRITE_TEX = false | |
| SEL_SAMPLE = false | |
| CB_SHADER_MASK | |
| OUTPUT0_ENABLE = 15 | |
| OUTPUT1_ENABLE = 0 | |
| OUTPUT2_ENABLE = 0 | |
| OUTPUT3_ENABLE = 0 | |
| OUTPUT4_ENABLE = 0 | |
| OUTPUT5_ENABLE = 0 | |
| OUTPUT6_ENABLE = 0 | |
| OUTPUT7_ENABLE = 0 | |
| CB_SHADER_CONTROL | |
| RT0_ENABLE = true | |
| RT1_ENABLE = false | |
| RT2_ENABLE = false | |
| RT3_ENABLE = false | |
| RT4_ENABLE = false | |
| RT5_ENABLE = false | |
| RT6_ENABLE = false | |
| RT7_ENABLE = false | |
| DB_SHADER_CONTROL | |
| Z_EXPORT_ENABLE = false | |
| STENCIL_REF_EXPORT_ENABLE = false | |
| Z_ORDER = 1 | |
| KILL_ENABLE = false | |
| COVERAGE_TO_MASK_ENABLE = false | |
| MASK_EXPORT_ENABLE = false | |
| DUAL_EXPORT_ENABLE = false | |
| EXEC_ON_HIER_FAIL = false | |
| EXEC_ON_NOOP = false | |
| ALPHA_TO_MASK_DISABLE = false | |
| SPI_INPUT_Z | |
| PROVIDE_Z_TO_SPI = false | |
| PixelShaderProgram | |
| index = 0 | |
| size = 144 | |
| 00 TEX ADDR(16) CNT(1) VALID_PIX | |
| 0 SAMPLE R0.xyzw, R0.xy0x, t0, s0 | |
| 01 EXP_DONE PIXEL0, R0.xyzw | |
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