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July 8, 2017 18:56
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| /* | |
| * This devicetree is generated by sopc2dts version 17.0 [3927ad8028c372247b58d3c7494076a6183668dc] on Sat Jul 08 18:40:08 UTC 2017 | |
| * Sopc2dts is written by Walter Goossens <[email protected]> | |
| * in cooperation with the nios2 community <[email protected]> | |
| */ | |
| /dts-v1/; | |
| / { | |
| model = "Altera SOCFPGA Arria 10"; /* appended from boardinfo */ | |
| compatible = "altr,socfpga-arria10", "altr,socfpga"; /* appended from boardinfo */ | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| aliases { | |
| ethernet0 = "/sopc@0/ethernet@0xff800000"; | |
| ethernet1 = "/sopc@0/ethernet@0xff802000"; | |
| ethernet2 = "/sopc@0/ethernet@0xff804000"; | |
| serial0 = "/sopc@0/serial@0xffc02100"; | |
| }; //end aliases | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| enable-method = "altr,socfpga-a10-smp"; /* appended from boardinfo */ | |
| a10_hps_arm_a9_0: cpu@0x0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9-17.0", "arm,cortex-a9"; | |
| reg = <0x00000000>; | |
| next-level-cache = <&a10_hps_mpu_reg_l2_MPUL2>; /* appended from boardinfo */ | |
| }; //end cpu@0x0 (a10_hps_arm_a9_0) | |
| a10_hps_arm_a9_1: cpu@0x1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9-17.0", "arm,cortex-a9"; | |
| reg = <0x00000001>; | |
| next-level-cache = <&a10_hps_mpu_reg_l2_MPUL2>; /* appended from boardinfo */ | |
| }; //end cpu@0x1 (a10_hps_arm_a9_1) | |
| }; //end cpus | |
| memory { | |
| device_type = "memory"; | |
| reg = <0xc0000000 0x00040000>; | |
| }; //end memory | |
| clocks { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clk_0: clk_0 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <100000000>; /* 100.00 MHz */ | |
| clock-output-names = "clk_0-clk"; | |
| }; //end clk_0 (clk_0) | |
| clock_bridge_0: clock_bridge_0 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <74250000>; /* 74.25 MHz */ | |
| clock-output-names = "clock_bridge_0-out_clk"; | |
| }; //end clock_bridge_0 (clock_bridge_0) | |
| a10_hps_eosc1: a10_hps_eosc1 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <25000000>; /* 25.00 MHz */ | |
| clock-output-names = "a10_hps_eosc1-clk"; | |
| }; //end a10_hps_eosc1 (a10_hps_eosc1) | |
| a10_hps_cb_intosc_hs_div2_clk: a10_hps_cb_intosc_hs_div2_clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <0>; /* 0.00 Hz */ | |
| clock-output-names = "a10_hps_cb_intosc_hs_div2_clk-clk"; | |
| }; //end a10_hps_cb_intosc_hs_div2_clk (a10_hps_cb_intosc_hs_div2_clk) | |
| a10_hps_cb_intosc_ls_clk: a10_hps_cb_intosc_ls_clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <60000000>; /* 60.00 MHz */ | |
| clock-output-names = "a10_hps_cb_intosc_ls_clk-clk"; | |
| }; //end a10_hps_cb_intosc_ls_clk (a10_hps_cb_intosc_ls_clk) | |
| a10_hps_f2s_free_clk: a10_hps_f2s_free_clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <200000000>; /* 200.00 MHz */ | |
| clock-output-names = "a10_hps_f2s_free_clk-clk"; | |
| }; //end a10_hps_f2s_free_clk (a10_hps_f2s_free_clk) | |
| }; //end clocks | |
| sopc0: sopc@0 { | |
| device_type = "soc"; | |
| ranges; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "ALTR,avalon", "simple-bus"; | |
| bus-frequency = <0>; | |
| a10_hps_bridges: bridge@0xc0000000 { | |
| compatible = "altr,bridge-17.0", "simple-bus"; | |
| reg = <0xc0000000 0x20000000>, | |
| <0xff200000 0x00200000>; | |
| reg-names = "axi_h2f", "axi_h2f_lw"; | |
| clocks = <&clk_0 &clk_0 &clk_0 &clk_0>; | |
| clock-names = "h2f_axi_clock", "h2f_lw_axi_clock", "f2sdram0_clock", "f2sdram2_clock"; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| ranges = <0x00000000 0x00000000 0xc0000000 0x00040000>, | |
| <0x00000001 0x00000100 0xff200100 0x00000100>, | |
| <0x00000001 0x00000000 0xff200000 0x00000008>, | |
| <0x00000001 0x00000010 0xff200010 0x00000010>, | |
| <0x00000001 0x00000020 0xff200020 0x00000010>, | |
| <0x00000001 0x00000030 0xff200030 0x00000010>; | |
| ILC: ilc@0x100000100 { | |
| compatible = "altr,altera_ilc-17.0", "altr,ilc-1.0"; | |
| reg = <0x00000001 0x00000100 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 19 1 0 20 1>; | |
| interrupt-names = "button_pio", "dipsw_pio"; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| clocks = <&clk_0>; | |
| altr,sw-fifo-depth = <32>; /* embeddedsw.dts.params.altr,sw-fifo-depth type NUMBER */ | |
| status = "disabled"; /* appended from boardinfo */ | |
| }; //end ilc@0x100000100 (ILC) | |
| sys_id: sysid@0x100000000 { | |
| compatible = "altr,sysid-17.0", "altr,sysid-1.0"; | |
| reg = <0x00000001 0x00000000 0x00000008>; | |
| clocks = <&clk_0>; | |
| id = <3221772800>; /* embeddedsw.dts.params.id type NUMBER */ | |
| timestamp = <1499422328>; /* embeddedsw.dts.params.timestamp type NUMBER */ | |
| }; //end sysid@0x100000000 (sys_id) | |
| led_pio: gpio@0x100000010 { | |
| compatible = "altr,pio-17.0", "altr,pio-1.0"; | |
| reg = <0x00000001 0x00000010 0x00000010>; | |
| clocks = <&clk_0>; | |
| altr,gpio-bank-width = <4>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ | |
| resetvalue = <0>; /* embeddedsw.dts.params.resetvalue type NUMBER */ | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| }; //end gpio@0x100000010 (led_pio) | |
| button_pio: gpio@0x100000020 { | |
| compatible = "altr,pio-17.0", "altr,pio-1.0"; | |
| reg = <0x00000001 0x00000020 0x00000010>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 19 1>; | |
| clocks = <&clk_0>; | |
| altr,gpio-bank-width = <4>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ | |
| altr,interrupt-type = <2>; /* embeddedsw.dts.params.altr,interrupt-type type NUMBER */ | |
| altr,interrupt_type = <2>; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ | |
| edge_type = <1>; /* embeddedsw.dts.params.edge_type type NUMBER */ | |
| level_trigger = <0>; /* embeddedsw.dts.params.level_trigger type NUMBER */ | |
| resetvalue = <0>; /* embeddedsw.dts.params.resetvalue type NUMBER */ | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| }; //end gpio@0x100000020 (button_pio) | |
| dipsw_pio: gpio@0x100000030 { | |
| compatible = "altr,pio-17.0", "altr,pio-1.0"; | |
| reg = <0x00000001 0x00000030 0x00000010>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 20 1>; | |
| clocks = <&clk_0>; | |
| altr,gpio-bank-width = <4>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ | |
| altr,interrupt-type = <3>; /* embeddedsw.dts.params.altr,interrupt-type type NUMBER */ | |
| altr,interrupt_type = <3>; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ | |
| edge_type = <2>; /* embeddedsw.dts.params.edge_type type NUMBER */ | |
| level_trigger = <0>; /* embeddedsw.dts.params.level_trigger type NUMBER */ | |
| resetvalue = <0>; /* embeddedsw.dts.params.resetvalue type NUMBER */ | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| }; //end gpio@0x100000030 (dipsw_pio) | |
| }; //end bridge@0xc0000000 (a10_hps_bridges) | |
| a10_hps_arm_gic_0: intc@0xffffd000 { | |
| compatible = "arm,cortex-a9-gic-17.0", "arm,cortex-a9-gic"; | |
| reg = <0xffffd000 0x00001000>, | |
| <0xffffc100 0x00000100>; | |
| reg-names = "axi_slave0", "axi_slave1"; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| }; //end intc@0xffffd000 (a10_hps_arm_gic_0) | |
| a10_hps_baum_clkmgr: clkmgr@0xffd04000 { | |
| compatible = "altr,clk-mgr-17.0", "altr,clk-mgr"; | |
| reg = <0xffd04000 0x00001000>; | |
| clocks = <&a10_hps_eosc1 &a10_hps_cb_intosc_hs_div2_clk &a10_hps_cb_intosc_ls_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "eosc1", "cb_intosc_hs_div2_clk", "cb_intosc_ls_clk", "f2s_free_clk"; | |
| clock_tree { | |
| #size-cells = <0>; | |
| #address-cells = <1>; | |
| main_pll: main_pll { | |
| compatible = "altr,socfpga-a10-pll-clock"; | |
| reg = <0x00000040>; | |
| clocks = <&a10_hps_eosc1 &a10_hps_cb_intosc_ls_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "a10_hps_eosc1", "a10_hps_cb_intosc_ls_clk", "a10_hps_f2s_free_clk"; | |
| #clock-cells = <0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| main_mpu_base_clk: main_mpu_base_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000040>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| div-reg = <0x00000140 0x00000000 0x0000000b>; | |
| }; //end main_mpu_base_clk (main_mpu_base_clk) | |
| main_noc_base_clk: main_noc_base_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000040>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| div-reg = <0x00000144 0x00000000 0x0000000b>; | |
| }; //end main_noc_base_clk (main_noc_base_clk) | |
| main_emaca_clk: main_emaca_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000068>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_emaca_clk (main_emaca_clk) | |
| main_emacb_clk: main_emacb_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x0000006c>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_emacb_clk (main_emacb_clk) | |
| main_emac_ptp_clk: main_emac_ptp_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000070>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_emac_ptp_clk (main_emac_ptp_clk) | |
| main_gpio_db_clk: main_gpio_db_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000074>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_gpio_db_clk (main_gpio_db_clk) | |
| main_sdmmc_clk: main_sdmmc_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000078>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_sdmmc_clk (main_sdmmc_clk) | |
| main_s2f_usr0_clk: main_s2f_usr0_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x0000007c>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_s2f_usr0_clk (main_s2f_usr0_clk) | |
| main_s2f_usr1_clk: main_s2f_usr1_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000080>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_s2f_usr1_clk (main_s2f_usr1_clk) | |
| main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000084>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_hmc_pll_ref_clk (main_hmc_pll_ref_clk) | |
| main_periph_ref_clk: main_periph_ref_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x0000009c>; | |
| clocks = <&main_pll>; | |
| #clock-cells = <0>; | |
| }; //end main_periph_ref_clk (main_periph_ref_clk) | |
| }; //end main_pll (main_pll) | |
| periph_pll: periph_pll { | |
| compatible = "altr,socfpga-a10-pll-clock"; | |
| reg = <0x000000c0>; | |
| clocks = <&a10_hps_eosc1 &a10_hps_cb_intosc_ls_clk &a10_hps_f2s_free_clk &main_periph_ref_clk>; | |
| clock-names = "a10_hps_eosc1", "a10_hps_cb_intosc_ls_clk", "a10_hps_f2s_free_clk", "main_periph_ref_clk"; | |
| #clock-cells = <0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| peri_mpu_base_clk: peri_mpu_base_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000c0>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| div-reg = <0x00000140 0x00000010 0x0000000b>; | |
| }; //end peri_mpu_base_clk (peri_mpu_base_clk) | |
| peri_noc_base_clk: peri_noc_base_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000c0>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| div-reg = <0x00000144 0x00000010 0x0000000b>; | |
| }; //end peri_noc_base_clk (peri_noc_base_clk) | |
| peri_emaca_clk: peri_emaca_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000e8>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_emaca_clk (peri_emaca_clk) | |
| peri_emacb_clk: peri_emacb_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000ec>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_emacb_clk (peri_emacb_clk) | |
| peri_emac_ptp_clk: peri_emac_ptp_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000f0>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_emac_ptp_clk (peri_emac_ptp_clk) | |
| peri_gpio_db_clk: peri_gpio_db_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000f4>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_gpio_db_clk (peri_gpio_db_clk) | |
| peri_sdmmc_clk: peri_sdmmc_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000f8>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_sdmmc_clk (peri_sdmmc_clk) | |
| peri_s2f_usr0_clk: peri_s2f_usr0_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x000000fc>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_s2f_usr0_clk (peri_s2f_usr0_clk) | |
| peri_s2f_usr1_clk: peri_s2f_usr1_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000100>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_s2f_usr1_clk (peri_s2f_usr1_clk) | |
| peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| reg = <0x00000104>; | |
| clocks = <&periph_pll>; | |
| #clock-cells = <0>; | |
| }; //end peri_hmc_pll_ref_clk (peri_hmc_pll_ref_clk) | |
| }; //end periph_pll (periph_pll) | |
| mpu_periph_clk: mpu_periph_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&mpu_free_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x00000048 0x00000000>; | |
| fixed-divider = <4>; | |
| }; //end mpu_periph_clk (mpu_periph_clk) | |
| l4_main_clk: l4_main_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&noc_free_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x00000048 0x00000001>; | |
| div-reg = <0x000000a8 0x00000000 0x00000002>; | |
| }; //end l4_main_clk (l4_main_clk) | |
| l4_mp_clk: l4_mp_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&noc_free_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x00000048 0x00000002>; | |
| div-reg = <0x000000a8 0x00000008 0x00000002>; | |
| }; //end l4_mp_clk (l4_mp_clk) | |
| l4_sp_clk: l4_sp_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&noc_free_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x00000048 0x00000003>; | |
| div-reg = <0x000000a8 0x00000010 0x00000002>; | |
| }; //end l4_sp_clk (l4_sp_clk) | |
| emac0_clk: emac0_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000000>; | |
| }; //end emac0_clk (emac0_clk) | |
| emac1_clk: emac1_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000001>; | |
| }; //end emac1_clk (emac1_clk) | |
| emac2_clk: emac2_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000002>; | |
| }; //end emac2_clk (emac2_clk) | |
| emac_ptp_clk: emac_ptp_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000003>; | |
| }; //end emac_ptp_clk (emac_ptp_clk) | |
| gpio_db_clk: gpio_db_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000004>; | |
| }; //end gpio_db_clk (gpio_db_clk) | |
| sdmmc_clk: sdmmc_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&sdmmc_free_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000005>; | |
| clk-phase = <0 135>; /* appended from boardinfo */ | |
| }; //end sdmmc_clk (sdmmc_clk) | |
| s2f_user1_clk: s2f_user1_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&peri_s2f_usr1_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000006>; | |
| }; //end s2f_user1_clk (s2f_user1_clk) | |
| reserved: reserved { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000007>; | |
| }; //end reserved (reserved) | |
| usb_clk: usb_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&l4_mp_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000008>; | |
| }; //end usb_clk (usb_clk) | |
| spi_m_clk: spi_m_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&l4_main_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x00000009>; | |
| }; //end spi_m_clk (spi_m_clk) | |
| nand_clk: nand_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&l4_mp_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x0000000a>; | |
| }; //end nand_clk (nand_clk) | |
| qspi_clk: qspi_clk { | |
| compatible = "altr,socfpga-a10-gate-clk"; | |
| clocks = <&l4_main_clk>; | |
| #clock-cells = <0>; | |
| clk-gate = <0x000000c8 0x0000000b>; | |
| }; //end qspi_clk (qspi_clk) | |
| mpu_free_clk: mpu_free_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| clocks = <&main_mpu_base_clk &peri_mpu_base_clk &a10_hps_eosc1 &a10_hps_cb_intosc_hs_div2_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "main_mpu_base_clk", "peri_mpu_base_clk", "a10_hps_eosc1", "a10_hps_cb_intosc_hs_div2_clk", "a10_hps_f2s_free_clk"; | |
| #clock-cells = <0>; | |
| reg = <0x00000060>; | |
| }; //end mpu_free_clk (mpu_free_clk) | |
| noc_free_clk: noc_free_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| clocks = <&main_noc_base_clk &peri_noc_base_clk &a10_hps_eosc1 &a10_hps_cb_intosc_hs_div2_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "main_noc_base_clk", "peri_noc_base_clk", "a10_hps_eosc1", "a10_hps_cb_intosc_hs_div2_clk", "a10_hps_f2s_free_clk"; | |
| #clock-cells = <0>; | |
| reg = <0x00000064>; | |
| }; //end noc_free_clk (noc_free_clk) | |
| s2f_usr1_clk: s2f_usr1_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| clocks = <&main_s2f_usr1_clk &peri_s2f_usr1_clk &a10_hps_eosc1 &a10_hps_cb_intosc_hs_div2_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "main_s2f_usr1_clk", "peri_s2f_usr1_clk", "a10_hps_eosc1", "a10_hps_cb_intosc_hs_div2_clk", "a10_hps_f2s_free_clk"; | |
| #clock-cells = <0>; | |
| reg = <0x00000104>; | |
| }; //end s2f_usr1_clk (s2f_usr1_clk) | |
| sdmmc_free_clk: sdmmc_free_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| clocks = <&main_sdmmc_clk &peri_sdmmc_clk &a10_hps_eosc1 &a10_hps_cb_intosc_hs_div2_clk &a10_hps_f2s_free_clk>; | |
| clock-names = "main_sdmmc_clk", "peri_sdmmc_clk", "a10_hps_eosc1", "a10_hps_cb_intosc_hs_div2_clk", "a10_hps_f2s_free_clk"; | |
| #clock-cells = <0>; | |
| reg = <0x000000f8>; | |
| fixed-divider = <4>; | |
| }; //end sdmmc_free_clk (sdmmc_free_clk) | |
| l4_sys_free_clk: l4_sys_free_clk { | |
| compatible = "altr,socfpga-a10-perip-clk"; | |
| clocks = <&noc_free_clk>; | |
| #clock-cells = <0>; | |
| fixed-divider = <4>; | |
| }; //end l4_sys_free_clk (l4_sys_free_clk) | |
| }; //end clock_tree | |
| }; //end clkmgr@0xffd04000 (a10_hps_baum_clkmgr) | |
| a10_hps_mpu_reg_l2_MPUL2: L2-cache@0xfffff000 { | |
| compatible = "arm,pl310-cache-17.0", "arm,pl310-cache"; | |
| reg = <0xfffff000 0x00001000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 18 4>; | |
| cache-level = <2>; /* embeddedsw.dts.params.cache-level type NUMBER */ | |
| cache-unified; /* appended from boardinfo */ | |
| arm,tag-latency = <1 1 1>; /* appended from boardinfo */ | |
| arm,data-latency = <2 1 1>; /* appended from boardinfo */ | |
| }; //end L2-cache@0xfffff000 (a10_hps_mpu_reg_l2_MPUL2) | |
| a10_hps_i_dma_DMASECURE: dma@0xffda1000 { | |
| compatible = "arm,pl330-17.0", "arm,pl330", "arm,primecell"; | |
| reg = <0xffda1000 0x00001000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 83 4>; | |
| clocks = <&l4_main_clk>; | |
| #dma-cells = <1>; /* embeddedsw.dts.params.#dma-cells type NUMBER */ | |
| #dma-channels = <8>; /* embeddedsw.dts.params.#dma-channels type NUMBER */ | |
| #dma-requests = <32>; /* embeddedsw.dts.params.#dma-requests type NUMBER */ | |
| clock-names = "apb_pclk"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| copy-align = <3>; /* embeddedsw.dts.params.copy-align type NUMBER */ | |
| nr-irqs = <9>; /* embeddedsw.dts.params.nr-irqs type NUMBER */ | |
| nr-valid-peri = <9>; /* embeddedsw.dts.params.nr-valid-peri type NUMBER */ | |
| }; //end dma@0xffda1000 (a10_hps_i_dma_DMASECURE) | |
| a10_hps_i_sys_mgr_core: sysmgr@0xffd06000 { | |
| compatible = "altr,sys-mgr-17.0", "altr,sys-mgr", "syscon"; | |
| reg = <0xffd06000 0x00000400>; | |
| cpu1-start-addr = <4291846704>; /* embeddedsw.dts.params.cpu1-start-addr type NUMBER */ | |
| }; //end sysmgr@0xffd06000 (a10_hps_i_sys_mgr_core) | |
| a10_hps_i_rst_mgr_rstmgr: rstmgr@0xffd05000 { | |
| compatible = "altr,rst-mgr-17.0", "altr,rst-mgr", "syscon"; | |
| reg = <0xffd05000 0x00000100>; | |
| #reset-cells = <1>; /* embeddedsw.dts.params.#reset-cells type NUMBER */ | |
| altr,modrst-offset = <32>; /* embeddedsw.dts.params.altr,modrst-offset type NUMBER */ | |
| }; //end rstmgr@0xffd05000 (a10_hps_i_rst_mgr_rstmgr) | |
| a10_hps_i_fpga_mgr_fpgamgrregs: fpgamgr@0xffd03000 { | |
| compatible = "altr,fpga-mgr-17.0", "altr,socfpga-a10-fpga-mgr"; | |
| reg = <0xffd03000 0x00001000>, | |
| <0xffcfe400 0x00000100>; | |
| reg-names = "axi_slave0", "axi_slave1"; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 123 4>; | |
| transport = "mmio"; /* embeddedsw.dts.params.transport type STRING */ | |
| clocks = <&l4_mp_clk>; /* appended from boardinfo */ | |
| }; //end fpgamgr@0xffd03000 (a10_hps_i_fpga_mgr_fpgamgrregs) | |
| a10_hps_timer: timer@0xffffc600 { | |
| compatible = "arm,cortex-a9-twd-timer-17.0", "arm,cortex-a9-twd-timer"; | |
| reg = <0xffffc600 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <1 13 3844>; | |
| clocks = <&mpu_periph_clk>; | |
| }; //end timer@0xffffc600 (a10_hps_timer) | |
| a10_hps_i_timer_sp_0_timer: timer@0xffc02700 { | |
| compatible = "snps,dw-apb-timer-sp-17.0", "snps,dw-apb-timer-sp"; | |
| reg = <0xffc02700 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 115 4>; | |
| clocks = <&l4_sp_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| }; //end timer@0xffc02700 (a10_hps_i_timer_sp_0_timer) | |
| a10_hps_i_timer_sp_1_timer: timer@0xffc02800 { | |
| compatible = "snps,dw-apb-timer-sp-17.0", "snps,dw-apb-timer-sp"; | |
| reg = <0xffc02800 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 116 4>; | |
| clocks = <&l4_sp_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| }; //end timer@0xffc02800 (a10_hps_i_timer_sp_1_timer) | |
| a10_hps_i_timer_sys_0_timer: timer@0xffd00000 { | |
| compatible = "snps,dw-apb-timer-osc-17.0", "snps,dw-apb-timer-osc"; | |
| reg = <0xffd00000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 117 4>; | |
| clocks = <&l4_sys_free_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| }; //end timer@0xffd00000 (a10_hps_i_timer_sys_0_timer) | |
| a10_hps_i_timer_sys_1_timer: timer@0xffd00100 { | |
| compatible = "snps,dw-apb-timer-osc-17.0", "snps,dw-apb-timer-osc"; | |
| reg = <0xffd00100 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 118 4>; | |
| clocks = <&l4_sys_free_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| }; //end timer@0xffd00100 (a10_hps_i_timer_sys_1_timer) | |
| a10_hps_i_watchdog_0_l4wd: timer@0xffd00200 { | |
| compatible = "snps,dw-wdt-17.0", "snps,dw-wdt"; | |
| reg = <0xffd00200 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 119 4>; | |
| clocks = <&l4_sys_free_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| status = "disabled"; /* appended from boardinfo */ | |
| }; //end timer@0xffd00200 (a10_hps_i_watchdog_0_l4wd) | |
| a10_hps_i_watchdog_1_l4wd: timer@0xffd00300 { | |
| compatible = "snps,dw-wdt-17.0", "snps,dw-wdt"; | |
| reg = <0xffd00300 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 120 4>; | |
| clocks = <&l4_sys_free_clk>; | |
| clock-names = "timer"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| }; //end timer@0xffd00300 (a10_hps_i_watchdog_1_l4wd) | |
| a10_hps_i_gpio_0_gpio: gpio@0xffc02900 { | |
| compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio"; | |
| reg = <0xffc02900 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 112 4>; | |
| clocks = <&l4_mp_clk>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| a10_hps_i_gpio_0_gpio_porta: gpio-controller@0 { | |
| compatible = "snps,dw-apb-gpio-port"; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| snps,nr-gpios = <24>; | |
| reg = <0>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <0 112 4>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| }; //end gpio-controller@0 (a10_hps_i_gpio_0_gpio_porta) | |
| }; //end gpio@0xffc02900 (a10_hps_i_gpio_0_gpio) | |
| a10_hps_i_gpio_1_gpio: gpio@0xffc02a00 { | |
| compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio"; | |
| reg = <0xffc02a00 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 113 4>; | |
| clocks = <&l4_mp_clk>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| a10_hps_i_gpio_1_gpio_porta: gpio-controller@0 { | |
| compatible = "snps,dw-apb-gpio-port"; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| snps,nr-gpios = <24>; | |
| reg = <0>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <0 113 4>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| }; //end gpio-controller@0 (a10_hps_i_gpio_1_gpio_porta) | |
| }; //end gpio@0xffc02a00 (a10_hps_i_gpio_1_gpio) | |
| a10_hps_i_gpio_2_gpio: gpio@0xffc02b00 { | |
| compatible = "snps,dw-apb-gpio", "snps,dw-gpio-17.0", "snps,dw-gpio"; | |
| reg = <0xffc02b00 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 114 4>; | |
| clocks = <&l4_mp_clk>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| a10_hps_i_gpio_2_gpio_porta: gpio-controller@0 { | |
| compatible = "snps,dw-apb-gpio-port"; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| snps,nr-gpios = <14>; | |
| reg = <0>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <0 114 4>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| }; //end gpio-controller@0 (a10_hps_i_gpio_2_gpio_porta) | |
| }; //end gpio@0xffc02b00 (a10_hps_i_gpio_2_gpio) | |
| a10_hps_i_uart_0_uart: serial@0xffc02000 { | |
| compatible = "snps,dw-apb-uart-17.0", "snps,dw-apb-uart"; | |
| reg = <0xffc02000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 110 4>; | |
| clocks = <&l4_sp_clk>; | |
| reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */ | |
| reg-shift = <2>; /* embeddedsw.dts.params.reg-shift type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end serial@0xffc02000 (a10_hps_i_uart_0_uart) | |
| a10_hps_i_uart_1_uart: serial@0xffc02100 { | |
| compatible = "snps,dw-apb-uart-17.0", "snps,dw-apb-uart"; | |
| reg = <0xffc02100 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 111 4>; | |
| clocks = <&l4_sp_clk>; | |
| reg-io-width = <4>; /* embeddedsw.dts.params.reg-io-width type NUMBER */ | |
| reg-shift = <2>; /* embeddedsw.dts.params.reg-shift type NUMBER */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end serial@0xffc02100 (a10_hps_i_uart_1_uart) | |
| a10_hps_i_emac_emac0: ethernet@0xff800000 { | |
| compatible = "synopsys,dwmac-17.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| reg = <0xff800000 0x00002000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 92 4>; | |
| clocks = <&l4_mp_clk>; /* appended from boardinfo */ | |
| clock-names = "stmmaceth"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */ | |
| rx-fifo-depth = <16384>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */ | |
| snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */ | |
| snps,perfect-filter-entries = <128>; /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| tx-fifo-depth = <4096>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */ | |
| address-bits = <48>; | |
| max-frame-size = <3800>; /* appended from boardinfo */ | |
| local-mac-address = [00 00 00 00 00 00]; | |
| snps,axi-config = <&socfpga_axi_setup>; /* appended from boardinfo */ | |
| resets = <&a10_hps_i_rst_mgr_rstmgr 32>; /* appended from boardinfo */ | |
| reset-names = "stmmaceth"; /* appended from boardinfo */ | |
| altr,sysmgr-syscon = <&a10_hps_i_sys_mgr_core 0x00000044 0>; /* appended from boardinfo */ | |
| phy-mode = "rgmii"; /* appended from boardinfo */ | |
| phy-addr = <0xffffffff>; /* appended from boardinfo */ | |
| txd0-skew-ps = <0>; /* appended from boardinfo */ | |
| txd1-skew-ps = <0>; /* appended from boardinfo */ | |
| txd2-skew-ps = <0>; /* appended from boardinfo */ | |
| txd3-skew-ps = <0>; /* appended from boardinfo */ | |
| rxd0-skew-ps = <420>; /* appended from boardinfo */ | |
| rxd1-skew-ps = <420>; /* appended from boardinfo */ | |
| rxd2-skew-ps = <420>; /* appended from boardinfo */ | |
| rxd3-skew-ps = <420>; /* appended from boardinfo */ | |
| txen-skew-ps = <0>; /* appended from boardinfo */ | |
| txc-skew-ps = <1860>; /* appended from boardinfo */ | |
| rxdv-skew-ps = <420>; /* appended from boardinfo */ | |
| rxc-skew-ps = <1680>; /* appended from boardinfo */ | |
| }; //end ethernet@0xff800000 (a10_hps_i_emac_emac0) | |
| a10_hps_i_emac_emac1: ethernet@0xff802000 { | |
| compatible = "synopsys,dwmac-17.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| reg = <0xff802000 0x00002000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 93 4>; | |
| clocks = <&l4_mp_clk>; /* appended from boardinfo */ | |
| clock-names = "stmmaceth"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */ | |
| rx-fifo-depth = <16384>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */ | |
| snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */ | |
| snps,perfect-filter-entries = <128>; /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| tx-fifo-depth = <4096>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */ | |
| address-bits = <48>; | |
| max-frame-size = <1518>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| snps,axi-config = <&socfpga_axi_setup>; /* appended from boardinfo */ | |
| resets = <&a10_hps_i_rst_mgr_rstmgr 33>; /* appended from boardinfo */ | |
| reset-names = "stmmaceth"; /* appended from boardinfo */ | |
| altr,sysmgr-syscon = <&a10_hps_i_sys_mgr_core 0x00000048 0>; /* appended from boardinfo */ | |
| }; //end ethernet@0xff802000 (a10_hps_i_emac_emac1) | |
| a10_hps_i_emac_emac2: ethernet@0xff804000 { | |
| compatible = "synopsys,dwmac-17.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| reg = <0xff804000 0x00002000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 94 4>; | |
| clocks = <&l4_mp_clk>; /* appended from boardinfo */ | |
| clock-names = "stmmaceth"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| interrupt-names = "macirq"; /* embeddedsw.dts.params.interrupt-names type STRING */ | |
| rx-fifo-depth = <16384>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */ | |
| snps,multicast-filter-bins = <256>; /* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */ | |
| snps,perfect-filter-entries = <128>; /* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| tx-fifo-depth = <4096>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */ | |
| address-bits = <48>; | |
| max-frame-size = <1518>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| snps,axi-config = <&socfpga_axi_setup>; /* appended from boardinfo */ | |
| resets = <&a10_hps_i_rst_mgr_rstmgr 34>; /* appended from boardinfo */ | |
| reset-names = "stmmaceth"; /* appended from boardinfo */ | |
| altr,sysmgr-syscon = <&a10_hps_i_sys_mgr_core 0x0000004c 0>; /* appended from boardinfo */ | |
| }; //end ethernet@0xff804000 (a10_hps_i_emac_emac2) | |
| a10_hps_i_spim_0_spim: spi@0xffda4000 { | |
| compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi"; | |
| reg = <0xffda4000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 103 4>; | |
| clocks = <&spi_m_clk>; | |
| #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */ | |
| #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */ | |
| bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */ | |
| num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end spi@0xffda4000 (a10_hps_i_spim_0_spim) | |
| a10_hps_i_spim_1_spim: spi@0xffda5000 { | |
| compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi"; | |
| reg = <0xffda5000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0x00000000 0x00000066 0x00000004>; /* appended from boardinfo */ | |
| clocks = <&spi_m_clk>; | |
| #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */ | |
| #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */ | |
| bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */ | |
| num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| tx-dma-channel = <&a10_hps_i_dma_DMASECURE 0x00000010>; /* appended from boardinfo */ | |
| rx-dma-channel = <&a10_hps_i_dma_DMASECURE 0x00000011>; /* appended from boardinfo */ | |
| 32bit_access; /* appended from boardinfo */ | |
| a10_sysctl: a10_sysctl@0 { | |
| compatible = "altr,a10sycon"; /* appended from boardinfo */ | |
| reg = <0>; /* appended from boardinfo */ | |
| interrupt-parent = <&a10_hps_i_gpio_1_gpio>; /* appended from boardinfo */ | |
| interrupts = <5 8>; /* appended from boardinfo */ | |
| interrupt-controller; /* appended from boardinfo */ | |
| #interrupt-cells = <2>; /* appended from boardinfo */ | |
| spi-max-frequency = <1000000>; /* appended from boardinfo */ | |
| gpio4: gpio-controller { | |
| compatible = "altr,a10sycon-gpio"; /* appended from boardinfo */ | |
| gpio-controller; /* appended from boardinfo */ | |
| #gpio-cells = <2>; /* appended from boardinfo */ | |
| ngpios = <16>; /* appended from boardinfo */ | |
| }; //end gpio-controller (gpio4) | |
| }; //end a10_sysctl@0 (a10_sysctl) | |
| }; //end spi@0xffda5000 (a10_hps_i_spim_1_spim) | |
| a10_hps_i_spis_0_spis: spi@0xffda2000 { | |
| compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi"; | |
| reg = <0xffda2000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 101 4>; | |
| clocks = <&l4_mp_clk>; | |
| #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */ | |
| #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */ | |
| bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */ | |
| num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end spi@0xffda2000 (a10_hps_i_spis_0_spis) | |
| a10_hps_i_spis_1_spis: spi@0xffda3000 { | |
| compatible = "snps,dw-spi-mmio-17.0", "snps,dw-spi-mmio", "snps,dw-apb-ssi"; | |
| reg = <0xffda3000 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 102 4>; | |
| clocks = <&l4_mp_clk>; | |
| #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */ | |
| #size-cells = <0>; /* embeddedsw.dts.params.#size-cells type NUMBER */ | |
| bus-num = <0>; /* embeddedsw.dts.params.bus-num type NUMBER */ | |
| num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end spi@0xffda3000 (a10_hps_i_spis_1_spis) | |
| a10_hps_i_i2c_0_i2c: i2c@0xffc02200 { | |
| compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; | |
| reg = <0xffc02200 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 105 4>; | |
| clocks = <&l4_sp_clk>; | |
| emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end i2c@0xffc02200 (a10_hps_i_i2c_0_i2c) | |
| a10_hps_i_i2c_1_i2c: i2c@0xffc02300 { | |
| compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; | |
| reg = <0xffc02300 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 106 4>; | |
| clocks = <&l4_sp_clk>; | |
| emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| speed-mode = <0>; /* appended from boardinfo */ | |
| clock-frequency = <100000>; /* appended from boardinfo */ | |
| i2c-sda-falling-time-ns = <6000>; /* appended from boardinfo */ | |
| i2c-scl-falling-time-ns = <6000>; /* appended from boardinfo */ | |
| lcd: newhaven,nhd-0216k3z-nsw-bbw@0x28 { | |
| compatible = "newhaven,nhd-0216k3z-nsw-bbw"; | |
| reg = <0x00000028>; | |
| height = <2>; /* appended from boardinfo */ | |
| width = <16>; /* appended from boardinfo */ | |
| brightness = <8>; /* appended from boardinfo */ | |
| }; //end newhaven,nhd-0216k3z-nsw-bbw@0x28 (lcd) | |
| eeprom: atmel,24c32@0x51 { | |
| compatible = "atmel,24c32"; | |
| reg = <0x00000051>; | |
| pagesize = <32>; /* appended from boardinfo */ | |
| }; //end atmel,24c32@0x51 (eeprom) | |
| rtc: dallas,ds1339@0x68 { | |
| compatible = "dallas,ds1339"; | |
| reg = <0x00000068>; | |
| }; //end dallas,ds1339@0x68 (rtc) | |
| }; //end i2c@0xffc02300 (a10_hps_i_i2c_1_i2c) | |
| a10_hps_i_i2c_emac_0_i2c: i2c@0xffc02400 { | |
| compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; | |
| reg = <0xffc02400 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 107 4>; | |
| clocks = <&l4_sp_clk>; | |
| emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end i2c@0xffc02400 (a10_hps_i_i2c_emac_0_i2c) | |
| a10_hps_i_i2c_emac_1_i2c: i2c@0xffc02500 { | |
| compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; | |
| reg = <0xffc02500 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 108 4>; | |
| clocks = <&l4_sp_clk>; | |
| emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end i2c@0xffc02500 (a10_hps_i_i2c_emac_1_i2c) | |
| a10_hps_i_i2c_emac_2_i2c: i2c@0xffc02600 { | |
| compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; | |
| reg = <0xffc02600 0x00000100>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 109 4>; | |
| clocks = <&l4_sp_clk>; | |
| emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| }; //end i2c@0xffc02600 (a10_hps_i_i2c_emac_2_i2c) | |
| a10_hps_i_qspi_QSPIDATA: flash@0xff809000 { | |
| compatible = "cadence,qspi-17.0", "cadence,qspi", "cdns,qspi-nor"; | |
| reg = <0xff809000 0x00000100>, | |
| <0xffa00000 0x00000100>; | |
| reg-names = "axi_slave0", "axi_slave1"; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 100 4>; | |
| clocks = <&qspi_clk>; /* appended from boardinfo */ | |
| bus-num = <2>; /* embeddedsw.dts.params.bus-num type NUMBER */ | |
| fifo-depth = <128>; /* embeddedsw.dts.params.fifo-depth type NUMBER */ | |
| num-chipselect = <4>; /* embeddedsw.dts.params.num-chipselect type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| bank-width = <2>; | |
| device-width = <1>; | |
| #address-cells = <1>; /* appended from boardinfo */ | |
| #size-cells = <0>; /* appended from boardinfo */ | |
| ext-decoder = <0>; /* appended from boardinfo */ | |
| flash0: n25q00@0 { | |
| #address-cells = <1>; /* appended from boardinfo */ | |
| #size-cells = <1>; /* appended from boardinfo */ | |
| compatible = "n25q00aa"; /* appended from boardinfo */ | |
| reg = <0>; /* appended from boardinfo */ | |
| spi-max-frequency = <50000000>; /* appended from boardinfo */ | |
| m25p,fast-read; /* appended from boardinfo */ | |
| page-size = <256>; /* appended from boardinfo */ | |
| block-size = <16>; /* appended from boardinfo */ | |
| tshsl-ns = <50>; /* appended from boardinfo */ | |
| tsd2d-ns = <50>; /* appended from boardinfo */ | |
| tchsh-ns = <4>; /* appended from boardinfo */ | |
| tslch-ns = <4>; /* appended from boardinfo */ | |
| cdns,page-size = <256>; /* appended from boardinfo */ | |
| cdns,block-size = <16>; /* appended from boardinfo */ | |
| cdns,tshsl-ns = <50>; /* appended from boardinfo */ | |
| cdns,tsd2d-ns = <50>; /* appended from boardinfo */ | |
| cdns,tchsh-ns = <4>; /* appended from boardinfo */ | |
| cdns,tslch-ns = <4>; /* appended from boardinfo */ | |
| part0: partition@0 { | |
| label = "Boot and FPGA data"; /* appended from boardinfo */ | |
| reg = <0x00000000 0x03020000>; /* appended from boardinfo */ | |
| }; //end partition@0 (part0) | |
| part1: partition@3020000 { | |
| label = "Root Filesystem - JFFS2"; /* appended from boardinfo */ | |
| reg = <0x03020000 0x04fe0000>; /* appended from boardinfo */ | |
| }; //end partition@3020000 (part1) | |
| }; //end n25q00@0 (flash0) | |
| }; //end flash@0xff809000 (a10_hps_i_qspi_QSPIDATA) | |
| a10_hps_i_sdmmc_sdmmc: flash@0xff808000 { | |
| compatible = "snps,mmc-17.0", "altr,socfpga-dw-mshc"; | |
| reg = <0xff808000 0x00001000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 98 4>; | |
| clocks = <&l4_mp_clk &sdmmc_clk>; | |
| clock-names = "biu", "ciu"; | |
| fifo-depth = <1024>; /* embeddedsw.dts.params.fifo-depth type NUMBER */ | |
| num-slots = <1>; /* embeddedsw.dts.params.num-slots type NUMBER */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| bank-width = <2>; | |
| device-width = <1>; | |
| supports-highspeed; /* appended from boardinfo */ | |
| broken-cd; /* appended from boardinfo */ | |
| cap-sd-highspeed; /* appended from boardinfo */ | |
| altr,dw-mshc-ciu-div = <3>; /* appended from boardinfo */ | |
| altr,dw-mshc-sdr-timing = <0 3>; /* appended from boardinfo */ | |
| pwr-en = <0>; /* appended from boardinfo */ | |
| #address-cells = <1>; /* appended from boardinfo */ | |
| #size-cells = <0>; /* appended from boardinfo */ | |
| bus-width = <4>; /* appended from boardinfo */ | |
| slot0: slot@0 { | |
| reg = <0>; /* appended from boardinfo */ | |
| bus-width = <4>; /* appended from boardinfo */ | |
| }; //end slot@0 (slot0) | |
| }; //end flash@0xff808000 (a10_hps_i_sdmmc_sdmmc) | |
| a10_hps_i_nand_NANDDATA: flash@0xffb90000 { | |
| compatible = "denali,nand-17.0", "denali,denali-nand-dt"; | |
| reg = <0xffb90000 0x00010000>, | |
| <0xffb80000 0x00010000>; | |
| reg-names = "nand_data", "denali_reg"; /* embeddedsw.dts.params.reg-names type STRING */ | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 99 4>; | |
| clocks = <&l4_mp_clk>; | |
| #address-cells = <1>; /* embeddedsw.dts.params.#address-cells type NUMBER */ | |
| #size-cells = <1>; /* embeddedsw.dts.params.#size-cells type NUMBER */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| bank-width = <2>; | |
| device-width = <1>; | |
| dma-mask = <0xffffffff>; /* appended from boardinfo */ | |
| have-hw-ecc-fixup; /* appended from boardinfo */ | |
| nand_part0: partition@0 { | |
| label = "Boot and FPGA data"; /* appended from boardinfo */ | |
| reg = <0x00000000 0x03020000>; /* appended from boardinfo */ | |
| }; //end partition@0 (nand_part0) | |
| nand_part1: partition@3020000 { | |
| label = "Root Filesystem - JFFS2"; /* appended from boardinfo */ | |
| reg = <0x03020000 0x04fe0000>; /* appended from boardinfo */ | |
| }; //end partition@3020000 (nand_part1) | |
| }; //end flash@0xffb90000 (a10_hps_i_nand_NANDDATA) | |
| a10_hps_i_usbotg_0_globgrp: usb@0xffb00000 { | |
| compatible = "snps,dwc-otg-17.0", "snps,dwc-otg", "snps,dwc2"; | |
| reg = <0xffb00000 0x00040000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 95 4>; | |
| clocks = <&usb_clk>; | |
| clock-names = "otg"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| dev-nperio-tx-fifo-size = <4096>; /* embeddedsw.dts.params.dev-nperio-tx-fifo-size type NUMBER */ | |
| dev-perio-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-perio-tx-fifo-size type STRING */ | |
| dev-rx-fifo-size = <512>; /* embeddedsw.dts.params.dev-rx-fifo-size type NUMBER */ | |
| dev-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-tx-fifo-size type STRING */ | |
| dma-mask = <268435455>; /* embeddedsw.dts.params.dma-mask type NUMBER */ | |
| enable-dynamic-fifo = <1>; /* embeddedsw.dts.params.enable-dynamic-fifo type NUMBER */ | |
| host-nperio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-nperio-tx-fifo-size type NUMBER */ | |
| host-perio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-perio-tx-fifo-size type NUMBER */ | |
| host-rx-fifo-size = <2560>; /* embeddedsw.dts.params.host-rx-fifo-size type NUMBER */ | |
| phy-names = "usb2-phy"; /* embeddedsw.dts.params.phy-names type STRING */ | |
| status = "okay"; /* embeddedsw.dts.params.status type STRING */ | |
| ulpi-ddr = <0>; /* embeddedsw.dts.params.ulpi-ddr type NUMBER */ | |
| voltage-switch = <0>; /* embeddedsw.dts.params.voltage-switch type NUMBER */ | |
| phys = <&usbphy0>; /* appended from boardinfo */ | |
| }; //end usb@0xffb00000 (a10_hps_i_usbotg_0_globgrp) | |
| a10_hps_i_usbotg_1_globgrp: usb@0xffb40000 { | |
| compatible = "snps,dwc-otg-17.0", "snps,dwc-otg", "snps,dwc2"; | |
| reg = <0xffb40000 0x00040000>; | |
| interrupt-parent = <&a10_hps_arm_gic_0>; | |
| interrupts = <0 96 4>; | |
| clocks = <&usb_clk>; | |
| clock-names = "otg"; /* embeddedsw.dts.params.clock-names type STRING */ | |
| dev-nperio-tx-fifo-size = <4096>; /* embeddedsw.dts.params.dev-nperio-tx-fifo-size type NUMBER */ | |
| dev-perio-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-perio-tx-fifo-size type STRING */ | |
| dev-rx-fifo-size = <512>; /* embeddedsw.dts.params.dev-rx-fifo-size type NUMBER */ | |
| dev-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-tx-fifo-size type STRING */ | |
| dma-mask = <268435455>; /* embeddedsw.dts.params.dma-mask type NUMBER */ | |
| enable-dynamic-fifo = <1>; /* embeddedsw.dts.params.enable-dynamic-fifo type NUMBER */ | |
| host-nperio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-nperio-tx-fifo-size type NUMBER */ | |
| host-perio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-perio-tx-fifo-size type NUMBER */ | |
| host-rx-fifo-size = <2560>; /* embeddedsw.dts.params.host-rx-fifo-size type NUMBER */ | |
| phy-names = "usb2-phy"; /* embeddedsw.dts.params.phy-names type STRING */ | |
| status = "disabled"; /* embeddedsw.dts.params.status type STRING */ | |
| ulpi-ddr = <0>; /* embeddedsw.dts.params.ulpi-ddr type NUMBER */ | |
| voltage-switch = <0>; /* embeddedsw.dts.params.voltage-switch type NUMBER */ | |
| }; //end usb@0xffb40000 (a10_hps_i_usbotg_1_globgrp) | |
| a10_hps_scu: scu@0xffffc000 { | |
| compatible = "arm,corex-a9-scu-17.0", "arm,cortex-a9-scu"; | |
| reg = <0xffffc000 0x00000100>; | |
| }; //end scu@0xffffc000 (a10_hps_scu) | |
| pmu: pmu0 { | |
| #address-cells = <1>; /* appended from boardinfo */ | |
| #size-cells = <1>; /* appended from boardinfo */ | |
| compatible = "arm,cortex-a9-pmu"; /* appended from boardinfo */ | |
| interrupt-parent = <&a10_hps_arm_gic_0>; /* appended from boardinfo */ | |
| interrupts = <0 176 4 0 177 4>; /* appended from boardinfo */ | |
| ranges; /* appended from boardinfo */ | |
| cti0: cti0@ff118000 { | |
| compatible = "arm,coresight-cti"; /* appended from boardinfo */ | |
| reg = <0xff118000 0x00001000>; /* appended from boardinfo */ | |
| }; //end cti0@ff118000 (cti0) | |
| cti1: cti0@ff119000 { | |
| compatible = "arm,coresight-cti"; /* appended from boardinfo */ | |
| reg = <0xff119000 0x00001000>; /* appended from boardinfo */ | |
| }; //end cti0@ff119000 (cti1) | |
| }; //end pmu0 (pmu) | |
| socfpga_axi_setup: stmmac-axi-config { | |
| snps,wr_osr_lmt = <0x0000000f>; /* appended from boardinfo */ | |
| snps,rd_osr_lmt = <0x0000000f>; /* appended from boardinfo */ | |
| snps,blen = <0 0 0 0 16 0 0>; /* appended from boardinfo */ | |
| }; //end stmmac-axi-config (socfpga_axi_setup) | |
| usbphy0: usbphy0 { | |
| #phy-cells = <0>; /* appended from boardinfo */ | |
| compatible = "usb-nop-xceiv"; /* appended from boardinfo */ | |
| status = "okay"; /* appended from boardinfo */ | |
| }; //end usbphy0 (usbphy0) | |
| soc_leds: leds { | |
| compatible = "gpio-leds"; /* appended from boardinfo */ | |
| led_fpga0: fpga0 { | |
| label = "fpga_led0"; /* appended from boardinfo */ | |
| gpios = <&led_pio 0 1>; /* appended from boardinfo */ | |
| }; //end fpga0 (led_fpga0) | |
| led_fpga1: fpga1 { | |
| label = "fpga_led1"; /* appended from boardinfo */ | |
| gpios = <&led_pio 1 1>; /* appended from boardinfo */ | |
| }; //end fpga1 (led_fpga1) | |
| led_fpga2: fpga2 { | |
| label = "fpga_led2"; /* appended from boardinfo */ | |
| gpios = <&led_pio 2 1>; /* appended from boardinfo */ | |
| }; //end fpga2 (led_fpga2) | |
| led_fpga3: fpga3 { | |
| label = "fpga_led3"; /* appended from boardinfo */ | |
| gpios = <&led_pio 3 1>; /* appended from boardinfo */ | |
| }; //end fpga3 (led_fpga3) | |
| a10sycon0: a10sycon0 { | |
| label = "a10sycon_led0"; /* appended from boardinfo */ | |
| gpios = <&gpio4 4 1>; /* appended from boardinfo */ | |
| }; //end a10sycon0 (a10sycon0) | |
| a10sycon1: a10sycon1 { | |
| label = "a10sycon_led1"; /* appended from boardinfo */ | |
| gpios = <&gpio4 5 1>; /* appended from boardinfo */ | |
| }; //end a10sycon1 (a10sycon1) | |
| a10sycon2: a10sycon2 { | |
| label = "a10sycon_led2"; /* appended from boardinfo */ | |
| gpios = <&gpio4 6 1>; /* appended from boardinfo */ | |
| }; //end a10sycon2 (a10sycon2) | |
| a10sycon3: a10sycon3 { | |
| label = "a10sycon_led3"; /* appended from boardinfo */ | |
| gpios = <&gpio4 7 1>; /* appended from boardinfo */ | |
| }; //end a10sycon3 (a10sycon3) | |
| }; //end leds (soc_leds) | |
| }; //end sopc@0 (sopc0) | |
| chosen { | |
| bootargs = "debug console=ttyAL0,115200"; | |
| }; //end chosen | |
| }; //end / |
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