Debouncing-a-push-button-stuff

gistfile1.vhd

-- Pulse To Level
-- 
-- PulseToLevel.vhdl
--
-- Decription
--
-- Lab 3, EDA234
--
-- @author Fredrik Brosser
-- @date 2011-11-01
--

library ieee;
use ieee.std_logic_1164.all;

Entity PulseToLevel is
  port(
        clk    :   in   std_logic;
        rst    :   in   std_logic;
        setOn  :   in   std_logic;
        setOff :   in   std_logic;
        output :   out  std_logic
  );
end Entity;

Architecture PulseToLevel_bhv of PulseToLevel is
begin
  -- Combinatorial process
  Comb_P : process (rst, clk)
  begin
    if(rst = '1') then
      output <= '0';
    elsif(clk'Event and clk = '1') then
      if(setOn = '1') then
        output <= '1';
      elsif(setOff = '1') then
        output <= '0';
      end if;
    end if;
  end process;
end Architecture;

-- Level To Pulse
-- 
-- LevelToPulse.vhdl
--
-- Decription
--
-- Lab 3, EDA234
--
-- @author Fredrik Brosser
-- @date 2011-11-01
--

library ieee;
use ieee.std_logic_1164.all;

Entity LevelToPulse is
  port(
        clk   :   in    std_logic;
        rst   :   in    std_logic;
        input :   in    std_logic;
        pulse :   out   std_logic
  );
end Entity;

Architecture LevelToPulse_bhv of LevelToPulse is
  type stateType is (S0, S1, S2);
  signal state : stateType;
  signal nextState : stateType;
begin
  
  -- Synchronous process
  ASM_P : process (clk, rst)
  begin
    if(rst = '1') then
      state <= S0;
    elsif(clk'Event and clk = '1') then
      state <= nextState;
    end if;
  end process;

  -- Combinatorial process
  Comb_P : process (input, state)
  begin
    
    -- Default values
    pulse <= '0';
    nextState <= state;
    
    case state is
      
      -- Wait for positive flank on input
      when S0 =>
        if(input = '1') then
          nextState <= S1;
        end if;
        
      -- Give Pulse
      when S1 =>
        pulse <= '1';
        nextState <= S2;
        
      -- Wait for input to go down
      when S2 =>
        if(input = '0') then
          nextState <= S0;
        end if;
        
    end case;
  end process;
  
end Architecture;

-- Synchronization module
-- 
-- Sync.vhdl
--
-- Synchronizing an asynchronous input
-- signal using two D-flipflops
-- 
-- Lab 3, EDA234
--
-- @author Fredrik Brosser
-- @date 2011-11-01
--

library ieee;
use ieee.std_logic_1164.all;

Entity Sync is
  port(
        clk   :   in    std_logic;
        rst   :   in    std_logic;
        async :   in    std_logic;
        sync  :   out   std_logic
  );
end Entity;

Architecture Sync_bhv of Sync is
  
  signal temp_sync : std_logic;
  
begin
  Sync_P : process (clk, rst)
  begin
    
    -- Asynchronous Reset
    if(rst = '1') then
      temp_sync <= '0';
      sync <= '0';
      
    elsif(clk'Event and clk = '1') then
      temp_sync <= async;
      sync <= temp_sync;
    end if;
    
  end process;
end Architecture;