Simple DE0 pwm - verilog

README

PWM on the DE0 board

The pll is left out. Its 50MHz in, 1MHz out, generated by quartus

ledpwm.v

`define BITRANGE 20:10

module ledpwm 	(
					input inclk,
					input reset,
					output [7:0] leds
					);

	reg [20:0] counter;
	wire clk;
	
	pll pll0 (
				.areset(),
				.locked(),
				.inclk0(inclk),
				.c0 (clk)
				);
	
	pwm pwm0 (
			.clk (clk),
			.reset (reset),
			.out (leds[0]),
			.dutycycle (counter[`BITRANGE])
			);
			
	pwm pwm1 (
		.clk (clk),
		.reset (reset),
		.out (leds[1]),
		.dutycycle (counter[`BITRANGE])
		);
			
	always@ (posedge clk)
	begin
		if (!reset)		counter <= 15'b0;
		else 				counter <= counter + 1'b1;
	end

endmodule

pin planning

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.

To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair
inclk,Input,PIN_R8,3,B3_N0,PIN_R8,,,,,
leds[7],Output,,,,PIN_F3,,,,,
leds[6],Output,,,,PIN_B5,,,,,
leds[5],Output,,,,PIN_T12,,,,,
leds[4],Output,,,,PIN_L2,,,,,
leds[3],Output,,,,PIN_A12,,,,,
leds[2],Output,,,,PIN_L3,,,,,
leds[1],Output,PIN_A13,7,B7_N0,PIN_A13,,,,,
leds[0],Output,PIN_A15,7,B7_N0,PIN_A15,,,,,
reset,Input,PIN_E1,1,B1_N0,PIN_E1,,,,,

pwm.v

module	pwm (
					input clk,
					input reset,
					input [10:0] dutycycle,
					output out
				 );
				
	reg [10:0] counter;
	
	always @(posedge clk)
	begin
		if (!reset)	counter <= 1'b0;
		else 			counter <= counter + 1'b1;
	end
	
	assign out = (counter >= dutycycle);
	
endmodule