2023-10-08 FM4DD
These are my notes from analyzing the Cologne Chip Gatemate E1 DevBoard flash programming and flash boot operations, which I could not find (or overlooked) inside the Gatemate technical documentation. It answers the question what SPI protocol and speed is used during FPGA initialization from flash.
The Gatemate E1 board implements the Macronix MX25R6435F SPI Flash memory. The MX25R6435F is a 64Mbit (8MByte) Serial NOR Flash that can operate in multiple modes up to 80Mhz Quad SPI. Datasheet and details at: https://www.mxic.com.tw/en-us/products/NOR-Flash/Pages/Ultra-Low-Power-Flash.aspx