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Fabian Peddinghaus fpedd

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fpedd / memory-analyzer-concurrency-investigation.md
Created March 30, 2026 11:37
Memory Analyzer Concurrency Investigation — ALTO Compiler (Restructured)

Memory Analyzer Concurrency Investigation — ALTO Compiler

Memory Analyzer Concurrency Investigation

1. Context

The ALTO compiler's memory analyzer (memory_analyzer/) models execution as a single sequential timeline — it traverses TIR top-to-bottom, generating a flat OrderedEventSet of ENTER/EXIT events. This was correct for single-core, single-unit execution, but the new multicore + unit-sync infrastructure introduces two levels of concurrency that the analyzer cannot represent. The result: incorrect memory usage numbers, misleading visualization, and suboptimal decisions in downstream passes.

This document characterizes the problems, analyzes root causes and downstream impact, and explores the design space for solutions. Detailed solution design is deferred to a follow-up document.

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fpedd / memory_analyzer_concurrency_investigation.md
Last active March 30, 2026 11:49
Memory Analyzer Concurrency Investigation — Restructured

Memory Analyzer Concurrency Investigation

1. Context

The ALTO compiler's memory analyzer (passes/memory_analyzer/) models execution as a single sequential timeline. It traverses TIR top-to-bottom, generating a flat OrderedEventSet of ENTER/EXIT events. This was correct for single-core, single-unit execution, but the new multicore + sync infrastructure introduces concurrency that the analyzer cannot represent.

This document characterizes the problems — what is wrong, why it is wrong, and what is affected. Solutions are deferred to a follow-up document.

Relates-To: SDK-8790