Created
June 19, 2023 18:44
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RISC-V Base Instruction Set v2.2 ASCII
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| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | |
| +------------------------------------------------------------------------------------------------+ | |
| | funct7 | rs2 | rs1 | funct3 | rd | opcode | R-type | |
| | imm[11:0] | rs1 | funct3 | rd | opcode | I-type | |
| | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode | S-type | |
| | imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode | B-type | |
| | imm[31:12] | rd | opcode | U-type | |
| | imm[20|10:1|11|19:12] | rd | opcode | J-type | |
| +------------------------------------------------------------------------------------------------+ | |
| +------------------------------------------------------------------------------------------------+ | |
| | imm[31:12] | rd | 0110111 | LUI | |
| | imm[31:12] | rd | 0010111 | AUIPC | |
| | imm[20|10:1|11|19:12] | rd | 1101111 | JAL | |
| | imm[11:0] | rs1 | 000 | rd | 1100111 | JALR | |
| | imm[12|10:5] | rs2 | rs1 | 000 | imm[4:1|11] | 1100011 | BEQ | |
| | imm[12|10:5] | rs2 | rs1 | 001 | imm[4:1|11] | 1100011 | BNE | |
| | imm[12|10:5] | rs2 | rs1 | 100 | imm[4:1|11] | 1100011 | BLT | |
| | imm[12|10:5] | rs2 | rs1 | 101 | imm[4:1|11] | 1100011 | BGE | |
| | imm[12|10:5] | rs2 | rs1 | 110 | imm[4:1|11] | 1100011 | BLTU | |
| | imm[12|10:5] | rs2 | rs1 | 111 | imm[4:1|11] | 1100011 | BGEU | |
| | imm[11:0] | rs1 | 000 | rd | 0000011 | LB | |
| | imm[11:0] | rs1 | 001 | rd | 0000011 | LH | |
| | imm[11:0] | rs1 | 010 | rd | 0000011 | LW | |
| | imm[11:0] | rs1 | 100 | rd | 0000011 | LBU | |
| | imm[11:0] | rs1 | 101 | rd | 0000011 | LHU | |
| | imm[11:5] | rs2 | rs1 | 000 | imm[4:0] | 0100011 | SB | |
| | imm[11:5] | rs2 | rs1 | 001 | imm[4:0] | 0100011 | SH | |
| | imm[11:5] | rs2 | rs1 | 010 | imm[4:0] | 0100011 | SW | |
| | imm[11:0] | rs1 | 000 | rd | 0010011 | ADDI | |
| | imm[11:0] | rs1 | 010 | rd | 0010011 | SLTI | |
| | imm[11:0] | rs1 | 011 | rd | 0010011 | SLTIU | |
| | imm[11:0] | rs1 | 100 | rd | 0010011 | XORI | |
| | imm[11:0] | rs1 | 110 | rd | 0010011 | ORI | |
| | imm[11:0] | rs1 | 111 | rd | 0010011 | ANDI | |
| | 0000000 | shamt | rs1 | 001 | rd | 0010011 | SLLI | |
| | 0000000 | shamt | rs1 | 101 | rd | 0010011 | SRLI | |
| | 0100000 | shamt | rs1 | 101 | rd | 0010011 | SRAI | |
| | 0000000 | rs2 | rs1 | 000 | rd | 0110011 | ADD | |
| | 0100000 | rs2 | rs1 | 000 | rd | 0110011 | SUB | |
| | 0000000 | rs2 | rs1 | 001 | rd | 0110011 | SLL | |
| | 0000000 | rs2 | rs1 | 010 | rd | 0110011 | SLT | |
| | 0000000 | rs2 | rs1 | 011 | rd | 0110011 | SLTU | |
| | 0000000 | rs2 | rs1 | 100 | rd | 0110011 | XOR | |
| | 0000000 | rs2 | rs1 | 101 | rd | 0110011 | SRL | |
| | 0100000 | rs2 | rs1 | 101 | rd | 0110011 | SRA | |
| | 0000000 | rs2 | rs1 | 110 | rd | 0110011 | OR | |
| | 0000000 | rs2 | rs1 | 111 | rd | 0110011 | AND | |
| | 0000 | pred | succ | 00000 | 000 | 00000 | 0001111 | FENCE | |
| | 0000 | 0000 | 0000 | 00000 | 001 | 00000 | 0001111 | FENCE.I | |
| | 000000000000 | 00000 | 000 | 00000 | 1110011 | ECALL | |
| | 000000000001 | 00000 | 000 | 00000 | 1110011 | EBREAK | |
| | csr | rs1 | 001 | rd | 1110011 | CSRRW | |
| | csr | rs1 | 010 | rd | 1110011 | CSRRS | |
| | csr | rs1 | 011 | rd | 1110011 | CSRRC | |
| | csr | zimm | 101 | rd | 1110011 | CSRRWI | |
| | csr | zimm | 110 | rd | 1110011 | CSRRSI | |
| | csr | zimm | 111 | rd | 1110011 | CSRRCI | |
| +------------------------------------------------------------------------------------------------+ | |
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