test-myhdl.py

from myhdl import always, always_comb, always_seq, Signal, ResetSignal, toVerilog, toVHDL, delay, traceSignals, Simulation, now, intbv, concat

def chenillar(clk, reset, leds, direction):
  @always(clk.posedge)
  def scroll():
    if bool(direction):
       leds.next = leds >> 1
       if leds == 0b1:
         direction.next = 0
    else:
       leds.next = leds << 1
       if leds == 0b10000000:
         direction.next = 1
  return scroll


def convert():
  clk = Signal(False)
  direction = Signal(False)
  reset = ResetSignal(False, True, async=True)
  leds = Signal(intbv(0,0,0b100000000))
  toVerilog.timescale = "100ms/1ms"
  toVerilog(chenillar, clk, reset, leds, direction)

convert()